bus: re-organize the directory structure

src/main/scala/memory/AXI4.scala → src/main/scala/bus/axi4/AXI4.scala

 // See LICENSE.SiFive for license details.
 
-package memory
+package bus.axi4
 
 import chisel3._
 import chisel3.util._
@@ -83,56 +83,3 @@ class AXI4 extends Bundle {
   val ar = Decoupled(new AXI4BundleAR)
   val r  = Flipped(Decoupled(new AXI4BundleR))
 }
-
-class SimpleBus2AXI4Converter extends Module {
-  val io = IO(new Bundle {
-    val in = Flipped(new SimpleBus)
-    val out = new AXI4
-  })
-
-  val mem = io.in
-  val axi = io.out
-
-  val ar = axi.ar.bits
-  val aw = axi.aw.bits
-  val w  = axi.w.bits
-  val r  = axi.r.bits
-  val b  = axi.b.bits
-
-  ar.id    := 0.U
-  ar.addr  := mem.a.bits.addr
-  ar.len   := 0.U  // single beat
-  ar.size  := mem.a.bits.size
-  ar.burst := AXI4Parameters.BURST_INCR
-  ar.lock  := false.B
-  ar.cache := 0.U
-  ar.prot  := AXI4Parameters.PROT_PRIVILEDGED
-  ar.qos   := 0.U
-  ar.user  := 0.U
-  aw := ar
-  w.data := mem.w.bits.data
-  w.strb := mem.w.bits.mask
-  w.last := true.B
-  mem.r.bits.data := r.data
-
-  val awAck = RegInit(false.B)
-  val wAck = RegInit(false.B)
-
-  val wSend = (axi.aw.fire() && axi.w.fire()) || (awAck && wAck)
-  when (wSend) {
-    awAck := false.B
-    wAck := false.B
-  }
-  .elsewhen (axi.aw.fire()) { awAck := true.B }
-  .elsewhen (axi. w.fire()) {  wAck := true.B }
-
-  axi.ar.valid := mem.isRead()
-  axi.aw.valid := mem.isWrite() && !awAck
-  axi.w .valid := mem.isWrite() && !wAck
-  mem.a.ready  := Mux(mem.w.valid, wSend, axi.ar.ready)
-
-  axi.r.ready  := mem.r.ready
-  mem.r.valid  := axi.r.valid
-
-  axi.b.ready  := true.B
-}

src/main/scala/memory/AXI4RAM.scala → src/main/scala/bus/axi4/AXI4RAM.scala

 // See LICENSE.SiFive for license details.
 
-package memory
+package bus.axi4
 
 import chisel3._
 import chisel3.util._

src/main/scala/memory/Delayer.scala → src/main/scala/bus/axi4/Delayer.scala

 // See LICENSE.SiFive for license details.
 
-package memory
+package bus.axi4
 
 import chisel3._
 import chisel3.util._

src/main/scala/memory/DistributedMem.scala → src/main/scala/bus/simplebus/DistributedMem.scala

-package memory
+package bus.simplebus
 
 import chisel3._
 import chisel3.util._

src/main/scala/memory/SimpleBus.scala → src/main/scala/bus/simplebus/SimpleBus.scala

-package memory
+package bus.simplebus
 
 import chisel3._
 import chisel3.util._
@@ -24,7 +24,7 @@ class SimpleBus(val dataBits: Int = 32) extends Bundle {
   def isRead (): Bool = a.valid && !w.valid
   def isWrite(): Bool = a.valid &&  w.valid
 
-  def toAXI4(): AXI4 = {
+  def toAXI4() = {
     val mem2axi = Module(new SimpleBus2AXI4Converter)
     mem2axi.io.in <> this
     mem2axi.io.out

src/main/scala/bus/simplebus/ToAXI4.scala

+package bus.simplebus
+
+import chisel3._
+import chisel3.util._
+
+import bus.axi4._
+
+class SimpleBus2AXI4Converter extends Module {
+  val io = IO(new Bundle {
+    val in = Flipped(new SimpleBus)
+    val out = new AXI4
+  })
+
+  val mem = io.in
+  val axi = io.out
+
+  val ar = axi.ar.bits
+  val aw = axi.aw.bits
+  val w  = axi.w.bits
+  val r  = axi.r.bits
+  val b  = axi.b.bits
+
+  ar.id    := 0.U
+  ar.addr  := mem.a.bits.addr
+  ar.len   := 0.U  // single beat
+  ar.size  := mem.a.bits.size
+  ar.burst := AXI4Parameters.BURST_INCR
+  ar.lock  := false.B
+  ar.cache := 0.U
+  ar.prot  := AXI4Parameters.PROT_PRIVILEDGED
+  ar.qos   := 0.U
+  ar.user  := 0.U
+  aw := ar
+  w.data := mem.w.bits.data
+  w.strb := mem.w.bits.mask
+  w.last := true.B
+  mem.r.bits.data := r.data
+
+  val awAck = RegInit(false.B)
+  val wAck = RegInit(false.B)
+
+  val wSend = (axi.aw.fire() && axi.w.fire()) || (awAck && wAck)
+  when (wSend) {
+    awAck := false.B
+    wAck := false.B
+  }
+  .elsewhen (axi.aw.fire()) { awAck := true.B }
+  .elsewhen (axi. w.fire()) {  wAck := true.B }
+
+  axi.ar.valid := mem.isRead()
+  axi.aw.valid := mem.isWrite() && !awAck
+  axi.w .valid := mem.isWrite() && !wAck
+  mem.a.ready  := Mux(mem.w.valid, wSend, axi.ar.ready)
+
+  axi.r.ready  := mem.r.ready
+  mem.r.valid  := axi.r.valid
+
+  axi.b.ready  := true.B
+}

src/main/scala/device/AXI4Timer.scala

@@ -5,7 +5,7 @@ package device
 import chisel3._
 import chisel3.util._
 
-import memory.{AXI4, AXI4Parameters}
+import bus.axi4.{AXI4, AXI4Parameters}
 
 class AXI4Timer() extends Module {
   val io = IO(new Bundle{

src/main/scala/gpu/GPU.scala

@@ -3,7 +3,7 @@ package gpu
 import chisel3._
 import chisel3.util._
 
-import memory.SimpleBus
+import bus.simplebus.SimpleBus
 
 class PixelBundle extends Bundle {
   val a = UInt(8.W)

src/main/scala/noop/EXU.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 
 import utils._
-import memory.SimpleBus
+import bus.simplebus.SimpleBus
 
 class EXU extends Module with HasFuType {
   val io = IO(new Bundle {

src/main/scala/noop/ICache.scala

@@ -3,7 +3,7 @@ package noop
 import chisel3._
 import chisel3.util._
 
-import memory.SimpleBus
+import bus.simplebus.SimpleBus
 import utils._
 
 class ICache extends Module {

src/main/scala/noop/IFU.scala

@@ -3,8 +3,8 @@ package noop
 import chisel3._
 import chisel3.util._
 
-import memory.SimpleBus
 import utils._
+import bus.simplebus.SimpleBus
 
 trait HasResetVector {
   val resetVector = 0x80100000L

src/main/scala/noop/NOOP.scala

@@ -3,7 +3,7 @@ package noop
 import chisel3._
 import chisel3.util._
 
-import memory.SimpleBus
+import bus.simplebus.SimpleBus
 
 trait NOOPConfig {
   val HasIcache = true

src/main/scala/noop/fu/LSU.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 
 import utils._
-import memory.SimpleBus
+import bus.simplebus.SimpleBus
 
 trait HasLSUOpType {
   val LsuOpTypeNum  = 10

src/main/scala/top/TopMain.scala

 package top
 
 import noop.NOOP
-import memory.AXI4
+import bus.axi4.AXI4
 import device.AXI4Timer
 
 import chisel3._

src/test/scala/top/NOOPSim.scala

@@ -5,7 +5,8 @@ import noop._
 import chisel3._
 import chisel3.util._
 
-import memory.{AXI4RAM, AXI4Parameters, SimpleBus2AXI4Converter, AXI4Delayer}
+import bus.axi4._
+import bus.simplebus.SimpleBus2AXI4Converter
 
 class NOOPSimTop(memInitFile: String = "") extends Module {
   val io = IO(new Bundle{

src/test/scala/top/SimMMIO.scala

@@ -3,7 +3,7 @@ package top
 import chisel3._
 import chisel3.util._
 
-import memory.SimpleBus
+import bus.simplebus.SimpleBus
 
 class SimMMIO extends Module {
   val io = IO(new Bundle {