noop,fu: use Module for LSU

src/main/scala/noop/EXU.scala

@@ -39,10 +39,11 @@ class EXU extends Module with HasFuType {
   bru.io.offset := src2
   bru.io.out.ready := true.B
 
-  val lsu = new LSU
-  val (dmem, lsuResultValid) = lsu.access(isLsu = fuType === FuLsu, base = src1, offset = src2,
-    func = fuOpType, wdata = io.in.bits.data.dest)
-  io.dmem <> dmem
+  val lsu = Module(new LSU)
+  val lsuOut = lsu.access(valid = (fuType === FuLsu), src1 = src1, src2 = src2, func = fuOpType)
+  lsu.io.wdata := io.in.bits.data.dest
+  io.dmem <> lsu.io.dmem
+  lsu.io.out.ready := true.B
 
   val mdu = Module(new MDU)
   val mduOut = mdu.access(valid = (fuType === FuMdu), src1 = src1, src2 = src2, func = fuOpType)
@@ -59,7 +60,7 @@ class EXU extends Module with HasFuType {
   io.out.bits.data.dest := LookupTree(fuType, 0.U, List(
     FuAlu -> aluOut,
     FuBru -> bruOut,
-    FuLsu -> lsu.rdataExt(io.dmem.r.bits.data, io.dmem.a.bits.addr, fuOpType),
+    FuLsu -> lsuOut,
     FuCsr -> csrOut,
     FuMdu -> mduOut
   ))
@@ -73,7 +74,7 @@ class EXU extends Module with HasFuType {
     o.rfDest := i.rfDest
   }
   io.out.bits.pc := io.in.bits.pc
-  io.out.valid := io.in.valid && ((fuType =/= FuLsu) || lsuResultValid)
+  io.out.valid := io.in.valid && ((fuType =/= FuLsu) || lsu.io.out.valid)
 
   csr.io.instrCommit := io.csrCtrl.instrCommit
 }

src/main/scala/noop/fu/LSU.scala

@@ -40,7 +40,23 @@ object LSUInstr extends HasDecodeConst {
   )
 }
 
-class LSU extends HasLSUOpType {
+class LSUIO extends FunctionUnitIO {
+  val wdata = Input(UInt(32.W))
+  val dmem = new MemIO
+}
+
+class LSU extends Module with HasLSUOpType {
+  val io = IO(new LSUIO)
+
+  val (valid, src1, src2, func) = (io.in.valid, io.in.bits.src1, io.in.bits.src2, io.in.bits.func)
+  def access(valid: Bool, src1: UInt, src2: UInt, func: UInt): UInt = {
+    this.valid := valid
+    this.src1 := src1
+    this.src2 := src2
+    this.func := func
+    io.out.bits
+  }
+
   def genWmask(addr: UInt, sizeEncode: UInt): UInt = {
     LookupTree(sizeEncode, List(
       "b00".U -> 0x1.U,
@@ -55,44 +71,46 @@ class LSU extends HasLSUOpType {
       "b10".U -> data
     ))
   }
-  def access(isLsu: Bool, base: UInt, offset: UInt, func: UInt, wdata: UInt): (MemIO, Bool) = {
-    val dmem = Wire(new MemIO)
-    val s_idle :: s_wait_resp :: Nil = Enum(2)
-    val state = RegInit(s_idle)
-
-    switch (state) {
-      is (s_idle) {
-        when (dmem.a.fire()) { state := Mux(dmem.w.valid || dmem.r.fire(), s_idle, s_wait_resp) }
-      }
-
-      is (s_wait_resp) {
-        when (dmem.r.fire()) { state := s_idle }
-      }
-    }
 
-    dmem.a.bits.addr := base + offset
-    dmem.a.bits.size := func(1, 0)
-    dmem.a.valid := isLsu && (state === s_idle)
-    dmem.w.valid := isLsu && func(3)
-    dmem.w.bits.data := genWdata(wdata, func(1, 0))
-    dmem.w.bits.mask := genWmask(base + offset, func(1, 0))
-    dmem.r.ready := true.B
+  val dmem = io.dmem
+  val addr = src1 + src2
+
+  val s_idle :: s_wait_resp :: Nil = Enum(2)
+  val state = RegInit(s_idle)
+
+  switch (state) {
+    is (s_idle) {
+      when (dmem.a.fire()) { state := Mux(dmem.w.valid || dmem.r.fire(), s_idle, s_wait_resp) }
+    }
 
-    (dmem, Mux(dmem.w.valid, dmem.a.fire(), dmem.r.fire()))
+    is (s_wait_resp) {
+      when (dmem.r.fire()) { state := s_idle }
+    }
   }
-  def rdataExt(rdataFromBus: UInt, addr: UInt, func: UInt): UInt = {
-    val rdata = LookupTree(addr(1, 0), List(
-      "b00".U -> rdataFromBus,
-      "b01".U -> rdataFromBus(15, 8),
-      "b10".U -> rdataFromBus(31, 16),
-      "b11".U -> rdataFromBus(31, 24)
-    ))
-    LookupTree(func, List(
+
+  dmem.a.bits.addr := addr
+  dmem.a.bits.size := func(1, 0)
+  dmem.a.valid := valid && (state === s_idle)
+  dmem.w.valid := valid && func(3)
+  dmem.w.bits.data := genWdata(io.wdata, func(1, 0))
+  dmem.w.bits.mask := genWmask(addr, func(1, 0))
+  dmem.r.ready := true.B
+
+  io.out.valid := Mux(dmem.w.valid, dmem.a.fire(), dmem.r.fire())
+  io.in.ready := (state === s_idle)
+
+  val rdataFromBus = io.dmem.r.bits.data
+  val rdata = LookupTree(addr(1, 0), List(
+    "b00".U -> rdataFromBus,
+    "b01".U -> rdataFromBus(15, 8),
+    "b10".U -> rdataFromBus(31, 16),
+    "b11".U -> rdataFromBus(31, 24)
+  ))
+  io.out.bits := LookupTree(func, List(
       LsuLb   -> Cat(Fill(24, rdata(7)), rdata(7, 0)),
       LsuLh   -> Cat(Fill(16, rdata(15)), rdata(15, 0)),
       LsuLw   -> rdata,
       LsuLbu  -> Cat(0.U(24.W), rdata(7, 0)),
       LsuLhu  -> Cat(0.U(16.W), rdata(15, 0))
-    ))
-  }
+  ))
 }