BPU: Add more perf counters

src/main/scala/xiangshan/decoupled-frontend/BPU.scala

@@ -353,11 +353,14 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
   val s1_takenOnBr  = resp.s1.preds.real_br_taken_mask.asUInt =/= 0.U
   val s1_predicted_ghist = s1_ghist.update(s1_sawNTBr, s1_takenOnBr)
 
+  XSDebug(p"s1_sawNTBR=${s1_sawNTBr}, resp.s1.hit=${resp.s1.hit}, is_br=${Binary(resp.s1.preds.is_br.asUInt)}, taken_mask=${Binary(resp.s1.preds.taken_mask.asUInt)}\n")
+  XSDebug(p"s1_takenOnBr=$s1_takenOnBr, real_taken_mask=${Binary(resp.s1.preds.real_taken_mask.asUInt)}\n")
+  XSDebug(p"s1_predicted_ghist=${Binary(s1_predicted_ghist.asUInt)}\n")
   // when(s1_valid) {
   //   s0_ghist := s1_predicted_ghist
   // }
 
-  when(s1_fire) {
+  when(s1_valid) {
     s0_pc := resp.s1.preds.target
     s0_ghist := s1_predicted_ghist
   }
@@ -375,9 +378,17 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
       s0_ghist := s2_predicted_ghist
       s2_redirect := true.B
       s0_pc := resp.s2.preds.target
+      XSDebug(p"s1_valid=$s1_valid, s1_pc=${Hexadecimal(s1_pc)}, s2_resp_target=${Hexadecimal(resp.s2.preds.target)}\n")
+      XSDebug(p"s2_correct_s1_ghist=$s2_correct_s1_ghist\n")
+      XSDebug(p"s1_ghist=${Binary(s1_ghist.predHist)}\n")
+      XSDebug(p"s2_predicted_ghist=${Binary(s2_predicted_ghist.predHist)}\n")
     }
   }
 
+  XSPerfAccumulate("s2_redirect_because_s1_not_valid", s2_fire && !s1_valid)
+  XSPerfAccumulate("s2_redirect_because_target_diff", s2_fire && s1_valid && s1_pc =/= resp.s2.preds.target)
+  XSPerfAccumulate("s2_redirect_because_ghist_diff", s2_fire && s1_valid && s2_correct_s1_ghist)
+
   // s3
   val s3_sawNTBr = Mux(resp.s3.hit,
     resp.s3.preds.is_br.zip(resp.s3.preds.taken_mask).map{ case (b, t) => b && !t }.reduce(_||_),

src/main/scala/xiangshan/decoupled-frontend/FTB.scala

@@ -185,6 +185,9 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
     s2_target := Mux((io.in.bits.resp_in(0).s2.preds.taken_mask.asUInt & ftb_entry.brValids.asUInt) =/= 0.U,
       PriorityMux(io.in.bits.resp_in(0).s2.preds.taken_mask.asUInt & ftb_entry.brValids.asUInt, ftb_entry.brTargets),
       Mux(ftb_entry.jmpValid, ftb_entry.jmpTarget, fallThruAddr))
+
+    XSDebug("s2 FTB resp:\n")
+    XSDebug(p"$ftb_entry\n")
   }
 
   val s1_latch_call_is_rvc   = DontCare // TODO: modify when add RAS

src/main/scala/xiangshan/decoupled-frontend/uBTB.scala

@@ -77,7 +77,7 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
   {
     val brTargets = Vec(numBr, UInt(VAddrBits.W))
     val jmpTarget = UInt(VAddrBits.W)
-    val pftAddr   = UInt(log2Up(PredictWidth).W)
+    val pftAddr   = UInt((log2Up(PredictWidth)+1).W)
   }
 
   class ReadResp extends XSBundle
@@ -115,7 +115,8 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
     }
   }
 
-  override val meta_size = WireInit(0.U.asTypeOf(new MicroBTBMeta)).getWidth
+  // override val meta_size = WireInit(0.U.asTypeOf(new MicroBTBMeta)).getWidth
+  override val meta_size = WireInit(0.U.asTypeOf(Bool())).getWidth
 
   class UBTBBank(val nWays: Int) extends XSModule with BPUUtils {
     val io = IO(new Bundle {
@@ -126,6 +127,7 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
       val update_write_meta = Flipped(Valid(new MicroBTBMeta))
       val update_write_data = Flipped(Valid(new MicroBTBData))
       val update_taken_mask = Input(Vec(numBr, Bool()))
+      val update_mask = Input(UInt(numBr.W))
     })
 
     // val debug_io = IO(new Bundle {
@@ -214,7 +216,7 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
     val update_old_pred = update_hit_meta.pred
     val update_new_pred = VecInit(
       (0 until numBr).map { i =>
-        Mux(update_hit, satUpdate(update_old_pred(i), 2, io.update_taken_mask(i)),
+        Mux(update_hit && io.update_mask(i), satUpdate(update_old_pred(i), 2, io.update_taken_mask(i)),
           Mux(io.update_taken_mask(i), 3.U, 0.U))
       })
 
@@ -255,6 +257,9 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
   val banks = ubtbBanks.io
   val read_resps = banks.read_resp
 
+  XSDebug(p"uBTB entry, read_pc=${Hexadecimal(s1_pc)}\n")
+  XSDebug(p"v=${read_resps.valid}, brValids=${Binary(read_resps.brValids.asUInt)}, jmpValid=${read_resps.jmpValid}, pred0=${Binary(read_resps.pred(0).asUInt)}, pred1=${Binary(read_resps.pred(1).asUInt)}, hit=${read_resps.hit}\n")
+
   // io.in.ready := !io.flush.valid
 
   banks.read_pc.valid := io.s1_fire
@@ -264,10 +269,11 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
   io.out.resp := io.in.bits.resp_in(0)
   // io.out.resp.valids(0) := io.out.valid
   io.out.resp.s1.pc := s1_pc
-  io.out.s3_meta := RegEnable(RegEnable(read_resps.pred.asUInt(), io.s1_fire), io.s2_fire) // s3_meta
+  io.out.s3_meta := RegEnable(RegEnable(read_resps.hit.asUInt(), io.s1_fire), io.s2_fire) // s3_meta
   io.out.resp.s1.preds.target := Mux(banks.read_hit, read_resps.target, s1_pc + (FetchWidth*4).U)
   io.out.resp.s1.preds.taken_mask := read_resps.taken_mask
   io.out.resp.s1.preds.is_br := read_resps.brValids
+  io.out.resp.s1.preds.hit := banks.read_hit
   // io.out.bits.resp.s1.preds.is_jal := read_resps.jmpValid && !(read_resps.isCall || read_resps.isRet || read_resps.isJalr)
   // io.out.bits.resp.s1.preds.is_jalr := read_resps.jmpValid && read_resps.isJalr
   // io.out.bits.resp.s1.preds.is_call := read_resps.jmpValid && read_resps.isCall
@@ -315,6 +321,7 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
   banks.update_write_data.valid := data_write_valid
   banks.update_write_data.bits := update_write_datas
   banks.update_taken_mask := u_taken_mask
+  banks.update_mask := LowerMaskFromLowest(u_taken_mask.asUInt)
 
   if (debug) {
     XSDebug("req_v=%b, req_pc=%x, hit=%b\n", io.s1_fire, s1_pc, banks.read_hit)