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4ae36549
编写于
6月 28, 2020
作者:
Z
ZhangZifei
浏览文件
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电子邮件补丁
差异文件
Bru: implement BRU and only support jal/jalr && add Bru's log info
上级
e435c306
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
73 addition
and
6 deletion
+73
-6
src/main/scala/xiangshan/backend/exu/Bru.scala
src/main/scala/xiangshan/backend/exu/Bru.scala
+71
-0
src/main/scala/xiangshan/backend/exu/Exu.scala
src/main/scala/xiangshan/backend/exu/Exu.scala
+0
-4
src/main/scala/xiangshan/backend/package.scala
src/main/scala/xiangshan/backend/package.scala
+2
-2
未找到文件。
src/main/scala/xiangshan/backend/exu/Bru.scala
0 → 100644
浏览文件 @
4ae36549
package
xiangshan.backend.exu
import
chisel3._
import
chisel3.util._
import
xiangshan._
import
xiangshan.FuType._
import
xiangshan.utils._
import
xiangshan.backend.regfile.RfWritePort
import
xiangshan.backend.BRUOpType
// NOTE: BRUOpType is at backend/package.scala
class
Bru
extends
Exu
(
FuType
.
bru
.
litValue
(),
writeFpRf
=
true
)
{
override
def
toString
:
String
=
"Bru"
val
(
iovalid
,
src1
,
offset
,
func
,
pc
,
uop
)
=
(
io
.
in
.
valid
,
io
.
in
.
bits
.
src1
,
io
.
in
.
bits
.
uop
.
ctrl
.
imm
,
io
.
in
.
bits
.
uop
.
ctrl
.
fuOpType
,
SignExt
(
io
.
in
.
bits
.
uop
.
cf
.
pc
,
AddrBits
),
io
.
in
.
bits
.
uop
)
val
redirectHit
=
(
io
.
redirect
.
valid
&&
((
UIntToOH
(
io
.
redirect
.
bits
.
brTag
)
&
uop
.
brMask
).
orR
||
io
.
redirect
.
bits
.
isException
))
val
valid
=
iovalid
&&
!
redirectHit
val
isCSR
=
BRUOpType
.
isCSR
(
func
)
val
isFMV
=
BRUOpType
.
isFMV
(
func
)
val
isMOU
=
BRUOpType
.
isMOU
(
func
)
val
isJUMP
=
BRUOpType
.
isJUMP
(
func
)
// CSR
// FMV
// MOU
// JUMP
val
isRVC
=
uop
.
cf
.
isRVC
val
pcDelaySlot
=
Mux
(
isRVC
,
pc
+
2.
U
,
pc
+
4.
U
)
val
target
=
src1
+
offset
// NOTE: src1 is (pc/rf(rs1)), src2 is (offset)
io
.
out
.
bits
.
redirect
.
valid
:=
valid
&&
isJUMP
io
.
out
.
bits
.
redirect
.
bits
.
target
:=
target
io
.
out
.
bits
.
redirect
.
bits
.
brTag
:=
uop
.
brTag
io
.
out
.
bits
.
redirect
.
bits
.
isException
:=
false
.
B
io
.
out
.
bits
.
redirect
.
bits
.
roqIdx
:=
uop
.
roqIdx
io
.
out
.
bits
.
redirect
.
bits
.
freelistAllocPtr
:=
uop
.
freelistAllocPtr
// Output
val
resCSR
=
WireInit
(
0.
U
(
XLEN
.
W
))
// TODO: implement it
val
resFMV
=
WireInit
(
0.
U
(
XLEN
.
W
))
// TODO: implement it
val
resMOU
=
WireInit
(
0.
U
(
XLEN
.
W
))
// TODO: implement it
val
resJMP
=
pcDelaySlot
val
res
=
ParallelMux
(
VecInit
(
isCSR
,
isFMV
,
isMOU
,
isJUMP
)
zip
VecInit
(
resCSR
,
resFMV
,
resMOU
,
resJMP
)
)
io
.
in
.
ready
:=
io
.
out
.
ready
io
.
out
.
valid
:=
valid
// TODO: CSR/MOU/FMV may need change it
io
.
out
.
bits
.
uop
<>
io
.
in
.
bits
.
uop
io
.
out
.
bits
.
data
:=
res
io
.
dmem
<>
DontCare
io
.
out
.
bits
.
debug
.
isMMIO
:=
DontCare
// NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it
XSDebug
(
io
.
in
.
valid
,
"In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x, brMask:%x\n"
,
io
.
in
.
valid
,
io
.
in
.
ready
,
io
.
out
.
valid
,
io
.
out
.
ready
,
io
.
redirect
.
valid
,
io
.
redirect
.
bits
.
isException
,
redirectHit
,
io
.
redirect
.
bits
.
brTag
,
uop
.
brMask
)
XSDebug
(
io
.
in
.
valid
&&
isCSR
,
"src1:%x offset:%x func:%b type:CSR pc:%x\n"
,
src1
,
offset
,
func
,
pc
)
XSDebug
(
io
.
in
.
valid
&&
isFMV
,
"src1:%x offset:%x func:%b type:FMV pc:%x\n"
,
src1
,
offset
,
func
,
pc
)
XSDebug
(
io
.
in
.
valid
&&
isMOU
,
"src1:%x offset:%x func:%b type:MOU pc:%x\n"
,
src1
,
offset
,
func
,
pc
)
XSDebug
(
io
.
in
.
valid
&&
isJUMP
,
"src1:%x offset:%x func:%b type:JUMP pc:%x\n"
,
src1
,
offset
,
func
,
pc
)
XSDebug
(
io
.
in
.
valid
,
"Res:%x` CsrRes:%x FMV:%x Mou:%x Jmp:%x\n"
,
res
,
resCSR
,
resFMV
,
resMOU
,
resJMP
)
}
\ No newline at end of file
src/main/scala/xiangshan/backend/exu/Exu.scala
浏览文件 @
4ae36549
...
...
@@ -38,10 +38,6 @@ abstract class Exu
val
io
=
IO
(
new
ExuIO
)
}
class
Bru
extends
Exu
(
FuType
.
bru
.
litValue
(),
writeFpRf
=
true
)
with
NeedImpl
{
override
def
toString
:
String
=
"Bru"
}
class
Mul
extends
Exu
(
FuType
.
mul
.
litValue
())
with
NeedImpl
{
override
def
toString
:
String
=
"Mul"
}
...
...
src/main/scala/xiangshan/backend/package.scala
浏览文件 @
4ae36549
...
...
@@ -16,7 +16,7 @@ package object backend {
def
wrti
=
"b00_101"
.
U
def
seti
=
"b00_110"
.
U
def
clri
=
"b00_111"
.
U
// 1. move(x2f)
// FIXME: temp decode, should be fixed when use it
def
fmv_w_x
=
"b01_000"
.
U
...
...
@@ -27,7 +27,7 @@ package object backend {
def
fencei
=
"b01_001"
.
U
def
sfence_vma
=
"b01_010"
.
U
// 3. j
al
// 3. j
ump
def
jal
=
"b11_000"
.
U
def
jalr
=
"b11_010"
.
U
def
call
=
"b11_011"
.
U
...
...
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