difftest: fix difftest datapath

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -24,7 +24,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
 
   val exuData = Reg(Vec(RoqSize, UInt(XLEN.W)))//for debug
   val exuDebug = Reg(Vec(RoqSize, new DebugBundle))//for debug
-  val archRF = RegInit(VecInit(List.fill(32)(0.U(32.W))))//for debug
+  val archRF = RegInit(VecInit(List.fill(64)(0.U(32.W))))//for debug, fp regs included
 
   val ringBufferHeadExtended = RegInit(0.U(ExtendedRoqIdxWidth.W))
   val ringBufferTailExtended = RegInit(0.U(ExtendedRoqIdxWidth.W))

src/test/csrc/difftest.cpp

@@ -86,7 +86,7 @@ static const char *reg_name[DIFFTEST_NR_REG] = {
 int difftest_step(int commit, uint64_t *reg_scala, uint32_t this_inst,
   int skip, int isRVC, uint64_t intrNO, int priviledgeMode) {
 
-  assert(!skip && !isRVC && intrNO == 0)
+  assert(!skip && !isRVC && intrNO == 0);
   #define DEBUG_RETIRE_TRACE_SIZE 16
 
   uint64_t ref_r[DIFFTEST_NR_REG];
@@ -116,7 +116,7 @@ int difftest_step(int commit, uint64_t *reg_scala, uint32_t this_inst,
     ref_difftest_exec(1);//TODO
   }
 
-  assert(commit > 0 && commit <= 6)
+  assert(commit > 0 && commit <= 6);
   ref_difftest_exec(commit);
   ref_difftest_getregs(&ref_r);
 

src/test/scala/top/XSSim.scala

@@ -10,10 +10,10 @@ import xiangshan._
 
 class DiffTestIO extends Bundle {
   val r = Output(Vec(64, UInt(64.W)))
-  val commit = Output(Bool())
+  val commit = Output(UInt(32.W))
   val thisPC = Output(UInt(64.W))
   val thisINST = Output(UInt(32.W))
-  val isMMIO = Output(Bool())
+  val skip = Output(Bool())
   val isRVC = Output(Bool())
   val intrNO = Output(UInt(64.W))
   
@@ -53,7 +53,7 @@ class XSSimTop extends Module {
   BoringUtils.addSink(difftest.commit, "difftestCommit")
   BoringUtils.addSink(difftest.thisPC, "difftestThisPC")
   BoringUtils.addSink(difftest.thisINST, "difftestThisINST")
-  BoringUtils.addSink(difftest.isMMIO, "difftestIsMMIO")
+  BoringUtils.addSink(difftest.skip, "difftestSkip")
   BoringUtils.addSink(difftest.isRVC, "difftestIsRVC")
   BoringUtils.addSink(difftest.intrNO, "difftestIntrNO")
   BoringUtils.addSink(difftest.r, "difftestRegs")