Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OpenXiangShan
XiangShan
提交
3ea4a72d
X
XiangShan
项目概览
OpenXiangShan
/
XiangShan
12 个月 前同步成功
通知
1183
Star
3914
Fork
526
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
X
XiangShan
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
3ea4a72d
编写于
6月 28, 2020
作者:
Y
Yinan Xu
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
roq,exu: update log content
上级
81b87c92
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
8 addition
and
12 deletion
+8
-12
src/main/scala/xiangshan/backend/exu/Exu.scala
src/main/scala/xiangshan/backend/exu/Exu.scala
+2
-2
src/main/scala/xiangshan/backend/roq/Roq.scala
src/main/scala/xiangshan/backend/roq/Roq.scala
+6
-10
未找到文件。
src/main/scala/xiangshan/backend/exu/Exu.scala
浏览文件 @
3ea4a72d
...
...
@@ -130,7 +130,7 @@ class WriteBackArbMtoN(m: Int, n: Int) extends XSModule {
}
for
(
i
<-
0
until
n
)
{
XSInfo
(
io
.
out
(
i
).
valid
,
"out(%d) pc(0x%x) writebacks 0x%x to pdest(%d) ldest(%d)\n"
,
i
.
U
,
io
.
out
(
i
).
bits
.
data
,
io
.
out
(
i
).
bits
.
uop
.
cf
.
pc
,
io
.
out
(
i
).
bits
.
uop
.
pdest
,
io
.
out
(
i
).
bits
.
uop
.
ctrl
.
ldest
)
XSInfo
(
io
.
out
(
i
).
valid
,
"out(%d) pc(0x%x) writebacks 0x%x to pdest(%d) ldest(%d)\n"
,
i
.
U
,
io
.
out
(
i
).
bits
.
uop
.
cf
.
pc
,
io
.
out
(
i
).
bits
.
data
,
io
.
out
(
i
).
bits
.
uop
.
pdest
,
io
.
out
(
i
).
bits
.
uop
.
ctrl
.
ldest
)
}
}
src/main/scala/xiangshan/backend/roq/Roq.scala
浏览文件 @
3ea4a72d
...
...
@@ -76,7 +76,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
val
firedWriteback
=
VecInit
((
0
until
exuConfig
.
ExuCnt
).
map
(
io
.
exeWbResults
(
_
).
fire
())).
asUInt
XSInfo
(
PopCount
(
firedWriteback
)
>
0.
U
,
"writebacked %d insts\n"
,
PopCount
(
firedWriteback
))
for
(
i
<-
0
until
exuConfig
.
ExuCnt
){
XSInfo
(
io
.
exeWbResults
(
i
).
valid
,
"writebacked pc 0x%x wen %d data
%d
\n"
,
microOp
(
io
.
exeWbResults
(
i
).
bits
.
uop
.
roqIdx
).
cf
.
pc
,
XSInfo
(
io
.
exeWbResults
(
i
).
valid
,
"writebacked pc 0x%x wen %d data
0x%x
\n"
,
microOp
(
io
.
exeWbResults
(
i
).
bits
.
uop
.
roqIdx
).
cf
.
pc
,
microOp
(
io
.
exeWbResults
(
i
).
bits
.
uop
.
roqIdx
).
ctrl
.
rfWen
,
io
.
exeWbResults
(
i
).
bits
.
data
)
}
...
...
@@ -107,20 +107,16 @@ class Roq(implicit val p: XSConfig) extends XSModule {
io
.
scommit
:=
PopCount
(
validScommit
.
asUInt
)
XSInfo
(
retireCounter
>
0.
U
,
"retired %d insts\n"
,
retireCounter
)
XSInfo
(
""
)
XSInfo
(){
printf
(
"retired pcs are: "
)
for
(
i
<-
0
until
CommitWidth
){
when
(
io
.
commits
(
i
).
valid
){
printf
(
"%d: 0x%x "
,
ringBufferTail
+
i
.
U
,
microOp
(
ringBufferTail
+
i
.
U
).
cf
.
pc
)
}
}
printf
(
"\n"
)
for
(
i
<-
0
until
CommitWidth
)
{
XSInfo
(
io
.
commits
(
i
).
valid
,
"retired pc at commmit(%d) is: %d 0x%x\n"
,
i
.
U
,
ringBufferTail
+
i
.
U
,
microOp
(
ringBufferTail
+
i
.
U
).
cf
.
pc
)
}
val
walkFinished
=
(
0
until
CommitWidth
).
map
(
i
=>
(
ringBufferWalk
+
i
.
U
)
===
ringBufferWalkTarget
).
reduce
(
_
||
_
)
when
(
state
===
s_walk
){
when
(
state
===
s_walk
)
{
//exit walk state when all roq entry is commited
when
(
walkFinished
){
when
(
walkFinished
)
{
state
:=
s_idle
}
ringBufferWalkExtended
:=
ringBufferWalkExtended
+
CommitWidth
.
U
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录