Merge branch 'dev-frontend' into dev-ras

src/main/scala/xiangshan/frontend/BPU.scala

@@ -114,7 +114,7 @@ abstract class BPUStage extends XSModule {
 
   val predValid = RegInit(false.B)
 
-  io.in.ready := !predValid || io.out.fire() && io.pred.fire()
+  io.in.ready := !predValid || io.out.fire() && io.pred.fire() || io.flush
 
   def npc(pc: UInt, instCount: UInt) = pc + (instCount << 1.U)
 
@@ -194,10 +194,10 @@ class BPUStage1 extends BPUStage {
 
   // 'overrides' default logic
   // when flush, the prediction should also starts
-  when (io.flush || inFire) { predValid := true.B }
-  .elsewhen(outFire)        { predValid := false.B }
-  .otherwise                { predValid := predValid }
-  io.in.ready := !predValid || io.out.fire() && io.pred.fire() || io.flush
+  when (inFire)        { predValid := true.B }
+  .elsewhen (io.flush) { predValid := false.B }
+  .elsewhen (outFire)  { predValid := false.B }
+  .otherwise           { predValid := predValid }
   // io.out.valid := predValid
 
   // ubtb is accessed with inLatch pc in s1, 
@@ -225,7 +225,7 @@ class BPUStage2 extends BPUStage {
   // Use latched response from s1
   val btbResp = inLatch.resp.btb
   val bimResp = inLatch.resp.bim
-  takens    := VecInit((0 until PredictWidth).map(i => btbResp.hits(i) && (btbResp.types(i) === BTBtype.B && bimResp.ctrs(i)(1) || btbResp.types(i) === BTBtype.J)))
+  takens    := VecInit((0 until PredictWidth).map(i => btbResp.hits(i) && (btbResp.types(i) === BTBtype.B && bimResp.ctrs(i)(1) || btbResp.types(i) =/= BTBtype.B)))
   notTakens := VecInit((0 until PredictWidth).map(i => btbResp.hits(i) && btbResp.types(i) === BTBtype.B && !bimResp.ctrs(i)(1)))
   targetSrc := btbResp.targets
 
@@ -356,9 +356,10 @@ object BranchUpdateInfoWithHist {
 abstract class BaseBPU extends XSModule with BranchPredictorComponents{
   val io = IO(new Bundle() {
     // from backend
-    val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfoWithHist))
     val redirect = Flipped(ValidIO(new Redirect))
     val recover =  Flipped(ValidIO(new BranchUpdateInfo))
+    val inOrderBrInfo    = Flipped(ValidIO(new BranchUpdateInfoWithHist))
+    val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfoWithHist))
     // from ifu, frontend redirect
     val flush = Input(Vec(3, Bool()))
     // from if1
@@ -373,7 +374,8 @@ abstract class BaseBPU extends XSModule with BranchPredictorComponents{
 
   def npc(pc: UInt, instCount: UInt) = pc + (instCount << 1.U)
 
-  preds.map(_.io.update <> io.inOrderBrInfo)
+  preds.map(_.io.update <> io.outOfOrderBrInfo)
+  tage.io.update <> io.inOrderBrInfo
 
   val s1 = Module(new BPUStage1)
   val s2 = Module(new BPUStage2)

src/main/scala/xiangshan/frontend/Btb.scala

@@ -142,6 +142,7 @@ class BTB extends BasePredictor with BTBParams{
 
 
   def allocWay(valids: UInt, meta_tags: UInt, req_tag: UInt) = {
+    val randomAlloc = true
     if (BtbWays > 1) {
       val w = Wire(UInt(log2Up(BtbWays).W))
       val valid = WireInit(valids.andR)
@@ -151,7 +152,7 @@ class BTB extends BasePredictor with BTBParams{
       val chunks = (0 until nChunks).map( i => 
         tags(min((i+1)*l, tags.getWidth)-1, i*l)
       )
-      w := Mux(valid, chunks.reduce(_^_), PriorityEncoder(~valids))
+      w := Mux(valid, chunks.reduce(_^_), (if (randomAlloc) {LFSR64()(log2Up(BtbWays)-1,0)} else {PriorityEncoder(~valids)}))
       w
     } else {
       val w = WireInit(0.U)
@@ -207,7 +208,8 @@ class BTB extends BasePredictor with BTBParams{
   val metaWrite = BtbMetaEntry(btbAddr.getTag(u.pc), updateType, u.pd.isRVC)
   val dataWrite = BtbDataEntry(new_offset, new_extended)
 
-  val updateValid = io.update.valid && (u.isMisPred || !u.brInfo.btbHitJal)
+  val jalFirstEncountered = !u.isMisPred && !u.brInfo.btbHitJal && updateType === BTBtype.J
+  val updateValid = io.update.valid && (u.isMisPred || jalFirstEncountered)
   // Update btb
   for (w <- 0 until BtbWays) {
     for (b <- 0 until BtbBanks) {

src/main/scala/xiangshan/frontend/IFU.scala

@@ -312,7 +312,10 @@ class IFU extends XSModule with HasIFUConst
   bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid
   bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt)
   bpu.io.redirect <> io.redirect
-  bpu.io.recover  <> io.outOfOrderBrInfo
+  bpu.io.recover  <> io.inOrderBrInfo
+  bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid
+  bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist
+
   // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush)
   bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush)
   bpu.io.in.valid := if1_fire

src/main/scala/xiangshan/frontend/uBTB.scala

@@ -167,11 +167,14 @@ class MicroBTB extends BasePredictor
     val update_bank = getBank(update_br_pc)
     val update_base_bank = getBank(update_fetch_pc)
     val update_tag = getTag(update_br_pc)
-    val update_taget_offset =  u.target.asSInt - update_br_pc.asSInt
+    val update_target = Mux(u.pd.isBr, u.brTarget, u.target)
+    val update_taget_offset =  update_target.asSInt - update_br_pc.asSInt
     val update_is_BR_or_JAL = (u.pd.brType === BrType.branch) || (u.pd.brType === BrType.jal) 
-
-    val entry_write_valid = io.update.valid //&& update_is_BR_or_JAL
-    val meta_write_valid = io.update.valid //&& update_is_BR_or_JAL
+  
+  
+    val jalFirstEncountered = !u.isMisPred && !u.brInfo.btbHitJal && (u.pd.brType === BrType.jal)
+    val entry_write_valid = io.update.valid && (u.isMisPred || jalFirstEncountered)//io.update.valid //&& update_is_BR_or_JAL
+    val meta_write_valid = io.update.valid && (u.isMisPred || jalFirstEncountered)//io.update.valid //&& update_is_BR_or_JAL
     //write btb target when miss prediction
     when(entry_write_valid)
     {