Merge branch 'master' into debian-gogogo

block-inclusivecache-sifive @ 5adff60a

-Subproject commit 3d6bdf10d7b740588130e3056c8fd29f4175cadb
+Subproject commit 5adff60abb929cce2e261f1c43c29d8fa40334f9

src/main/scala/xiangshan/cache/atomicsMissQueue.scala

@@ -155,4 +155,12 @@ class AtomicsMissQueue extends DCacheModule
   val miss_finish = io.miss_finish
   XSDebug(miss_finish.fire(), "miss_finish client_id: %d entry_id: %d\n",
     miss_finish.bits.client_id, miss_finish.bits.entry_id)
+
+  when (io.lsu.req.fire()) {
+    XSDebug(s"AtomicsMissEntryTransaction req 0\n")
+  }
+
+  when (io.lsu.resp.fire()) {
+    XSDebug(s"AtomicsMissEntryTransaction resp 0\n")
+  }
 }

src/main/scala/xiangshan/cache/loadMissQueue.scala

@@ -153,6 +153,15 @@ class LoadMissEntry extends DCacheModule
       state := s_invalid
     }
   }
+
+  // debug output
+  when (io.lsu.req.fire()) {
+    XSDebug(s"LoadMissEntryTransaction req %d\n", io.id)
+  }
+
+  when (io.lsu.resp.fire()) {
+    XSDebug(s"LoadMissEntryTransaction resp %d\n", io.id)
+  }
 }
 
 

src/main/scala/xiangshan/cache/storeMissQueue.scala

@@ -139,6 +139,15 @@ class StoreMissEntry extends DCacheModule
       state := s_invalid
     }
   }
+
+  // debug output
+  when (io.lsu.req.fire()) {
+    XSDebug(s"StoreMissEntryTransaction req %d\n", io.id)
+  }
+
+  when (io.lsu.resp.fire()) {
+    XSDebug(s"StoreMissEntryTransaction resp %d\n", io.id)
+  }
 }