TLB: add assert to avoid other alu(1/2/3) exec sfence/fence.i

src/main/scala/xiangshan/backend/decode/Decoder.scala

@@ -143,7 +143,7 @@ class Decoder extends XSModule with HasInstrType {
   when(io.out.ctrl.isXSTrap){
     io.out.ctrl.lsrc1 := 10.U // a0
   }
-  io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap || io.out.ctrl.fuType===FuType.csr || io.out.ctrl.fuType===FuType.mou || (io.out.ctrl.fuType===FuType.alu && io.out.ctrl.fuOpType===ALUOpType.sfence)
+  io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap || io.out.ctrl.fuType===FuType.csr || io.out.ctrl.fuType===FuType.mou || (io.out.ctrl.fuType===FuType.alu && io.out.ctrl.fuOpType===ALUOpType.sfence/*noSpecExec make it sent to alu0,for roq is empty*/)
   //io.out.ctrl.isBlocked := (io.out.ctrl.fuType===FuType.alu && io.out.ctrl.fuOpType===ALUOpType.sfence) // TOOD: check it
 
 

src/main/scala/xiangshan/backend/exu/AluExeUnit.scala

@@ -71,7 +71,7 @@ class AluExeUnit(hasSfence: Boolean) extends Exu(Exu.aluExeUnitCfg) {
   io.out.bits.brUpdate.taken := isBranch && taken
   // io.out.bits.brUpdate.fetchIdx := uop.cf.brUpdate.fetchOffset >> 1.U  //TODO: consider RVC
 
-  if (hasSfence) {
+  if (hasSfence) { // Sfence && fence.i here. // TODO: add fence.i
     val waitSbuffer = ALUOpType.waitSbuffer(func)
     val sbEmpty = WireInit(true.B) // TODO: use tileLink and init is false.B
     val validNeg = RegInit(true.B)
@@ -89,6 +89,7 @@ class AluExeUnit(hasSfence: Boolean) extends Exu(Exu.aluExeUnitCfg) {
     io.out.bits.data := aluRes
     io.in.ready := Mux(waitSbuffer, sbEmpty && io.out.ready, io.out.ready)
   } else {
+    assert(!(ALUOpType.sfence===func && iovalid))
     io.in.ready := io.out.ready
     io.out.valid := valid
     io.out.bits.uop <> io.in.bits.uop