Difftest: add vec regs

difftest @ c56be38f

-Subproject commit 9fa45204da3bb274cd494448f7c84c9e2fca02d8
+Subproject commit c56be38ffc884bd752dac014fc7764bc77bc269c

ready-to-run @ b2bd1c24

-Subproject commit ff39f3680f69f9b38fa3cdf4c9fc1b2c6b3ec919
+Subproject commit b2bd1c24429d22443c2585c6414cfb157087251d

src/main/scala/xiangshan/Parameters.scala

@@ -50,7 +50,7 @@ case class XSCoreParameters
   AddrBits: Int = 64,
   VAddrBits: Int = 39,
   HasFPU: Boolean = true,
-  HasVPU: Boolean = false,
+  HasVPU: Boolean = true,
   HasCustomCSRCacheOp: Boolean = true,
   FetchWidth: Int = 8,
   AsidLength: Int = 16,

src/main/scala/xiangshan/XSCore.scala

@@ -382,6 +382,7 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
     exu.scheExtra.stIssuePtr <> memBlock.io.stIssuePtr
     exu.scheExtra.debug_fp_rat <> ctrlBlock.io.debug_fp_rat
     exu.scheExtra.debug_int_rat <> ctrlBlock.io.debug_int_rat
+    exu.scheExtra.debug_vec_rat <> ctrlBlock.io.debug_vec_rat
     exu.scheExtra.lqFull := memBlock.io.lqFull
     exu.scheExtra.sqFull := memBlock.io.sqFull
     exu.scheExtra.memWaitUpdateReq.staIssue.zip(memBlock.io.stIn).foreach{case (sink, src) => {

src/main/scala/xiangshan/backend/Scheduler.scala

@@ -19,7 +19,7 @@ package xiangshan.backend
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
-import difftest.{DifftestArchFpRegState, DifftestArchIntRegState}
+import difftest.{DifftestArchFpRegState, DifftestArchIntRegState, DifftestArchVecRegState}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import utils._
 import xiangshan._
@@ -295,6 +295,7 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
     // debug
     val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W)))
     val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W)))
+    val debug_vec_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W)))
     // perf
     val sqFull = Input(Bool())
     val lqFull = Input(Bool())
@@ -393,7 +394,7 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
     val wbPorts = if (isInt) io.writeback.take(intRfWritePorts) else io.writeback.drop(intRfWritePorts)
     val waddr = wbPorts.map(_.bits.uop.pdest)
     val wdata = wbPorts.map(_.bits.data)
-    val debugRead = if (isInt) io.extra.debug_int_rat else io.extra.debug_fp_rat
+    val debugRead = if (isInt) io.extra.debug_int_rat else io.extra.debug_fp_rat ++ io.extra.debug_vec_rat
     if (isInt) {
       val wen = wbPorts.map(wb =>wb.valid && wb.bits.uop.ctrl.rfWen)
       IntRegFile(IntPhyRegs, readIntRf, wen, waddr, wdata, debugReadAddr = Some(debugRead))
@@ -559,7 +560,13 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
     val difftest = Module(new DifftestArchFpRegState)
     difftest.io.clock := clock
     difftest.io.coreid := io.hartId
-    difftest.io.fpr := RegNext(RegNext(VecInit(fpRfReadData.takeRight(32))))
+    difftest.io.fpr := RegNext(RegNext(VecInit(fpRfReadData.map(_(XLEN-1, 0)).takeRight(64).take(32))))
+  }
+  if ((env.AlwaysBasicDiff || env.EnableDifftest) && fpRfConfig._1) {
+    val difftest = Module(new DifftestArchVecRegState)
+    difftest.io.clock := clock
+    difftest.io.coreid := io.hartId
+    difftest.io.vpr := RegNext(RegNext(VecInit(fpRfReadData.map((x : UInt) => (List(x(63, 0), x(127, 64)))).flatten.takeRight(64))))
   }
 
   XSPerfAccumulate("allocate_valid", PopCount(allocate.map(_.valid)))

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -69,9 +69,9 @@ class VpuCsrIO(implicit p: Parameters) extends XSBundle {
   val vstart = Input(UInt(XLEN.W))
   val vxsat = Input(UInt(1.W))
   val vxrm = Input(UInt(2.W))
-  val vcsr = Output(Valid(UInt(XLEN.W)))
+  val vcsr = Input(UInt(XLEN.W))
   val vl = Input(UInt(XLEN.W))
-  val vtype = Output(Valid(UInt(XLEN.W)))
+  val vtype = Input(UInt(XLEN.W))
   val vlenb = Input(UInt(XLEN.W))
   
   val vill = Input(UInt(1.W))
@@ -80,10 +80,10 @@ class VpuCsrIO(implicit p: Parameters) extends XSBundle {
   val vsew = Input(UInt(3.W))
   val vlmul = Input(UInt(3.W))
 
+  val set_vstart = Output(Valid(UInt(XLEN.W)))
   val set_vl = Output(Valid(UInt(XLEN.W)))
+  val set_vtype = Output(Valid(UInt(XLEN.W)))
 
-  val vstart_clr = Output(Bool())
-  val vstart_inc = Output(Bool())
   val dirty_vs = Output(Bool())
 }
 
@@ -624,7 +624,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   val vcsr = RegInit(0.U(XLEN.W))
   val vl = Reg(UInt(XLEN.W))
   val vtype = Reg(UInt(XLEN.W))
-  val vlenb = RegInit(32.U(XLEN.W))
+  val vlenb = RegInit(0.U(XLEN.W))
 
   // set mstatus->sd and mstatus->vs when true
   val csrw_dirty_vs_state = WireInit(false.B)
@@ -670,25 +670,14 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
     vcsrOld.asUInt
   }
 
-  def vtype_wfn(wdata: UInt): UInt = {
-    val vtypeOld = WireInit(vtype.asTypeOf(new VtypeStruct))
-    csrw_dirty_vs_state := true.B
-    vtypeOld.vill := wdata.asTypeOf(vtypeOld).vill
-    vtypeOld.vma := wdata.asTypeOf(vtypeOld).vma
-    vtypeOld.vta := wdata.asTypeOf(vtypeOld).vta
-    vtypeOld.vsew := wdata.asTypeOf(vtypeOld).vsew
-    vtypeOld.vlmul := wdata.asTypeOf(vtypeOld).vlmul
-    vtypeOld.asUInt
-  }
-
   val vcsrMapping = Map(
     MaskedRegMap(Vstart, vstart),
     MaskedRegMap(Vxrm, vcsr, wfn = vxrm_wfn, rfn = vxrm_rfn),
     MaskedRegMap(Vxsat, vcsr, wfn = vxsat_wfn, rfn = vxsat_rfn),
     MaskedRegMap(Vcsr, vcsr, wfn = vcsr_wfn),
     MaskedRegMap(Vl, vl),
-    MaskedRegMap(Vtype, vtype, wfn = vtype_wfn),
-    MaskedRegMap(Vlenb, vlenb)
+    MaskedRegMap(Vtype, vtype),
+    MaskedRegMap(Vlenb, vlenb),
   )
 
   // Hart Priviledge Mode
@@ -920,33 +909,28 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   }
   csrio.fpu.frm := fcsr.asTypeOf(new FcsrStruct).frm
 
-  when (RegNext(csrio.vpu.vcsr.valid)) {
-    vcsr := vcsr_wfn(RegNext(csrio.vpu.vcsr.bits))
+  when (RegNext(csrio.vpu.set_vstart.valid)) {
+    vstart := RegNext(csrio.vpu.set_vstart.bits)
   }
-  when (RegNext(csrio.vpu.vtype.valid)) {
-    vtype := vtype_wfn(RegNext(csrio.vpu.vtype.bits))
+  when (RegNext(csrio.vpu.set_vtype.valid)) {
+    vtype := RegNext(csrio.vpu.set_vtype.bits)
   }
   when (RegNext(csrio.vpu.set_vl.valid)) {
     vl := RegNext(csrio.vpu.set_vl.bits)
   }
   // set vs and sd in mstatus
-  when (csrw_dirty_vs_state || RegNext(csrio.vpu.dirty_vs)) {
-    val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
-    mstatusNew.vs := "b11".U
-    mstatusNew.sd := true.B
-    mstatus := mstatusNew.asUInt
-  }
-
-  when (RegNext(csrio.vpu.vstart_clr)) {
-    vstart := 0.U
-  }
-  .elsewhen (RegNext(csrio.vpu.vstart_inc)) {
-    vstart := vstart + 1.U
-  }
+  // when (csrw_dirty_vs_state || RegNext(csrio.vpu.dirty_vs)) {
+  //   val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
+  //   mstatusNew.vs := "b11".U
+  //   mstatusNew.sd := true.B
+  //   mstatus := mstatusNew.asUInt
+  // }
   
   csrio.vpu.vstart := vstart
   csrio.vpu.vxrm := vcsr.asTypeOf(new VcsrStruct).vxrm
   csrio.vpu.vxsat := vcsr.asTypeOf(new VcsrStruct).vxsat
+  csrio.vpu.vcsr := vcsr
+  csrio.vpu.vtype := vtype
   csrio.vpu.vl := vl
   csrio.vpu.vlenb := vlenb
   csrio.vpu.vill := vtype.asTypeOf(new VtypeStruct).vill
@@ -1360,6 +1344,19 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
     difftest.io.dscratch0 := dscratch
     difftest.io.dscratch1 := dscratch1
   }
+
+  if (env.AlwaysBasicDiff || env.EnableDifftest) {
+    val difftest = Module(new DifftestVectorState)
+    difftest.io.clock := clock
+    difftest.io.coreid := csrio.hartId
+    difftest.io.vstart := vstart
+    difftest.io.vxsat := vcsr.asTypeOf(new VcsrStruct).vxsat
+    difftest.io.vxrm := vcsr.asTypeOf(new VcsrStruct).vxrm
+    difftest.io.vcsr := vcsr
+    difftest.io.vl := vl
+    difftest.io.vtype := vtype
+    difftest.io.vlenb := vlenb
+  }
 }
 
 class PFEvent(implicit p: Parameters) extends XSModule with HasCSRConst  {

src/main/scala/xiangshan/backend/regfile/Regfile.scala

@@ -44,7 +44,7 @@ class Regfile
   val io = IO(new Bundle() {
     val readPorts = Vec(numReadPorts, new RfReadPort(len, width))
     val writePorts = Vec(numWritePorts, new RfWritePort(len, width))
-    val debug_rports = Vec(32, new RfReadPort(len, width))
+    val debug_rports = Vec(64, new RfReadPort(len, width))
   })
 
   println("Regfile: size:" + NRPhyRegs + " read: " + numReadPorts + " write: " + numWritePorts)