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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
346c99d3
编写于
12月 17, 2020
作者:
Y
Yinan Xu
浏览文件
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电子邮件补丁
差异文件
loadQueue: use vec for enqPtr
上级
61ec8c34
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
14 addition
and
12 deletion
+14
-12
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
+12
-10
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
+2
-2
未找到文件。
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
浏览文件 @
346c99d3
...
...
@@ -58,11 +58,11 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
val
listening
=
Reg
(
Vec
(
LoadQueueSize
,
Bool
()))
// waiting for refill result
val
pending
=
Reg
(
Vec
(
LoadQueueSize
,
Bool
()))
// mmio pending: inst is an mmio inst, it will not be executed until it reachs the end of roq
val
enqPtrExt
=
RegInit
(
0.
U
.
asTypeOf
(
new
LqPtr
))
val
enqPtrExt
=
RegInit
(
VecInit
((
0
until
RenameWidth
).
map
(
_
.
U
.
asTypeOf
(
new
LqPtr
))
))
val
deqPtrExt
=
RegInit
(
0.
U
.
asTypeOf
(
new
LqPtr
))
val
enqPtr
=
enqPtrExt
.
value
val
enqPtr
=
enqPtrExt
(
0
)
.
value
val
deqPtr
=
deqPtrExt
.
value
val
sameFlag
=
enqPtrExt
.
flag
===
deqPtrExt
.
flag
val
sameFlag
=
enqPtrExt
(
0
)
.
flag
===
deqPtrExt
.
flag
val
isEmpty
=
enqPtr
===
deqPtr
&&
sameFlag
val
isFull
=
enqPtr
===
deqPtr
&&
!
sameFlag
val
allowIn
=
!
isFull
...
...
@@ -76,13 +76,13 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
val
enqDeqMask
=
Mux
(
sameFlag
,
enqDeqMask1
,
~
enqDeqMask1
)
// Enqueue at dispatch
val
validEntries
=
distanceBetween
(
enqPtrExt
,
deqPtrExt
)
val
validEntries
=
distanceBetween
(
enqPtrExt
(
0
)
,
deqPtrExt
)
val
firedDispatch
=
io
.
enq
.
req
.
map
(
_
.
valid
)
io
.
enq
.
canAccept
:=
validEntries
<=
(
LoadQueueSize
-
RenameWidth
).
U
XSDebug
(
p
"(ready, valid): ${io.enq.canAccept}, ${Binary(Cat(firedDispatch))}\n"
)
for
(
i
<-
0
until
RenameWidth
)
{
val
offset
=
if
(
i
==
0
)
0.
U
else
PopCount
((
0
until
i
).
map
(
firedDispatch
(
_
)))
val
lqIdx
=
enqPtrExt
+
offset
val
lqIdx
=
enqPtrExt
(
offset
)
val
index
=
lqIdx
.
value
when
(
io
.
enq
.
req
(
i
).
valid
)
{
uop
(
index
)
:=
io
.
enq
.
req
(
i
).
bits
...
...
@@ -100,8 +100,9 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
}
when
(
Cat
(
firedDispatch
).
orR
)
{
enqPtrExt
:=
enqPtrExt
+
PopCount
(
firedDispatch
)
XSInfo
(
"dispatched %d insts to lq\n"
,
PopCount
(
firedDispatch
))
val
enqNumber
=
PopCount
(
firedDispatch
)
enqPtrExt
:=
VecInit
(
enqPtrExt
.
map
(
_
+
enqNumber
))
XSInfo
(
"dispatched %d insts to lq\n"
,
enqNumber
)
}
// writeback load
...
...
@@ -365,7 +366,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
val
startIndex
=
io
.
storeIn
(
i
).
bits
.
uop
.
lqIdx
.
value
val
lqIdxMask
=
UIntToMask
(
startIndex
,
LoadQueueSize
)
val
xorMask
=
lqIdxMask
^
enqMask
val
sameFlag
=
io
.
storeIn
(
i
).
bits
.
uop
.
lqIdx
.
flag
===
enqPtrExt
.
flag
val
sameFlag
=
io
.
storeIn
(
i
).
bits
.
uop
.
lqIdx
.
flag
===
enqPtrExt
(
0
)
.
flag
val
toEnqPtrMask
=
Mux
(
sameFlag
,
xorMask
,
~
xorMask
)
// check if load already in lq needs to be rolledback
...
...
@@ -539,7 +540,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
enqPtrExt
:=
enqPtrExt
}
when
(
lastCycleRedirect
.
valid
)
{
enqPtrExt
:=
enqPtrExt
-
PopCount
(
needCancelReg
)
val
cancelCount
=
PopCount
(
needCancelReg
)
enqPtrExt
:=
VecInit
(
enqPtrExt
.
map
(
_
-
cancelCount
))
}
// assert(!io.rollback.valid)
...
...
@@ -548,7 +550,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
}
// debug info
XSDebug
(
"enqPtrExt %d:%d deqPtrExt %d:%d\n"
,
enqPtrExt
.
flag
,
enqPtr
,
deqPtrExt
.
flag
,
deqPtr
)
XSDebug
(
"enqPtrExt %d:%d deqPtrExt %d:%d\n"
,
enqPtrExt
(
0
)
.
flag
,
enqPtr
,
deqPtrExt
.
flag
,
deqPtr
)
def
PrintFlag
(
flag
:
Bool
,
name
:
String
)
:
Unit
=
{
when
(
flag
)
{
...
...
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
浏览文件 @
346c99d3
...
...
@@ -52,8 +52,8 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
val
pending
=
Reg
(
Vec
(
StoreQueueSize
,
Bool
()))
// mmio pending: inst is an mmio inst, it will not be executed until it reachs the end of roq
require
(
StoreQueueSize
>
RenameWidth
)
val
enqPtrExt
=
RegInit
(
VecInit
((
0
until
RenameWidth
).
map
(
i
=>
i
.
U
.
asTypeOf
(
new
SqPtr
))))
val
deqPtrExt
=
RegInit
(
VecInit
((
0
until
StorePipelineWidth
).
map
(
i
=>
i
.
U
.
asTypeOf
(
new
SqPtr
))))
val
enqPtrExt
=
RegInit
(
VecInit
((
0
until
RenameWidth
).
map
(
_
.
U
.
asTypeOf
(
new
SqPtr
))))
val
deqPtrExt
=
RegInit
(
VecInit
((
0
until
StorePipelineWidth
).
map
(
_
.
U
.
asTypeOf
(
new
SqPtr
))))
val
enqPtr
=
enqPtrExt
(
0
).
value
val
deqPtr
=
deqPtrExt
(
0
).
value
val
sameFlag
=
enqPtrExt
(
0
).
flag
===
deqPtrExt
(
0
).
flag
...
...
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