RVA: add RVA decode

src/main/scala/xiangshan/backend/decode/Decoder.scala

@@ -143,5 +143,5 @@ class Decoder extends XSModule with HasInstrType {
   when(io.out.ctrl.isXSTrap){
     io.out.ctrl.lsrc1 := 10.U // a0
   }
-  io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap || io.out.ctrl.fuType===FuType.csr
+  io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap || io.out.ctrl.fuType===FuType.csr || io.out.ctrl.fuType===FuType.mou
 }

src/main/scala/xiangshan/backend/decode/isa/RVA.scala

@@ -3,6 +3,7 @@ package xiangshan.backend.decode.isa
 import chisel3._
 import chisel3.util._
 import xiangshan.FuType
+import xiangshan.mem.LSUOpType
 import xiangshan.backend.decode.HasInstrType
 
 
@@ -25,6 +26,21 @@ object RVAInstr extends HasInstrType {
   def AMOMAXU = BitPat("b11100_??_?????_?????_01?_?????_0101111")
   // funct3 === 010 or 011
 
-  // fixme: add rva inst
-  val table = Array()
+  val table = Array(
+    // LR          -> List(InstrI, FuType.mou, LSUOpType.lr),
+    // SC          -> List(InstrS, FuType.mou, LSUOpType.sc),
+    LR_D        -> List(InstrI, FuType.mou, LSUOpType.lr),
+    LR_W        -> List(InstrI, FuType.mou, LSUOpType.lr),
+    SC_D        -> List(InstrSA, FuType.mou, LSUOpType.sc),
+    SC_W        -> List(InstrSA, FuType.mou, LSUOpType.sc),
+    AMOSWAP     -> List(InstrR, FuType.mou, LSUOpType.amoswap),
+    AMOADD      -> List(InstrR, FuType.mou, LSUOpType.amoadd),
+    AMOXOR      -> List(InstrR, FuType.mou, LSUOpType.amoxor),
+    AMOAND      -> List(InstrR, FuType.mou, LSUOpType.amoand),
+    AMOOR       -> List(InstrR, FuType.mou, LSUOpType.amoor),
+    AMOMIN      -> List(InstrR, FuType.mou, LSUOpType.amomin),
+    AMOMAX      -> List(InstrR, FuType.mou, LSUOpType.amomax),
+    AMOMINU     -> List(InstrR, FuType.mou, LSUOpType.amominu),
+    AMOMAXU     -> List(InstrR, FuType.mou, LSUOpType.amomaxu)
+  )
 }

src/main/scala/xiangshan/package.scala

@@ -41,13 +41,14 @@ package object xiangshan {
 
     def ldu          = "b1100".U
     def stu          = "b1101".U
+    def mou          = "b1110".U // for amo, lr, sc, fence
 
     def apply() = UInt(log2Up(num).W)
 
     def isIntExu(fuType: UInt) =  !fuType(3)
     def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U
     def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U
-    def isLoadExu(fuType: UInt) = fuType === ldu
+    def isLoadExu(fuType: UInt) = fuType === ldu || fuType===mou
     def isStoreExu(fuType: UInt) = fuType === stu
 
     val functionNameMap = Map(