MissQueue, WBU: sync with prober on writebacked block.

src/main/scala/xiangshan/cache/dcacheWrapper.scala

@@ -410,6 +410,9 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   prober.io.wb_resp    := wb.io.resp
   wb.io.mem_grant      := bus.d.fire() && bus.d.bits.source === cfg.nMissEntries.U
 
+  missQueue.io.probe_wb_req.valid := prober.io.wb_req.fire()
+  missQueue.io.probe_wb_req.bits  := prober.io.wb_req.bits
+
   TLArbiter.lowestFromSeq(edge, bus.c, Seq(prober.io.rep, wb.io.release))
 
   // synchronization stuff
@@ -469,7 +472,10 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
     val miss_idx_matches = VecInit(missQueue.io.block_probe_idxes map (entry => entry.valid && entry.bits === get_idx(addr)))
     val miss_idx_match = miss_idx_matches.reduce(_||_)
 
-    store_addr_match || atomics_addr_match || lrsc_addr_match || miss_idx_match
+    // the missed req
+    val miss_req_idx_match = missReq.fire() && get_idx(missReq.bits.addr) === get_idx(addr)
+
+    store_addr_match || atomics_addr_match || lrsc_addr_match || miss_idx_match || miss_req_idx_match
   }
 
   def block_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T], block_signal: Bool) = {

src/main/scala/xiangshan/cache/missQueue.scala

@@ -57,6 +57,9 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
 
     val wb_req      = DecoupledIO(new WritebackReq(edge.bundle.sourceBits))
     val wb_resp     = Input(Bool())
+
+    // watch prober's write back requests
+    val probe_wb_req = Flipped(ValidIO(new WritebackReq(edge.bundle.sourceBits)))
   })
 
   // MSHR:
@@ -356,6 +359,32 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
     }
   }
 
+  // during refill, probe may step in, it may release our blocks
+  // if it releases the block we are trying to acquire, we don't care, since we will get it back eventually
+  // but we need to know whether it releases the block we are trying to evict
+  val prober_writeback_our_block = (state === s_refill_req || state === s_refill_resp) &&
+    io.probe_wb_req.valid && !io.probe_wb_req.bits.voluntary &&
+    io.probe_wb_req.bits.tag === req_old_meta.tag &&
+    io.probe_wb_req.bits.idx === req_idx &&
+    io.probe_wb_req.bits.way_en === req_way_en &&
+    needs_writeback
+
+  def onShrink(param: UInt): ClientMetadata = {
+    import freechips.rocketchip.tilelink.ClientStates._
+    import freechips.rocketchip.tilelink.TLPermissions._
+    val state = MuxLookup(param, Nothing, Seq(
+      TtoB   -> Branch,
+      TtoN   -> Nothing,
+      BtoN   -> Nothing))
+    ClientMetadata(state)
+  }
+
+  when (prober_writeback_our_block) {
+    req_old_meta.coh := onShrink(io.probe_wb_req.bits.param)
+  }
+
+  // --------------------------------------------
+  // data write
   when (state === s_data_write_req) {
     io.refill.valid        := true.B
     io.refill.bits.addr    := req_block_addr
@@ -445,6 +474,8 @@ class MissQueue(edge: TLEdgeOut) extends DCacheModule with HasTLDump
     val wb_req      = Decoupled(new WritebackReq(edge.bundle.sourceBits))
     val wb_resp     = Input(Bool())
 
+    val probe_wb_req = Flipped(ValidIO(new WritebackReq(edge.bundle.sourceBits)))
+
     val inflight_req_idxes       = Output(Vec(cfg.nMissEntries, Valid(UInt())))
     val inflight_req_block_addrs = Output(Vec(cfg.nMissEntries, Valid(UInt())))
 
@@ -495,6 +526,7 @@ class MissQueue(edge: TLEdgeOut) extends DCacheModule with HasTLDump
 
     wb_req_arb.io.in(i)     <>  entry.io.wb_req
     entry.io.wb_resp        :=  io.wb_resp
+    entry.io.probe_wb_req   <>  io.probe_wb_req
 
     entry.io.mem_grant.valid := false.B
     entry.io.mem_grant.bits  := DontCare

src/main/scala/xiangshan/cache/wbu.scala

@@ -56,10 +56,17 @@ class WritebackUnit(edge: TLEdgeOut) extends DCacheModule {
   when (state === s_invalid) {
     io.req.ready := true.B
     when (io.req.fire()) {
-      state := s_data_read_req
-      data_req_cnt := 0.U
-      req := io.req.bits
-      acked := false.B
+      // for report types: TtoT, BtoB, NtoN, we do nothing
+      import freechips.rocketchip.tilelink.TLPermissions._
+      def do_nothing(x: UInt) = x > BtoN
+      when (do_nothing(io.req.bits.param)) {
+        state := s_resp
+      } .otherwise {
+        state := s_data_read_req
+        data_req_cnt := 0.U
+        req := io.req.bits
+        acked := false.B
+      }
     }
   }