LoadUnit: removed unnecessary wiring.

2d31690c · Allen · 3550f2de · 2d31690c
隐藏空白更改
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src/main/scala/xiangshan/mem/LoadUnit.scala src/main/scala/xiangshan/mem/LoadUnit.scala +0 -3

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--- a/src/main/scala/xiangshan/mem/LoadUnit.scala
+++ b/src/main/scala/xiangshan/mem/LoadUnit.scala
@@ -273,9 +273,6 @@ class LoadUnit extends XSModule {
  // pipeline control
  l5_in.ready := io.ldout.ready

-  io.lsroq.ldout.ready := false.B // TODO
-  // TODO: writeback missed loads
-
  val cdbArb = Module(new Arbiter(new ExuOutput, 2))
  io.ldout <> cdbArb.io.out
  hitLoadOut <> cdbArb.io.in(0)