Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OpenXiangShan
XiangShan
提交
2ab2279c
X
XiangShan
项目概览
OpenXiangShan
/
XiangShan
9 个月 前同步成功
通知
1183
Star
3914
Fork
526
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
X
XiangShan
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
2ab2279c
编写于
12月 23, 2020
作者:
Y
Yinan Xu
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
dpq: use reg to keep track of the number of valid entries
上级
dc98c21c
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
28 addition
and
4 deletion
+28
-4
src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
...main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
+28
-4
未找到文件。
src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
浏览文件 @
2ab2279c
...
...
@@ -20,7 +20,6 @@ class DispatchQueueIO(enqnum: Int, deqnum: Int) extends XSBundle {
// dispatch queue: accepts at most enqnum uops from dispatch1 and dispatches deqnum uops at every clock cycle
class
DispatchQueue
(
size
:
Int
,
enqnum
:
Int
,
deqnum
:
Int
)
extends
XSModule
with
HasCircularQueuePtrHelper
{
val
io
=
IO
(
new
DispatchQueueIO
(
enqnum
,
deqnum
))
val
indexWidth
=
log2Ceil
(
size
)
val
s_invalid
::
s_valid
::
Nil
=
Enum
(
2
)
...
...
@@ -34,10 +33,12 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int) extends XSModule with H
// tail: first invalid entry (free entry)
val
tailPtr
=
RegInit
(
VecInit
((
0
until
enqnum
).
map
(
_
.
U
.
asTypeOf
(
new
CircularQueuePtr
(
size
)))))
val
tailPtrMask
=
UIntToMask
(
tailPtr
(
0
).
value
,
size
)
// valid entries counter
val
validCounter
=
RegInit
(
0.
U
(
log2Ceil
(
size
).
W
))
val
allowEnqueue
=
RegInit
(
true
.
B
)
val
validEntries
=
distanceBetween
(
tailPtr
(
0
),
headPtr
(
0
))
val
isTrueEmpty
=
~
Cat
((
0
until
size
).
map
(
i
=>
stateEntries
(
i
)
===
s_valid
)).
orR
val
canEnqueue
=
validEntries
<=
(
size
-
enqnum
).
U
val
canEnqueue
=
allowEnqueue
val
canActualEnqueue
=
canEnqueue
&&
!
io
.
redirect
.
valid
/**
...
...
@@ -93,7 +94,8 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int) extends XSModule with H
*/
// dequeue
val
numDeqTry
=
Mux
(
validEntries
>
deqnum
.
U
,
deqnum
.
U
,
validEntries
)
val
currentValidCounter
=
distanceBetween
(
tailPtr
(
0
),
headPtr
(
0
))
val
numDeqTry
=
Mux
(
currentValidCounter
>
deqnum
.
U
,
deqnum
.
U
,
currentValidCounter
)
val
numDeqFire
=
PriorityEncoder
(
io
.
deq
.
zipWithIndex
.
map
{
case
(
deq
,
i
)
=>
// For dequeue, the first entry should never be s_invalid
// Otherwise, there should be a redirect and tail walks back
...
...
@@ -146,6 +148,28 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int) extends XSModule with H
)
}
// update valid counter and allowEnqueue reg
validCounter
:=
Mux
(
exceptionValid
,
0.
U
,
Mux
(
io
.
redirect
.
valid
,
validCounter
,
Mux
(
lastLastCycleMisprediction
,
currentValidCounter
,
validCounter
+
numEnq
-
numDeq
)
)
)
allowEnqueue
:=
Mux
(
io
.
redirect
.
valid
,
false
.
B
,
Mux
(
lastLastCycleMisprediction
,
currentValidCounter
<=
(
size
-
enqnum
).
U
,
// To optimize timing, we don't use numDeq here.
// It affects cases when validCount + numEnq - numDeq <= (size - enqnum).U.
// For example, there're 10 empty entries with 6 enqueue and 2 dequeue.
// However, since dispatch queue size > (numEnq + numDeq),
// even if we allow enqueue, they cannot be dispatched immediately.
validCounter
+
numEnq
<=
(
size
-
enqnum
).
U
)
)
/**
* Part 3: set output and input
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录