Merge pull request #253 from RISCVERS/fix-icache-s3_ready

fix icache s3_ready bug

chisel3 @ 87916d55

-Subproject commit e6192ea75ce0d840b4b51a376921c2feecaa3b46
+Subproject commit 87916d55490ff04691bc59454086c82ed09646b2

chiseltest @ 6a2e1776

-Subproject commit 22d2846004b03d545b657922f1a03c1497e3d847
+Subproject commit 6a2e1776c91635deb7e1982b2333611ae620e777

firrtl @ cd845bdb

-Subproject commit c7bbb75b8b293d639848abaa9f68121f80947f42
+Subproject commit cd845bdbfea0c09e9edbf61e651ede5197d8a084

rocket-chip @ 147bdcc4

-Subproject commit 923ec05edecbbf509f614573b728ce8d029698aa
+Subproject commit 147bdcc4a26c74e5d7a47e3d667d456699d6d11f

src/main/scala/xiangshan/cache/icache.scala

@@ -407,7 +407,7 @@ class ICache extends ICacheModule
   val refillDataVec = icacheMissQueue.io.resp.bits.data.asTypeOf(Vec(blockWords,UInt(wordBits.W)))
   val refillDataOut = cutHelper(refillDataVec, s3_req_pc(5,1),s3_req_mask )
 
-  s3_ready := ((io.resp.fire() || !s3_valid) && !blocking) || (blocking && icacheMissQueue.io.resp.valid)
+  s3_ready := ((io.resp.fire() || !s3_valid) && !blocking) || (blocking && icacheMissQueue.io.resp.fire())
 
   //TODO: coherence
   XSDebug("[Stage 3] valid:%d   pc: 0x%x  mask: %b ipf:%d\n",s3_valid,s3_req_pc,s3_req_mask,s3_tlb_resp.excp.pf.instr)

treadle @ 0368d83b

-Subproject commit 7b786e80233701adb16d2e8c39069669ec614b3a
+Subproject commit 0368d83ba472e8fb90057ace0389ff65d96b667a