frontend: add logs

src/main/scala/xiangshan/XSCore.scala

@@ -29,7 +29,7 @@ trait HasXSParameter {
   val PredictWidth = FetchWidth * 2
   val EnableBPU = true
   val EnableBPD = false // enable backing predictor(like Tage) in BPUStage3
-  val EnableRAS = false
+  val EnableRAS = true
   val HistoryLength = 64
   val BtbSize = 256
   // val BtbWays = 4

src/main/scala/xiangshan/frontend/BPU.scala

@@ -168,9 +168,9 @@ class BPUStage1 extends XSModule {
 
   // update ghr
   updateGhr := io.s1OutPred.bits.redirect || 
-               RegNext(io.in.pc.fire) && ~io.s1OutPred.bits.redirect && (btbNotTakens.asUInt & maskLatch).reduce(_||_) ||
+               RegNext(io.in.pc.fire) && ~io.s1OutPred.bits.redirect && (btbNotTakens.asUInt & maskLatch).orR || // TODO: use parallel or
                io.flush
-  val brJumpIdx = Mux(!(btbHit && btbTaken), 0.U, UIntToOH(btbTakenIdx))
+  val brJumpIdx = Mux(!btbTaken, 0.U, UIntToOH(btbTakenIdx))
   val indirectIdx = Mux(!jbtacHit, 0.U, UIntToOH(jbtacHitIdx))
   // if backend redirects, restore history from backend;
   // if stage3 redirects, restore history from stage3;
@@ -204,7 +204,7 @@ class BPUStage1 extends XSModule {
     // io.s1OutPred.bits.instrValid := Mux(!io.s1OutPred.bits.redirect || io.s1OutPred.bits.lateJump, maskLatch,
     //                                 Mux(!btbIsRVCs(OHToUInt(takenIdx)), LowerMask(takenIdx << 1.U, PredictWidth),
     //                                 LowerMask(takenIdx, PredictWidth))).asTypeOf(Vec(PredictWidth, Bool()))
-    io.s1OutPred.bits.redirect := (maskLatch & Fill(PredictWidth, ~io.s1OutPred.bits.redirect || io.s1OutPred.bits.lateJump) |
+    io.s1OutPred.bits.instrValid := (maskLatch & Fill(PredictWidth, ~io.s1OutPred.bits.redirect || io.s1OutPred.bits.lateJump) |
       PriorityMux(brJumpIdx | indirectIdx, (0 until PredictWidth).map(getInstrValid(_)))).asTypeOf(Vec(PredictWidth, Bool()))
     io.s1OutPred.bits.target := Mux(takenIdx === 0.U, pcLatch + (PopCount(maskLatch) << 1.U), Mux(takenIdx === brJumpIdx, btbTakenTarget, jbtacTarget))
     io.s1OutPred.bits.lateJump := btb.io.out.isRVILateJump || jbtac.io.out.isRVILateJump
@@ -370,7 +370,8 @@ class BPUStage3 extends XSModule {
   }
 
   // TODO: what if if4 and if2 late jump to the same target?
-  val lateJump = io.s3Taken && PriorityMux(Reverse(predecode.mask),((PredictWidth - 1) to 0).map(_.U)) === jmpIdx && !predecode.isRVC(jmpIdx)
+  // val lateJump = io.s3Taken && PriorityMux(Reverse(predecode.mask), ((PredictWidth - 1) to 0).map(_.U)) === jmpIdx && !predecode.isRVC(jmpIdx)
+  val lateJump = io.s3Taken && PriorityMux(Reverse(predecode.mask), (0 until PredictWidth).map {i => (PredictWidth - 1 - i).U}) === jmpIdx && !predecode.isRVC(jmpIdx)
   io.out.bits.lateJump := lateJump
 
   io.out.bits.predCtr := inLatch.btbPred.bits.predCtr
@@ -412,6 +413,7 @@ class BPUStage3 extends XSModule {
   // for (i <- 0 until FetchWidth) {
   //   io.out.bits.instrValid(i) := ((io.s3Taken && i.U <= jmpIdx) || ~io.s3Taken) && io.predecode.bits.mask(i)
   // }
+  io.out.bits.instrValid := predecode.mask.asTypeOf(Vec(PredictWidth, Bool()))
   for (i <- PredictWidth - 1 to 0) {
     io.out.bits.instrValid(i) := (io.s3Taken && i.U <= jmpIdx || !io.s3Taken) && predecode.mask(i)
     if (i != (PredictWidth - 1)) {

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -66,15 +66,17 @@ class Ibuffer extends XSModule {
         ibuf(enq_idx).hist := io.in.bits.hist(i>>1)
         // ibuf(enq_idx).btbVictimWay := io.in.bits.btbVictimWay
         ibuf(enq_idx).btbPredCtr := io.in.bits.predCtr(i>>1)
-        ibuf(enq_idx).btbHit := io.in.bits.btbHit
+        ibuf(enq_idx).btbHit := io.in.bits.btbHit(i>>1)
         ibuf(enq_idx).tageMeta := io.in.bits.tageMeta(i>>1)
         ibuf(enq_idx).rasSp := io.in.bits.rasSp
         ibuf(enq_idx).rasTopCtr := io.in.bits.rasTopCtr
         ibuf_valid(enq_idx) := true.B
+        XSDebug("Enq: i:%d idx:%d mask:%b instr:%x pc:%x fetchOffset=%d\n",
+          i.U, enq_idx, io.in.bits.mask(i), Mux(i.U(0), io.in.bits.instrs(i>>1)(31,16), io.in.bits.instrs(i>>1)(15,0)), io.in.bits.pc + ((enq_idx - tail_ptr)<<1).asUInt, ((enq_idx - tail_ptr) << 1).asUInt)
       }
 
-      XSDebug(!(i.U)(0), "Enq: i:%d Idx:%d mask:%b instr:%x pc:%x pnpc:%x\n",
-        (i/2).U, enq_idx, io.in.bits.mask(i), io.in.bits.instrs(i/2), io.in.bits.pc + (2*i).U, io.in.bits.pnpc(i/2))
+      // XSDebug(!(i.U)(0), "Enq: i:%d Idx:%d mask:%b instr:%x pc:%x pnpc:%x\n",
+      //   (i/2).U, enq_idx, io.in.bits.mask(i), io.in.bits.instrs(i/2), io.in.bits.pc + ((enq_idx - tail_ptr)<<1).asUInt, io.in.bits.pnpc(i/2))
       enq_idx = enq_idx + io.in.bits.mask(i)
     }
 
@@ -149,6 +151,7 @@ class Ibuffer extends XSModule {
         io.out(i).bits.rasTopCtr := ibuf(head_ptr + (i<<1).U).rasTopCtr
         io.out(i).bits.isRVC := false.B
       }
+      XSDebug(deqValid, p"Deq: i:${i.U} valid:${ibuf_valid(deq_idx)} idx=${Decimal(deq_idx)} ${Decimal(deq_idx + 1.U)} instr:${Hexadecimal(io.out(i).bits.instr)} PC=${Hexadecimal(io.out(i).bits.pc)} v=${io.out(i).valid}  r=${io.out(i).ready}\n")
 
       // When can't deque, deq_idx+0
       // when RVC deque, deq_idx+1
@@ -159,8 +162,6 @@ class Ibuffer extends XSModule {
         (ibuf(deq_idx).inst(1,0) =/= "b11".U) -> 1.U,
         ibuf_valid(deq_idx + 1.U) -> 2.U
       ))
-
-      XSDebug(deqValid, p"Deq: i:${i.U} valid:${ibuf_valid(head_ptr + deq_idx)} idx=${Decimal(head_ptr + deq_idx)} instr:${Hexadecimal(io.out(i).bits.instr)} PC=${Hexadecimal(io.out(i).bits.pc)}  ${Decimal(head_ptr + deq_idx + 1.U)} v=${io.out(i).valid}  r=${io.out(i).ready}\n")
     }
     head_ptr := deq_idx
 
@@ -207,6 +208,6 @@ class Ibuffer extends XSModule {
   // for(i <- 0 until DecodeWidth) {
   //   XSDebug(deqValid, p"${Binary(io.out(i).bits.instr)}  PC=${Hexadecimal(io.out(i).bits.pc)}  v=${io.out(i).valid}  r=${io.out(i).ready}\n")
   // }
-  XSDebug(enqValid, p"last_head_ptr=$head_ptr  last_tail_ptr=$tail_ptr\n")
+  XSDebug(p"head_ptr=$head_ptr  tail_ptr=$tail_ptr\n")
 //  XSInfo(full, "Queue is full\n")
 }

src/main/scala/xiangshan/frontend/btb.scala

@@ -236,6 +236,8 @@ class BTB extends XSModule {
     XSDebug(fireLatch, "read_resp[b=%d][r=%d]: valid=%d, tag=0x%x, target=0x%x, type=%d, ctr=%d\n",
     i.U, realRowLatch(i), metaRead(i).valid, metaRead(i).tag, dataRead(i).target, dataRead(i).btbType, dataRead(i).pred)
   }
+  XSDebug("out: taken=%d takenIdx=%d tgt=%x notTakens=%b hits=%b isRVILateJump=%d\n",
+    io.out.taken, io.out.takenIdx, io.out.target, io.out.notTakens.asUInt, io.out.hits.asUInt, io.out.isRVILateJump)
   XSDebug(fireLatch, "bankIdxInOrder:")
   for (i <- 0 until BtbBanks){ XSDebug(fireLatch, "%d ", bankIdxInOrder(i))}
   XSDebug(fireLatch, "\n")

src/main/scala/xiangshan/frontend/jbtac.scala

@@ -140,6 +140,8 @@ class JBTAC extends XSModule {
 
   XSDebug(io.in.pc.fire(), "read: pc=0x%x, histXORAddr=0x%x, bank=%d, row=%d, hist=%b\n",
     io.in.pc.bits, histXORAddr, readBank, readRow, io.in.hist)
+  XSDebug("out: hit=%d tgt=%x hitIdx=%d iRVILateJump=%d\n",
+    io.out.hit, io.out.target, io.out.hitIdx, io.out.isRVILateJump)
   XSDebug(fireLatch, "read_resp: pc=0x%x, bank=%d, row=%d, target=0x%x, offset=%d, hit=%d\n",
     io.in.pcLatch, readBankLatch, readRowLatch, readEntries(readBankLatch).target, readEntries(readBankLatch).offset, outHit)
   XSDebug(io.redirectValid, "update_req: fetchPC=0x%x, writeValid=%d, hist=%b, bank=%d, row=%d, target=0x%x, offset=%d, type=0x%d\n",