pc: SignExt to XLEN for pc as imm and pc for difftest

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -122,7 +122,7 @@ class Dispatch2Int extends XSModule {
 
     io.enqIQData(i) := DontCare
     io.enqIQData(i).src1 := Mux(uopReg(i).ctrl.src1Type === SrcType.pc,
-      uopReg(i).cf.pc, io.readRf(readPortIndexReg(i)).data)
+      SignExt(uopReg(i).cf.pc, XLEN), io.readRf(readPortIndexReg(i)).data)
     io.enqIQData(i).src2 := Mux(uopReg(i).ctrl.src2Type === SrcType.imm,
       uopReg(i).ctrl.imm, io.readRf(readPortIndexReg(i) + 1.U).data)
 

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -169,10 +169,12 @@ class Roq extends XSModule {
 
         when(io.commits(i).valid){v := false.B}
         XSInfo(io.commits(i).valid,
-          "retired pc %x wen %d ldst %d data %x\n",
+          "retired pc %x wen %d ldest %d pdest %x old_pdest %x data %x\n",
           commitUop.cf.pc,
           commitUop.ctrl.rfWen,
           commitUop.ctrl.ldest,
+          commitUop.pdest,
+          commitUop.old_pdest,
           exuData(commitIdx)
         )
         XSInfo(io.commits(i).valid && exuDebug(commitIdx).isMMIO,
@@ -298,7 +300,7 @@ class Roq extends XSModule {
   val wen = Wire(Vec(CommitWidth, Bool()))
   val wdata = Wire(Vec(CommitWidth, UInt(XLEN.W)))
   val wdst = Wire(Vec(CommitWidth, UInt(32.W)))
-  val wpc = Wire(Vec(CommitWidth, UInt(VAddrBits.W)))
+  val wpc = Wire(Vec(CommitWidth, UInt(XLEN.W)))
   val trapVec = Wire(Vec(CommitWidth, Bool()))
   val isRVC = Wire(Vec(CommitWidth, Bool()))
   for(i <- 0 until CommitWidth){
@@ -309,7 +311,7 @@ class Roq extends XSModule {
     wen(i) := io.commits(i).valid && uop.ctrl.rfWen && uop.ctrl.ldest =/= 0.U
     wdata(i) := exuData(idx)
     wdst(i) := uop.ctrl.ldest
-    wpc(i) := uop.cf.pc
+    wpc(i) := SignExt(uop.cf.pc, XLEN)
     trapVec(i) := io.commits(i).valid && (state===s_idle) && uop.ctrl.isXSTrap
     isRVC(i) := uop.cf.brUpdate.pd.isRVC
   }
@@ -320,7 +322,7 @@ class Roq extends XSModule {
   ExcitingUtils.addSink(difftestIntrNO, "difftestIntrNOfromCSR")
   XSDebug(difftestIntrNO =/= 0.U, "difftest intrNO set %x\n", difftestIntrNO)
   val retireCounterFix = Mux(io.redirect.valid, 1.U, retireCounter)
-  val retirePCFix = Mux(io.redirect.valid, microOp(deqPtr).cf.pc, microOp(firstValidCommit).cf.pc)
+  val retirePCFix = SignExt(Mux(io.redirect.valid, microOp(deqPtr).cf.pc, microOp(firstValidCommit).cf.pc), XLEN)
   val retireInstFix = Mux(io.redirect.valid, microOp(deqPtr).cf.instr, microOp(firstValidCommit).cf.instr)
   if(!env.FPGAPlatform){
     BoringUtils.addSource(RegNext(retireCounterFix), "difftestCommit")
@@ -337,7 +339,7 @@ class Roq extends XSModule {
 
     val hitTrap = trapVec.reduce(_||_)
     val trapCode = PriorityMux(wdata.zip(trapVec).map(x => x._2 -> x._1))
-    val trapPC = PriorityMux(wpc.zip(trapVec).map(x => x._2 ->x._1))
+    val trapPC = SignExt(PriorityMux(wpc.zip(trapVec).map(x => x._2 ->x._1)), XLEN)
 
     ExcitingUtils.addSource(RegNext(hitTrap), "trapValid")
     ExcitingUtils.addSource(RegNext(trapCode), "trapCode")

src/test/scala/top/XSSim.scala

@@ -18,13 +18,13 @@ import xstransforms.ShowPrintTransform
 class DiffTestIO extends XSBundle {
   val r = Output(Vec(64, UInt(XLEN.W)))
   val commit = Output(UInt(32.W))
-  val thisPC = Output(UInt(VAddrBits.W))
+  val thisPC = Output(UInt(XLEN.W))
   val thisINST = Output(UInt(32.W))
   val skip = Output(UInt(32.W))
   val wen = Output(UInt(32.W))
   val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6
   val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6
-  val wpc = Output(Vec(CommitWidth, UInt(VAddrBits.W))) // set difftest width to 6
+  val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6
   val isRVC = Output(Bool())
   val intrNO = Output(UInt(64.W))