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21732575
编写于
12月 03, 2020
作者:
Y
Yinan Xu
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
replay: send redirect when replay
上级
5e5d3dcb
变更
9
隐藏空白更改
内联
并排
Showing
9 changed file
with
64 addition
and
52 deletion
+64
-52
src/main/scala/xiangshan/backend/CtrlBlock.scala
src/main/scala/xiangshan/backend/CtrlBlock.scala
+26
-21
src/main/scala/xiangshan/backend/brq/Brq.scala
src/main/scala/xiangshan/backend/brq/Brq.scala
+8
-3
src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala
src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala
+1
-1
src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
+1
-1
src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
+1
-1
src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
...main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
+3
-3
src/main/scala/xiangshan/backend/roq/Roq.scala
src/main/scala/xiangshan/backend/roq/Roq.scala
+8
-8
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
+10
-8
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
+6
-6
未找到文件。
src/main/scala/xiangshan/backend/CtrlBlock.scala
浏览文件 @
21732575
...
...
@@ -2,6 +2,7 @@ package xiangshan.backend
import
chisel3._
import
chisel3.util._
import
utils._
import
xiangshan._
import
xiangshan.backend.decode.
{
DecodeBuffer
,
DecodeStage
}
import
xiangshan.backend.rename.
{
Rename
,
BusyTable
}
...
...
@@ -37,7 +38,7 @@ class CtrlToLsBlockIO extends XSBundle {
val
redirect
=
ValidIO
(
new
Redirect
)
}
class
CtrlBlock
extends
XSModule
{
class
CtrlBlock
extends
XSModule
with
HasCircularQueuePtrHelper
{
val
io
=
IO
(
new
Bundle
{
val
frontend
=
Flipped
(
new
FrontendToBackendIO
)
val
fromIntBlock
=
Flipped
(
new
IntBlockToCtrlIO
)
...
...
@@ -70,18 +71,14 @@ class CtrlBlock extends XSModule {
val
roq
=
Module
(
new
Roq
(
roqWbSize
))
val
redirect
=
Mux
(
roq
.
io
.
redirect
.
valid
,
roq
.
io
.
redirect
,
Mux
(
brq
.
io
.
redirect
.
valid
,
brq
.
io
.
redirect
,
io
.
fromLsBlock
.
replay
)
)
val
lsqIsAfterBrq
=
isAfter
(
io
.
fromLsBlock
.
replay
.
bits
.
roqIdx
,
brq
.
io
.
redirect
.
bits
.
roqIdx
)
val
redirectArb
=
Mux
(
brq
.
io
.
redirect
.
valid
&&
(!
io
.
fromLsBlock
.
replay
.
valid
||
lsqIsAfterBrq
),
brq
.
io
.
redirect
.
bits
,
io
.
fromLsBlock
.
replay
.
bits
)
val
redirectValid
=
roq
.
io
.
redirect
.
valid
||
brq
.
io
.
redirect
.
valid
||
io
.
fromLsBlock
.
replay
.
valid
val
redirect
=
Mux
(
roq
.
io
.
redirect
.
valid
,
roq
.
io
.
redirect
.
bits
,
redirectArb
)
io
.
frontend
.
redirect
.
valid
:=
r
oq
.
io
.
redirect
.
valid
||
brq
.
io
.
redirect
.
v
alid
io
.
frontend
.
redirect
.
bits
:=
Mux
(
brq
.
io
.
redirect
.
valid
,
brq
.
io
.
redirect
.
bits
.
target
,
roq
.
io
.
redirect
.
bits
.
target
)
io
.
frontend
.
redirect
.
valid
:=
r
edirectV
alid
io
.
frontend
.
redirect
.
bits
:=
Mux
(
roq
.
io
.
redirect
.
valid
,
roq
.
io
.
redirect
.
bits
.
target
,
redirectArb
.
target
)
io
.
frontend
.
outOfOrderBrInfo
<>
brq
.
io
.
outOfOrderBrInfo
io
.
frontend
.
inOrderBrInfo
<>
brq
.
io
.
inOrderBrInfo
...
...
@@ -97,15 +94,18 @@ class CtrlBlock extends XSModule {
brq
.
io
.
exuRedirect
<>
io
.
fromIntBlock
.
exuRedirect
decBuf
.
io
.
isWalking
:=
roq
.
io
.
commits
(
0
).
valid
&&
roq
.
io
.
commits
(
0
).
bits
.
isWalk
decBuf
.
io
.
redirect
<>
redirect
decBuf
.
io
.
redirect
.
valid
<>
redirectValid
decBuf
.
io
.
redirect
.
bits
<>
redirect
decBuf
.
io
.
out
<>
rename
.
io
.
in
rename
.
io
.
redirect
<>
redirect
rename
.
io
.
redirect
.
valid
<>
redirectValid
rename
.
io
.
redirect
.
bits
<>
redirect
rename
.
io
.
roqCommits
<>
roq
.
io
.
commits
rename
.
io
.
out
<>
dispatch
.
io
.
fromRename
rename
.
io
.
renameBypass
<>
dispatch
.
io
.
renameBypass
dispatch
.
io
.
redirect
<>
redirect
dispatch
.
io
.
redirect
.
valid
<>
redirectValid
dispatch
.
io
.
redirect
.
bits
<>
redirect
dispatch
.
io
.
enqRoq
<>
roq
.
io
.
enq
dispatch
.
io
.
enqLsq
<>
io
.
toLsBlock
.
enqLsq
dispatch
.
io
.
dequeueRoqIndex
.
valid
:=
roq
.
io
.
commitRoqIndex
.
valid
||
io
.
oldestStore
.
valid
...
...
@@ -126,7 +126,7 @@ class CtrlBlock extends XSModule {
dispatch
.
io
.
enqIQData
<>
io
.
toIntBlock
.
enqIqData
++
io
.
toFpBlock
.
enqIqData
++
io
.
toLsBlock
.
enqIqData
val
flush
=
redirect
.
valid
&&
(
redirect
.
bits
.
isException
||
redirect
.
bits
.
isFlushPipe
)
val
flush
=
redirect
Valid
&&
(
redirect
.
isException
||
redirect
.
isFlushPipe
)
fpBusyTable
.
io
.
flush
:=
flush
intBusyTable
.
io
.
flush
:=
flush
for
((
wb
,
setPhyRegRdy
)
<-
io
.
fromIntBlock
.
wbRegs
.
zip
(
intBusyTable
.
io
.
wbPregs
)){
...
...
@@ -148,8 +148,10 @@ class CtrlBlock extends XSModule {
fpBusyTable
.
io
.
replayPregs
(
i
).
bits
:=
dispatch
.
io
.
replayPregReq
(
i
).
preg
}
roq
.
io
.
memRedirect
<>
io
.
fromLsBlock
.
replay
roq
.
io
.
brqRedirect
<>
brq
.
io
.
redirect
roq
.
io
.
memRedirect
:=
DontCare
roq
.
io
.
memRedirect
.
valid
:=
false
.
B
roq
.
io
.
brqRedirect
.
valid
:=
brq
.
io
.
redirect
.
valid
||
io
.
fromLsBlock
.
replay
.
valid
roq
.
io
.
brqRedirect
.
bits
<>
redirectArb
roq
.
io
.
exeWbResults
.
take
(
roqWbSize
-
1
).
zip
(
io
.
fromIntBlock
.
wbRegs
++
io
.
fromFpBlock
.
wbRegs
++
io
.
fromLsBlock
.
stOut
).
foreach
{
...
...
@@ -159,9 +161,12 @@ class CtrlBlock extends XSModule {
}
roq
.
io
.
exeWbResults
.
last
:=
brq
.
io
.
out
io
.
toIntBlock
.
redirect
:=
redirect
io
.
toFpBlock
.
redirect
:=
redirect
io
.
toLsBlock
.
redirect
:=
redirect
io
.
toIntBlock
.
redirect
.
valid
:=
redirectValid
io
.
toIntBlock
.
redirect
.
bits
:=
redirect
io
.
toFpBlock
.
redirect
.
valid
:=
redirectValid
io
.
toFpBlock
.
redirect
.
bits
:=
redirect
io
.
toLsBlock
.
redirect
.
valid
:=
redirectValid
io
.
toLsBlock
.
redirect
.
bits
:=
redirect
// roq to int block
io
.
roqio
.
toCSR
<>
roq
.
io
.
csr
...
...
src/main/scala/xiangshan/backend/brq/Brq.scala
浏览文件 @
21732575
...
...
@@ -224,16 +224,21 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
// misprediction or replay
stateQueue
.
zipWithIndex
.
foreach
({
case
(
s
,
i
)
=>
val
ptr
=
BrqPtr
(
brQueue
(
i
).
ptrFlag
,
i
.
U
)
when
(
s
.
isWb
&&
brQueue
(
i
).
exuOut
.
uop
.
roqIdx
.
needFlush
(
io
.
memRedirect
)){
when
(
io
.
memRedirect
.
valid
&&
ptr
.
needBrFlush
(
io
.
memRedirect
.
bits
.
brTag
)){
s
:=
s_idle
}
when
(
io
.
redirect
.
valid
&&
ptr
.
needBrFlush
(
io
.
redirect
.
bits
.
brTag
)){
s
:=
s_invalid
}
})
when
(
io
.
redirect
.
valid
){
// Only Br Mispred reset tailPtr, replay does not
tailPtr
:=
io
.
redirect
.
bits
.
brTag
+
true
.
B
when
(
io
.
redirect
.
valid
||
io
.
memRedirect
.
valid
){
when
(!
io
.
memRedirect
.
valid
||
isAfter
(
io
.
memRedirect
.
bits
.
brTag
,
io
.
redirect
.
bits
.
brTag
))
{
tailPtr
:=
io
.
redirect
.
bits
.
brTag
+
1.
U
}.
otherwise
{
tailPtr
:=
io
.
memRedirect
.
bits
.
brTag
+
1.
U
}
}
}
...
...
src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala
浏览文件 @
21732575
...
...
@@ -24,7 +24,7 @@ class DecodeBuffer extends XSModule {
})
)
val
flush
=
io
.
redirect
.
valid
&&
!
io
.
redirect
.
bits
.
isReplay
val
flush
=
io
.
redirect
.
valid
//
&& !io.redirect.bits.isReplay
for
(
i
<-
0
until
RenameWidth
){
when
(
io
.
out
(
i
).
fire
()){
...
...
src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
浏览文件 @
21732575
...
...
@@ -67,7 +67,7 @@ class Dispatch extends XSModule {
// pipeline between rename and dispatch
// accepts all at once
val
redirectValid
=
io
.
redirect
.
valid
&&
!
io
.
redirect
.
bits
.
isReplay
val
redirectValid
=
io
.
redirect
.
valid
//
&& !io.redirect.bits.isReplay
for
(
i
<-
0
until
RenameWidth
)
{
PipelineConnect
(
io
.
fromRename
(
i
),
dispatch1
.
io
.
fromRename
(
i
),
dispatch1
.
io
.
recv
(
i
),
redirectValid
)
}
...
...
src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
浏览文件 @
21732575
...
...
@@ -122,7 +122,7 @@ class Dispatch1 extends XSModule {
* acquire ROQ (all), LSQ (load/store only) and dispatch queue slots
* only set valid when all of them provides enough entries
*/
val
redirectValid
=
io
.
redirect
.
valid
&&
!
io
.
redirect
.
bits
.
isReplay
val
redirectValid
=
io
.
redirect
.
valid
//
&& !io.redirect.bits.isReplay
val
allResourceReady
=
io
.
enqLsq
.
canAccept
&&
io
.
enqRoq
.
canAccept
&&
io
.
toIntDqReady
&&
io
.
toFpDqReady
&&
io
.
toLsDqReady
// Instructions should enter dispatch queues in order.
...
...
src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
浏览文件 @
21732575
...
...
@@ -62,7 +62,7 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, replayWidth: Int) exten
val
allWalkDone
=
!
io
.
inReplayWalk
&&
io
.
otherWalkDone
val
canEnqueue
=
validEntries
<=
(
size
-
enqnum
).
U
&&
allWalkDone
val
canActualEnqueue
=
canEnqueue
&&
!(
io
.
redirect
.
valid
&&
!
io
.
redirect
.
bits
.
isReplay
)
val
canActualEnqueue
=
canEnqueue
&&
!(
io
.
redirect
.
valid
/*&& !io.redirect.bits.isReplay*/
)
/**
* Part 1: update states and uops when enqueue, dequeue, commit, redirect/replay
...
...
@@ -109,7 +109,7 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, replayWidth: Int) exten
}
// redirect: cancel uops currently in the queue
val
mispredictionValid
=
io
.
redirect
.
valid
&&
io
.
redirect
.
bits
.
isMisPred
val
mispredictionValid
=
io
.
redirect
.
valid
//
&& io.redirect.bits.isMisPred
val
exceptionValid
=
io
.
redirect
.
valid
&&
io
.
redirect
.
bits
.
isException
val
flushPipeValid
=
io
.
redirect
.
valid
&&
io
.
redirect
.
bits
.
isFlushPipe
val
roqNeedFlush
=
Wire
(
Vec
(
size
,
Bool
()))
...
...
@@ -128,7 +128,7 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, replayWidth: Int) exten
}
// replay: from s_dispatched to s_valid
val
replayValid
=
io
.
redirect
.
valid
&&
io
.
redirect
.
bits
.
isReplay
val
replayValid
=
false
.
B
//
io.redirect.valid && io.redirect.bits.isReplay
val
needReplay
=
Wire
(
Vec
(
size
,
Bool
()))
for
(
i
<-
0
until
size
)
{
needReplay
(
i
)
:=
roqNeedFlush
(
i
)
&&
stateEntries
(
i
)
===
s_dispatched
&&
replayValid
...
...
src/main/scala/xiangshan/backend/roq/Roq.scala
浏览文件 @
21732575
...
...
@@ -425,14 +425,14 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
}
// rollback: write all
// when rollback, reset writebacked entry to valid
when
(
io
.
memRedirect
.
valid
)
{
// TODO: opt timing
for
(
i
<-
0
until
RoqSize
)
{
val
recRoqIdx
=
RoqPtr
(
flagBkup
(
i
),
i
.
U
)
when
(
valid
(
i
)
&&
isAfter
(
recRoqIdx
,
io
.
memRedirect
.
bits
.
roqIdx
))
{
writebacked
(
i
)
:=
false
.
B
}
}
}
//
when(io.memRedirect.valid) { // TODO: opt timing
//
for (i <- 0 until RoqSize) {
//
val recRoqIdx = RoqPtr(flagBkup(i), i.U)
//
when (valid(i) && isAfter(recRoqIdx, io.memRedirect.bits.roqIdx)) {
//
writebacked(i) := false.B
//
}
//
}
//
}
// read
// deqPtrWritebacked
...
...
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
浏览文件 @
21732575
...
...
@@ -433,6 +433,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
rollback
(
i
).
bits
.
isMisPred
:=
false
.
B
rollback
(
i
).
bits
.
isException
:=
false
.
B
rollback
(
i
).
bits
.
isFlushPipe
:=
false
.
B
rollback
(
i
).
bits
.
target
:=
rollbackUop
.
cf
.
pc
rollback
(
i
).
bits
.
brTag
:=
rollbackUop
.
brTag
XSDebug
(
l1Violation
,
...
...
@@ -529,15 +531,15 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
for
(
i
<-
0
until
LoadQueueSize
)
{
needCancel
(
i
)
:=
uop
(
i
).
roqIdx
.
needFlush
(
io
.
brqRedirect
)
&&
allocated
(
i
)
&&
!
commited
(
i
)
when
(
needCancel
(
i
))
{
when
(
io
.
brqRedirect
.
bits
.
isReplay
){
valid
(
i
)
:=
false
.
B
writebacked
(
i
)
:=
false
.
B
listening
(
i
)
:=
false
.
B
miss
(
i
)
:=
false
.
B
pending
(
i
)
:=
false
.
B
}.
otherwise
{
//
when(io.brqRedirect.bits.isReplay){
//
valid(i) := false.B
//
writebacked(i) := false.B
//
listening(i) := false.B
//
miss(i) := false.B
//
pending(i) := false.B
//
}.otherwise{
allocated
(
i
)
:=
false
.
B
}
//
}
}
}
when
(
io
.
brqRedirect
.
valid
&&
io
.
brqRedirect
.
bits
.
isMisPred
)
{
...
...
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
浏览文件 @
21732575
...
...
@@ -340,13 +340,13 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
for
(
i
<-
0
until
StoreQueueSize
)
{
needCancel
(
i
)
:=
uop
(
i
).
roqIdx
.
needFlush
(
io
.
brqRedirect
)
&&
allocated
(
i
)
&&
!
commited
(
i
)
when
(
needCancel
(
i
))
{
when
(
io
.
brqRedirect
.
bits
.
isReplay
){
datavalid
(
i
)
:=
false
.
B
writebacked
(
i
)
:=
false
.
B
pending
(
i
)
:=
false
.
B
}.
otherwise
{
//
when(io.brqRedirect.bits.isReplay){
//
datavalid(i) := false.B
//
writebacked(i) := false.B
//
pending(i) := false.B
//
}.otherwise{
allocated
(
i
)
:=
false
.
B
}
//
}
}
}
when
(
io
.
brqRedirect
.
valid
&&
io
.
brqRedirect
.
bits
.
isMisPred
)
{
...
...
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