Merge pull request #202 from RISCVERS/debian-gogogo

bug fixes

Makefile

@@ -121,6 +121,7 @@ endif
 EMU_FLAGS = -s $(SEED) -b $(B) -e $(E) $(SNAPSHOT_OPTION) $(WAVEFORM)
 
 emu: $(EMU)
+	ls build
 	$(EMU) -i $(IMAGE) $(EMU_FLAGS)
 
 cache:

src/main/scala/device/TLTimer.scala

@@ -27,7 +27,7 @@ class TLTimer(address: Seq[AddressSet], sim: Boolean)(implicit p: Parameters) ex
 
     val clk = (if (!sim) 40 /* 40MHz / 1000000 */ else 100)
     val freq = RegInit(clk.U(16.W))
-    val inc = RegInit(1000.U(16.W))
+    val inc = RegInit(1.U(16.W))
 
     val cnt = RegInit(0.U(16.W))
     val nextCnt = cnt + 1.U
@@ -37,7 +37,7 @@ class TLTimer(address: Seq[AddressSet], sim: Boolean)(implicit p: Parameters) ex
 
     if (sim) {
       val isWFI = WireInit(false.B)
-      BoringUtils.addSink(isWFI, "isWFI")
+      ExcitingUtils.addSink(isWFI, "isWFI")
       when (isWFI) { mtime := mtime + 100000.U }
     }
 

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -242,7 +242,7 @@ class Brq extends XSModule {
       val ptr = BrqPtr(brQueue(i).ptrFlag, i.U)
       when(
         (io.redirect.valid && ptr.needBrFlush(io.redirect.bits.brTag)) ||
-          (!s.isIdle && brQueue(i).exuOut.uop.needFlush(io.memRedirect))
+          (s.isWb && brQueue(i).exuOut.uop.needFlush(io.memRedirect))
       ){
         s := s_idle
       }

src/main/scala/xiangshan/backend/decode/DecodeHelper.scala

@@ -54,12 +54,10 @@ object Instructions extends HasInstrType with HasXSParameter {
       RVZicsrInstr.table ++
       RVZifenceiInstr.table ++
       Privileged.table ++
-      RVFInstr.table ++
-      RVDInstr.table ++
       RVAInstr.table ++
       (if (HasMExtension) RVMInstr.table else Nil) ++
-      (if (HasCExtension) RVCInstr.table else Nil) // ++
-//    (if (HasFPU) RVFInstr.table ++ RVDInstr.table else Nil) ++
+      (if (HasCExtension) RVCInstr.table else Nil) ++
+      (if (HasFPU) RVFInstr.table ++ RVDInstr.table else Nil)
 //    Privileged.table ++
 //    RVAInstr.table ++
 //    RVZicsrInstr.table

src/main/scala/xiangshan/backend/decode/isa/Privileged.scala

@@ -21,7 +21,8 @@ object Privileged extends HasInstrType {
     MRET           -> List(InstrI, FuType.csr, CSROpType.jmp),
     SRET           -> List(InstrI, FuType.csr, CSROpType.jmp),
     SFANCE_VMA     -> List(InstrI, FuType.fence, FenceOpType.sfence), // NOTE: Ignore Src2, no need for asid
-    FENCE          -> List(InstrU, FuType.fence, FenceOpType.fence)
+    FENCE          -> List(InstrU, FuType.fence, FenceOpType.fence),
+    WFI            -> List(InstrU, FuType.alu, ALUOpType.sll)
 //    FENCE          -> List(InstrS, FuType.alu, ALUOpType.add), // nop    InstrS -> !wen
 //    WFI            -> List(InstrI, FuType.alu, ALUOpType.add) // nop
     // FENCE          -> List(InstrB, FuType.mou, MOUOpType.fencei)

src/main/scala/xiangshan/backend/decode/isa/RVC.scala

@@ -57,13 +57,13 @@ object RVCInstr extends HasInstrType with HasRVCConst {
 //   def C_XX    = BitPat("b????????????????_???_?_10_987_65_432_10")
   def C_ILLEGAL  = BitPat("b0000000000000000_000_0_00_000_00_000_00")
   def C_ADDI4SPN = BitPat("b????????????????_000_?_??_???_??_???_00")
-  def C_FLD      = BitPat("b????????????????_001_?_??_???_??_???_00")
+  // def C_FLD      = BitPat("b????????????????_001_?_??_???_??_???_00")
 //   def C_LQ    = BitPat("b????????????????_001_?_??_???_??_???_00")
   def C_LW       = BitPat("b????????????????_010_?_??_???_??_???_00")
 //   def C_FLW   = BitPat("b????????????????_011_?_??_???_??_???_00") // RV32FC Only
   def C_LD       = BitPat("b????????????????_011_?_??_???_??_???_00")
   // def C_LI    = BitPat("b????????????????_100_?_??_???_??_???_00") //reserved
-  def C_FSD      = BitPat("b????????????????_101_?_??_???_??_???_00")
+  // def C_FSD      = BitPat("b????????????????_101_?_??_???_??_???_00")
 //   def C_SQ    = BitPat("b????????????????_101_?_??_???_??_???_00")
   def C_SW       = BitPat("b????????????????_110_?_??_???_??_???_00")
 //   def C_FSW   = BitPat("b????????????????_111_?_??_???_??_???_00") // RV32FC Only
@@ -97,7 +97,7 @@ object RVCInstr extends HasInstrType with HasRVCConst {
   //RVC 11
   def C_SLLI    = BitPat("b????????????????_000_?_??_???_??_???_10")
 //   def C_SLLI64  = BitPat("b????????????????_000_0_??_???_00_000_10")
-  def C_FLDSP   = BitPat("b????????????????_001_?_??_???_??_???_10")
+  // def C_FLDSP   = BitPat("b????????????????_001_?_??_???_??_???_10")
 //   def C_LQSP    = BitPat("b????????????????_001_?_??_???_??_???_10")
   def C_LWSP    = BitPat("b????????????????_010_?_??_???_??_???_10")
 //  def C_FLWSP   = BitPat("b????????????????_011_?_??_???_??_???_10") // RV32FC Only
@@ -107,8 +107,8 @@ object RVCInstr extends HasInstrType with HasRVCConst {
   def C_EBREAK  = BitPat("b????????????????_100_1_00_000_00_000_10")
   def C_JALR    = BitPat("b????????????????_100_1_??_???_00_000_10")
   def C_ADD     = BitPat("b????????????????_100_1_??_???_??_???_10")
-  def C_FSDSP   = BitPat("b????????????????_101_?_??_???_??_???_10")
-//   def C_SQSP    = BitPat("b????????????????_101_?_??_???_??_???_10")
+  // def C_FSDSP   = BitPat("b????????????????_101_?_??_???_??_???_10")
+  // def C_SQSP    = BitPat("b????????????????_101_?_??_???_??_???_10")
   def C_SWSP    = BitPat("b????????????????_110_?_??_???_??_???_10")
 //  def C_FSWSP   = BitPat("b????????????????_111_?_??_???_??_???_10") // RV32FC Only
   def C_SDSP    = BitPat("b????????????????_111_?_??_???_??_???_10")
@@ -121,10 +121,10 @@ object RVCInstr extends HasInstrType with HasRVCConst {
   val table = Array(
     C_ILLEGAL    -> List(InstrN, FuType.csr, CSROpType.jmp),
     C_ADDI4SPN   -> List(InstrI, FuType.alu, ALUOpType.add),
-    C_FLD        -> List(InstrFI, FuType.ldu, LSUOpType.ld),
+    // C_FLD        -> List(InstrFI, FuType.ldu, LSUOpType.ld),
     C_LW         -> List(InstrI, FuType.ldu, LSUOpType.lw),
     C_LD         -> List(InstrI, FuType.ldu, LSUOpType.ld),
-    C_FSD        -> List(InstrFS, FuType.stu, LSUOpType.sd),
+    // C_FSD        -> List(InstrFS, FuType.stu, LSUOpType.sd),
     C_SW         -> List(InstrS, FuType.stu, LSUOpType.sw),
     C_SD         -> List(InstrS, FuType.stu, LSUOpType.sd),
     C_NOP        -> List(InstrI, FuType.alu, ALUOpType.add),
@@ -164,10 +164,10 @@ object RVCInstr extends HasInstrType with HasRVCConst {
 
    val cExtraTable = Array(
     C_ADDI4SPN   -> List(ImmADD4SPN, REGx2, DtCare, REGrs2p),
-    C_FLD        -> List(ImmLD, REGrs1p, DtCare, REGrs2p),
+    // C_FLD        -> List(ImmLD, REGrs1p, DtCare, REGrs2p),
     C_LW         -> List(ImmLW, REGrs1p, DtCare, REGrs2p),
     C_LD         -> List(ImmLD, REGrs1p, DtCare, REGrs2p),
-    C_FSD        -> List(ImmSD, REGrs1p, REGrs2p, DtCare),
+    // C_FSD        -> List(ImmSD, REGrs1p, REGrs2p, DtCare),
     C_SW         -> List(ImmSW, REGrs1p, REGrs2p, DtCare),
     C_SD         -> List(ImmSD, REGrs1p, REGrs2p, DtCare),
     C_NOP        -> List(ImmNone, DtCare, DtCare, DtCare),
@@ -190,7 +190,7 @@ object RVCInstr extends HasInstrType with HasRVCConst {
     C_BEQZ       -> List(ImmB, REGrs1p, DtCare, DtCare), // rd: x0
     C_BNEZ       -> List(ImmB, REGrs1p, DtCare, DtCare), // rd: x0
     C_SLLI       -> List(ImmLI, REGrd, DtCare, REGrd),
-    C_FLDSP      -> List(ImmLDSP, REGx2, DtCare, REGrd),
+    // C_FLDSP      -> List(ImmLDSP, REGx2, DtCare, REGrd),
     // C_LQSP       -> List(),
     C_LWSP       -> List(ImmLWSP, REGx2, DtCare, REGrd),
     C_LDSP       -> List(ImmLDSP, REGx2, DtCare, REGrd),
@@ -199,7 +199,7 @@ object RVCInstr extends HasInstrType with HasRVCConst {
     C_EBREAK     -> List(ImmNone, DtCare, DtCare, DtCare), //not implemented
     C_JALR       -> List(ImmNone, REGrs1, DtCare, REGx1),
     C_ADD        -> List(ImmNone, REGrd, REGrs2, REGrd),
-    C_FSDSP      -> List(ImmSDSP, REGx2, REGrs2, DtCare),
+    // C_FSDSP      -> List(ImmSDSP, REGx2, REGrs2, DtCare),
     // C_SQSP       -> List(),
     C_SWSP       -> List(ImmSWSP, REGx2, REGrs2, DtCare),
     C_SDSP       -> List(ImmSDSP, REGx2, REGrs2, DtCare)

src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala

@@ -91,7 +91,7 @@ class Dispatch2Ls extends XSModule {
       enq.bits.src2State := DontCare
     }
     else {
-      enq.bits.src2State := Mux(io.fromDq(indexVec(i)).bits.ctrl.src1Type === SrcType.fp,
+      enq.bits.src2State := Mux(io.fromDq(indexVec(i)).bits.ctrl.src2Type === SrcType.fp,
         io.fpRegRdy(i - exuParameters.LduCnt), io.intRegRdy(readPort(i) + 1))
     }
 

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -595,9 +595,14 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
   val hasLoadAddrMisaligned = io.exception.bits.cf.exceptionVec(loadAddrMisaligned) && io.exception.valid
 
   // mtval write logic
-  val memExceptionAddr = WireInit(0.U(VAddrBits.W))
+  val lsroqExceptionAddr = WireInit(0.U(VAddrBits.W))
+  val atomExceptionAddr = WireInit(0.U(VAddrBits.W))
+  val atomOverrideXtval = WireInit(false.B)
   ExcitingUtils.addSource(io.exception.bits.lsroqIdx, "EXECPTION_LSROQIDX")
-  ExcitingUtils.addSink(memExceptionAddr, "EXECPTION_VADDR")
+  ExcitingUtils.addSink(lsroqExceptionAddr, "EXECPTION_VADDR")
+  ExcitingUtils.addSink(atomExceptionAddr, "ATOM_EXECPTION_VADDR")
+  ExcitingUtils.addSink(atomOverrideXtval, "ATOM_OVERRIDE_XTVAL")
+  val memExceptionAddr = Mux(atomOverrideXtval, atomExceptionAddr, lsroqExceptionAddr)
   when(hasInstrPageFault || hasLoadPageFault || hasStorePageFault){
     val tval = Mux(
       hasInstrPageFault,
@@ -670,6 +675,7 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
   val causeNO = (raiseIntr << (XLEN-1)).asUInt() | Mux(raiseIntr, intrNO, exceptionNO)
   val difftestIntrNO = Mux(raiseIntr, causeNO, 0.U)
   ExcitingUtils.addSource(difftestIntrNO, "difftestIntrNOfromCSR")
+  ExcitingUtils.addSource(causeNO, "difftestCausefromCSR")
 
   val raiseExceptionIntr = io.exception.valid
   val retTarget = Wire(UInt(VAddrBits.W))
@@ -866,6 +872,10 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
     BoringUtils.addSource(mstatus & sstatusRmask, "difftestSstatus")
     BoringUtils.addSource(mepc, "difftestMepc")
     BoringUtils.addSource(sepc, "difftestSepc")
+    BoringUtils.addSource(mtval, "difftestMtval")
+    BoringUtils.addSource(stval, "difftestStval")
+    BoringUtils.addSource(mtvec, "difftestMtvec")
+    BoringUtils.addSource(stvec, "difftestStvec")
     BoringUtils.addSource(mcause, "difftestMcause")
     BoringUtils.addSource(scause, "difftestScause")
     BoringUtils.addSource(satp, "difftestSatp")

src/main/scala/xiangshan/backend/rename/FreeList.scala

@@ -99,7 +99,7 @@ class FreeList extends XSModule with HasFreeListConsts {
 
   headPtr := Mux(io.redirect.valid, // mispredict or exception happen
     Mux(io.redirect.bits.isException || io.redirect.bits.isFlushPipe, // TODO: need check by JiaWei
-      FreeListPtr(!tailPtr.flag, tailPtr.value),
+      FreeListPtr(!tailPtrNext.flag, tailPtrNext.value),
       Mux(io.redirect.bits.isMisPred,
         checkPoints(io.redirect.bits.brTag.value),
         headPtrNext // replay

src/main/scala/xiangshan/backend/rename/RenameTable.scala

@@ -47,6 +47,9 @@ class RenameTable(float: Boolean) extends XSModule {
 
   when(io.flush){
     spec_table := arch_table
+    for(w <- io.archWritePorts) {
+      when(w.wen){ spec_table(w.addr) := w.wdata }
+    }
   }
 
   BoringUtils.addSource(arch_table, if(float) "DEBUG_FP_ARCH_RAT" else "DEBUG_INI_ARCH_RAT")

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -7,6 +7,7 @@ import xiangshan._
 import utils._
 import chisel3.util.experimental.BoringUtils
 import xiangshan.backend.LSUOpType
+import xiangshan.backend.decode.isa.Privileged.WFI
 
 
 class Roq extends XSModule {
@@ -114,15 +115,12 @@ class Roq extends XSModule {
   ExcitingUtils.addSink(trapTarget, "trapTarget")
 
   val deqUop = microOp(deqPtr)
-  val intrEnable = intrBitSet && (state === s_idle) && !isEmpty && !hasNoSpec // TODO: wanna check why has hasCsr(hasNoSpec)
-  val exceptionEnable = Cat(deqUop.cf.exceptionVec).orR() && (state === s_idle) && !isEmpty
-  // TODO: need check if writebacked needed
-  val isEcall = deqUop.cf.exceptionVec(ecallM) ||
-    deqUop.cf.exceptionVec(ecallS) ||
-    deqUop.cf.exceptionVec(ecallU)
-  val isFlushPipe = (deqUop.ctrl.flushPipe && writebacked(deqPtr) && valid(deqPtr) && (state === s_idle) && !isEmpty)
+  val deqPtrWritebacked = writebacked(deqPtr) && valid(deqPtr)
+  val intrEnable = intrBitSet && !isEmpty && !hasNoSpec // TODO: wanna check why has hasCsr(hasNoSpec)
+  val exceptionEnable = deqPtrWritebacked && Cat(deqUop.cf.exceptionVec).orR()
+  val isFlushPipe = deqPtrWritebacked && deqUop.ctrl.flushPipe
   io.redirect := DontCare
-  io.redirect.valid := intrEnable || exceptionEnable || isFlushPipe// TODO: add fence flush to flush the whole pipe
+  io.redirect.valid := (state === s_idle) && (intrEnable || exceptionEnable || isFlushPipe)// TODO: add fence flush to flush the whole pipe
   io.redirect.bits.isException := intrEnable || exceptionEnable
   io.redirect.bits.isFlushPipe := isFlushPipe
   io.redirect.bits.target := Mux(isFlushPipe, deqUop.cf.pc + 4.U, trapTarget)
@@ -240,6 +238,9 @@ class Roq extends XSModule {
   // commit branch to brq
   io.bcommit := PopCount(cfiCommitVec)
 
+  val hasWFI = io.commits.map(c => c.valid && state===s_idle && c.bits.uop.cf.instr===WFI).reduce(_||_)
+  ExcitingUtils.addSource(hasWFI, "isWFI")
+
   // when redirect, walk back roq entries
   when(io.brqRedirect.valid){ // TODO: need check if consider exception redirect?
     state := s_walk
@@ -337,7 +338,10 @@ class Roq extends XSModule {
   instrCnt := instrCnt + retireCounter
 
   val difftestIntrNO = WireInit(0.U(XLEN.W))
+  val difftestCause = WireInit(0.U(XLEN.W))
   ExcitingUtils.addSink(difftestIntrNO, "difftestIntrNOfromCSR")
+  ExcitingUtils.addSink(difftestCause, "difftestCausefromCSR")
+
   XSDebug(difftestIntrNO =/= 0.U, "difftest intrNO set %x\n", difftestIntrNO)
   val retireCounterFix = Mux(io.redirect.valid, 1.U, retireCounter)
   val retirePCFix = SignExt(Mux(io.redirect.valid, microOp(deqPtr).cf.pc, microOp(firstValidCommit).cf.pc), XLEN)
@@ -355,6 +359,7 @@ class Roq extends XSModule {
     BoringUtils.addSource(RegNext(wdst), "difftestWdst")
     BoringUtils.addSource(RegNext(scFailed), "difftestScFailed")
     BoringUtils.addSource(RegNext(difftestIntrNO), "difftestIntrNO")
+    BoringUtils.addSource(RegNext(difftestCause), "difftestCause")
 
     val hitTrap = trapVec.reduce(_||_)
     val trapCode = PriorityMux(wdata.zip(trapVec).map(x => x._2 -> x._1))

src/main/scala/xiangshan/mem/AtomicsUnit.scala

@@ -15,6 +15,7 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
     val dtlb          = new TlbRequestIO
     val flush_sbuffer = new SbufferFlushBundle
     val tlbFeedback   = ValidIO(new TlbFeedback)
+    val redirect      = Flipped(ValidIO(new Redirect))
   })
 
   //-------------------------------------------------------
@@ -23,12 +24,18 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
   val s_invalid :: s_tlb  :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7)
   val state = RegInit(s_invalid)
   val in = Reg(new ExuInput())
+  // vaddr for stored for exception
+  val vaddr = Reg(UInt())
+  val atom_override_xtval = RegInit(false.B)
   // paddr after translation
   val paddr = Reg(UInt())
   // dcache response data
   val resp_data = Reg(UInt())
   val is_lrsc_valid = Reg(Bool())
 
+  ExcitingUtils.addSource(vaddr, "ATOM_EXECPTION_VADDR")
+  ExcitingUtils.addSource(atom_override_xtval, "ATOM_OVERRIDE_XTVAL")
+
   // assign default value to output signals
   io.in.ready          := false.B
   io.out.valid         := false.B
@@ -51,6 +58,7 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
     when (io.in.fire()) {
       in := io.in.bits
       state := s_tlb
+      vaddr := in.src1
     }
   }
 
@@ -85,11 +93,13 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
       ))
       in.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned
       in.uop.cf.exceptionVec(storePageFault)      := io.dtlb.resp.bits.excp.pf.st
-      val exception = !addrAligned || io.dtlb.resp.bits.excp.pf.st
+      in.uop.cf.exceptionVec(loadPageFault)       := io.dtlb.resp.bits.excp.pf.ld
+      val exception = !addrAligned || io.dtlb.resp.bits.excp.pf.st || io.dtlb.resp.bits.excp.pf.ld
       when (exception) {
         // check for exceptions
         // if there are exceptions, no need to execute it
         state := s_finish
+        atom_override_xtval := true.B
       } .otherwise {
         paddr := io.dtlb.resp.bits.paddr
         state := s_flush_sbuffer_req
@@ -211,4 +221,8 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
       state := s_invalid
     }
   }
+
+  when(io.redirect.valid){
+    atom_override_xtval := false.B
+  }
 }

src/main/scala/xiangshan/mem/Memend.scala

@@ -206,8 +206,7 @@ class Memend extends XSModule {
   atomicsUnit.io.dcache        <> io.atomics
   atomicsUnit.io.flush_sbuffer.empty := sbEmpty
 
-  atomicsUnit.io.dcache        <> io.atomics
-  atomicsUnit.io.flush_sbuffer.empty := sbEmpty
+  atomicsUnit.io.redirect <> io.backend.redirect
 
   when(atomicsUnit.io.out.valid){
     io.backend.ldout(0) <> atomicsUnit.io.out

src/test/csrc/difftest.cpp

@@ -16,7 +16,9 @@ void (*ref_difftest_memcpy_from_dut)(paddr_t dest, void *src, size_t n) = NULL;
 void (*ref_difftest_memcpy_from_ref)(void *dest, paddr_t src, size_t n) = NULL;
 void (*ref_difftest_getregs)(void *c) = NULL;
 void (*ref_difftest_setregs)(const void *c) = NULL;
-static void (*ref_difftest_sync)(uint64_t *skip) = NULL;
+void (*ref_difftest_get_mastatus)(void *s) = NULL;
+void (*ref_difftest_set_mastatus)(const void *s) = NULL;
+vaddr_t (*ref_disambiguate_exec)(void *disambiguate_para) = NULL;
 static void (*ref_difftest_exec)(uint64_t n) = NULL;
 static void (*ref_difftest_raise_intr)(uint64_t NO) = NULL;
 static void (*ref_isa_reg_display)(void) = NULL;
@@ -58,8 +60,14 @@ void init_difftest() {
   ref_difftest_setregs = (void (*)(const void *))dlsym(handle, "difftest_setregs");
   assert(ref_difftest_setregs);
 
-  ref_difftest_sync = (void (*)(uint64_t *))dlsym(handle, "difftest_sync");
-  assert(ref_difftest_sync);
+  ref_difftest_get_mastatus = (void (*)(void *))dlsym(handle, "difftest_get_mastatus");
+  assert(ref_difftest_get_mastatus);
+
+  ref_difftest_set_mastatus = (void (*)(const void *))dlsym(handle, "difftest_set_mastatus");
+  assert(ref_difftest_set_mastatus);
+
+  ref_disambiguate_exec = (vaddr_t (*)(void *))dlsym(handle, "disambiguate_exec");
+  assert(ref_disambiguate_exec);
 
   ref_difftest_exec = (void (*)(uint64_t))dlsym(handle, "difftest_exec");
   assert(ref_difftest_exec);
@@ -89,7 +97,8 @@ static const char *reg_name[DIFFTEST_NR_REG] = {
   "mstatus", "mcause", "mepc",
   "sstatus", "scause", "sepc",
   "satp", 
-  "mip", "mie", "mscratch", "sscratch", "mideleg", "medeleg"   
+  "mip", "mie", "mscratch", "sscratch", "mideleg", "medeleg", 
+  "mtval", "stval", "mtvec", "stvec", "mode"
 };
 
 static uint64_t nemu_this_pc = 0x80000000;
@@ -147,12 +156,9 @@ int difftest_step(DiffState *s) {
 
   // sync lr/sc reg status
   if(s->sync.scFailed){
-    struct SyncState {
-      uint64_t lrscValid; // sc inst commited, it failed beacuse lr_valid === 0
-      uint64_t lrscAddr;
-    } sync;
+    struct SyncState sync;
     sync.lrscValid = 0;
-    ref_difftest_sync((uint64_t*)&sync); // sync lr/sc microarchitectural regs
+    ref_difftest_set_mastatus((uint64_t*)&sync); // sync lr/sc microarchitectural regs
   }
 
   // single step difftest
@@ -182,7 +188,13 @@ int difftest_step(DiffState *s) {
         ref_difftest_setregs(ref_r);
       }else{
         // single step exec
-        ref_difftest_exec(1);
+        // IPF, LPF, SPF
+        if(s->cause == 12 || s->cause == 13 || s->cause == 15){
+          printf("s->cause %ld\n", s->cause);
+          ref_disambiguate_exec(&s->cause);
+        }else{
+          ref_difftest_exec(1);
+        }
       }
     }
   }

src/test/csrc/difftest.h

@@ -30,15 +30,20 @@ enum {
   DIFFTEST_SSCRATCH,
   DIFFTEST_MIDELEG,
   DIFFTEST_MEDELEG,
+  DIFFTEST_MTVAL,
+  DIFFTEST_STVAL,
+  DIFFTEST_MTVEC,
+  DIFFTEST_STVEC,
   DIFFTEST_MODE,
   DIFFTEST_NR_REG
 };
-// DIFFTEST_MTVAL, DIFFTEST_STVAL will be updated while committing exception
-// Compare / snapshot them is not necessary
 
 struct SyncChannel {
   uint64_t scFailed; // sc inst commited, it failed beacuse lr_valid === 0
-  // uint64_t lrscAddr;
+};
+
+struct SyncState {
+  uint64_t lrscValid;
 };
 
 struct DiffState {
@@ -53,6 +58,7 @@ struct DiffState {
   uint32_t *wdst;
   int wen;
   uint64_t intrNO;
+  uint64_t cause; // for disambiguate_exec
   int priviledgeMode;
 
   // Microarchitucural signal needed to sync status
@@ -66,6 +72,11 @@ extern void (*ref_difftest_memcpy_from_dut)(paddr_t dest, void *src, size_t n);
 extern void (*ref_difftest_memcpy_from_ref)(void *dest, paddr_t src, size_t n);
 extern void (*ref_difftest_getregs)(void *c);
 extern void (*ref_difftest_setregs)(const void *c);
+extern void (*ref_difftest_getregs)(void *c);
+extern void (*ref_difftest_setregs)(const void *c);
+extern void (*ref_difftest_get_mastatus)(void *s);
+extern void (*ref_difftest_set_mastatus)(const void *s);
+extern vaddr_t (*ref_disambiguate_exec)(void *disambiguate_para);
 
 void init_difftest();
 int difftest_step(DiffState *s);

src/test/csrc/emu.cpp

@@ -139,8 +139,6 @@ inline void Emulator::read_emu_regs(uint64_t *r) {
   r[DIFFTEST_SEPC   ] = dut_ptr->io_difftest_sepc;
   r[DIFFTEST_MCAUSE ] = dut_ptr->io_difftest_mcause;
   r[DIFFTEST_SCAUSE ] = dut_ptr->io_difftest_scause;
-  // r[DIFFTEST_MTVAL  ] = dut_ptr->io_difftest_mtval;
-  // r[DIFFTEST_STVAL  ] = dut_ptr->io_difftest_stval;
   r[DIFFTEST_SATP   ] = dut_ptr->io_difftest_satp;
   r[DIFFTEST_MIP    ] = dut_ptr->io_difftest_mip;
   r[DIFFTEST_MIE    ] = dut_ptr->io_difftest_mie;
@@ -148,6 +146,10 @@ inline void Emulator::read_emu_regs(uint64_t *r) {
   r[DIFFTEST_SSCRATCH]= dut_ptr->io_difftest_sscratch;
   r[DIFFTEST_MIDELEG] = dut_ptr->io_difftest_mideleg;
   r[DIFFTEST_MEDELEG] = dut_ptr->io_difftest_medeleg;
+  r[DIFFTEST_MTVAL]   = dut_ptr->io_difftest_mtval;
+  r[DIFFTEST_STVAL]   = dut_ptr->io_difftest_stval;
+  r[DIFFTEST_MTVEC]   = dut_ptr->io_difftest_mtvec;
+  r[DIFFTEST_STVEC]   = dut_ptr->io_difftest_stvec;
   r[DIFFTEST_MODE]    = dut_ptr->io_difftest_priviledgeMode;
 }
 
@@ -256,6 +258,7 @@ uint64_t Emulator::execute(uint64_t n) {
       diff.isRVC = dut_ptr->io_difftest_isRVC;
       diff.wen = dut_ptr->io_difftest_wen;
       diff.intrNO = dut_ptr->io_difftest_intrNO;
+      diff.cause = dut_ptr->io_difftest_cause;
       diff.priviledgeMode = dut_ptr->io_difftest_priviledgeMode;
 
       diff.sync.scFailed = dut_ptr->io_difftest_scFailed;
@@ -359,6 +362,10 @@ void Emulator::snapshot_save(const char *filename) {
   stream.unbuf_write(buf, size);
   delete buf;
 
+  struct SyncState sync_mastate;
+  ref_difftest_get_mastatus(&sync_mastate);
+  stream.unbuf_write(&sync_mastate, sizeof(struct SyncState));
+
   // actually write to file in snapshot_finalize()
 }
 
@@ -384,4 +391,8 @@ void Emulator::snapshot_load(const char *filename) {
   stream.read(buf, size);
   ref_difftest_memcpy_from_dut(0x80000000, buf, size);
   delete buf;
+
+  struct SyncState sync_mastate;
+  stream.read(&sync_mastate, sizeof(struct SyncState));
+  ref_difftest_set_mastatus(&sync_mastate);
 }

src/test/scala/top/XSSim.scala

@@ -27,12 +27,17 @@ class DiffTestIO extends XSBundle {
   val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6
   val isRVC = Output(UInt(32.W))
   val intrNO = Output(UInt(64.W))
+  val cause = Output(UInt(64.W))
 
   val priviledgeMode = Output(UInt(2.W))
   val mstatus = Output(UInt(64.W))
   val sstatus = Output(UInt(64.W))
   val mepc = Output(UInt(64.W))
   val sepc = Output(UInt(64.W))
+  val mtval = Output(UInt(64.W))
+  val stval = Output(UInt(64.W))
+  val mtvec = Output(UInt(64.W))
+  val stvec = Output(UInt(64.W))
   val mcause = Output(UInt(64.W))
   val scause = Output(UInt(64.W))
 
@@ -45,7 +50,6 @@ class DiffTestIO extends XSBundle {
   val medeleg = Output(UInt(64.W))
 
   val scFailed = Output(Bool())
-  // val lrscAddr = Output(UInt(64.W))
 }
 
 class LogCtrlIO extends Bundle {
@@ -108,12 +112,17 @@ class XSSimTop()(implicit p: config.Parameters) extends LazyModule {
     BoringUtils.addSink(difftest.wdst, "difftestWdst")
     BoringUtils.addSink(difftest.wpc, "difftestWpc")
     BoringUtils.addSink(difftest.intrNO, "difftestIntrNO")
+    BoringUtils.addSink(difftest.cause, "difftestCause")
     BoringUtils.addSink(difftest.r, "difftestRegs")
     BoringUtils.addSink(difftest.priviledgeMode, "difftestMode")
     BoringUtils.addSink(difftest.mstatus, "difftestMstatus")
     BoringUtils.addSink(difftest.sstatus, "difftestSstatus")
     BoringUtils.addSink(difftest.mepc, "difftestMepc")
     BoringUtils.addSink(difftest.sepc, "difftestSepc")
+    BoringUtils.addSink(difftest.mtval, "difftestMtval")
+    BoringUtils.addSink(difftest.stval, "difftestStval")
+    BoringUtils.addSink(difftest.mtvec, "difftestMtvec")
+    BoringUtils.addSink(difftest.stvec, "difftestStvec")
     BoringUtils.addSink(difftest.mcause, "difftestMcause")
     BoringUtils.addSink(difftest.scause, "difftestScause")
     BoringUtils.addSink(difftest.satp, "difftestSatp")