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体验新版 GitCode,发现更多精彩内容 >>
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1aa6429e
编写于
12月 19, 2020
作者:
Y
Yinan Xu
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电子邮件补丁
差异文件
brq: use redirectPtr referring to the first instruction that didn't write back
上级
77701a78
变更
1
隐藏空白更改
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并排
Showing
1 changed file
with
10 addition
and
35 deletion
+10
-35
src/main/scala/xiangshan/backend/brq/Brq.scala
src/main/scala/xiangshan/backend/brq/Brq.scala
+10
-35
未找到文件。
src/main/scala/xiangshan/backend/brq/Brq.scala
浏览文件 @
1aa6429e
...
...
@@ -82,37 +82,11 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
val
stateQueue
=
RegInit
(
VecInit
(
Seq
.
fill
(
BrqSize
)(
s_invalid
)))
val
headPtr
,
tailPtr
=
RegInit
(
BrqPtr
(
false
.
B
,
0.
U
))
val
redirectPtr
=
RegInit
(
BrqPtr
(
false
.
B
,
0.
U
))
// dequeue
val
headIdx
=
headPtr
.
value
val
skipMask
=
Cat
(
stateQueue
.
map
(
_
.
isCommit
).
reverse
)
/*
example: headIdx = 2
headIdxMaskHi = 11111100
headIdxMaskLo = 00000011
commitIdxHi = 6
commitIdxLo = 0
commitIdx = 6
*/
val
headIdxMaskLo
=
UIntToMask
(
headIdx
,
BrqSize
)
val
headIdxMaskHi
=
~
headIdxMaskLo
val
commitIdxHi
=
PriorityEncoder
((~
skipMask
).
asUInt
()
&
headIdxMaskHi
)
val
(
commitIdxLo
,
findLo
)
=
PriorityEncoderWithFlag
((~
skipMask
).
asUInt
()
&
headIdxMaskLo
)
val
skipHi
=
(
skipMask
|
headIdxMaskLo
)
===
Fill
(
BrqSize
,
1.
U
(
1.
W
))
val
useLo
=
skipHi
&&
findLo
val
commitIdx
=
Mux
(
stateQueue
(
commitIdxHi
).
isWb
,
commitIdxHi
,
Mux
(
useLo
&&
stateQueue
(
commitIdxLo
).
isWb
,
commitIdxLo
,
headIdx
)
)
val
commitIdx
=
redirectPtr
.
value
val
deqValid
=
stateQueue
(
headIdx
).
isCommit
&&
brCommitCnt
=/=
0.
U
val
commitValid
=
stateQueue
(
commitIdx
).
isWb
...
...
@@ -148,7 +122,7 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
}
assert
(!(
commitIdx
===
headIdx
&&
commitValid
&&
deqValid
),
"Error: deq and commit a same entry!"
)
headPtr
:=
headPtrNext
headPtr
:=
Mux
(
deqValid
,
headPtr
+
1.
U
,
headPtr
)
io
.
redirect
.
valid
:=
commitValid
&&
commitIsMisPred
//&&
// !io.roqRedirect.valid &&
...
...
@@ -160,8 +134,8 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
io
.
outOfOrderBrInfo
.
valid
:=
commitValid
io
.
outOfOrderBrInfo
.
bits
:=
commitEntry
.
exuOut
.
brUpdate
when
(
io
.
redirect
.
v
alid
)
{
commitEntry
.
npc
:=
io
.
redirect
.
bits
.
target
when
(
commitV
alid
)
{
redirectPtr
:=
redirectPtr
+
1.
U
}
XSInfo
(
io
.
out
.
valid
,
...
...
@@ -209,6 +183,7 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
stateQueue
.
foreach
(
_
:=
s_invalid
)
headPtr
:=
BrqPtr
(
false
.
B
,
0.
U
)
tailPtr
:=
BrqPtr
(
false
.
B
,
0.
U
)
redirectPtr
:=
BrqPtr
(
false
.
B
,
0.
U
)
brCommitCnt
:=
0.
U
}.
elsewhen
(
io
.
memRedirect
.
valid
){
// misprediction or replay
...
...
@@ -216,14 +191,14 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
// replay should flush brTag
val
ptr
=
BrqPtr
(
brQueue
(
i
).
ptrFlag
,
i
.
U
)
val
replayMatch
=
io
.
memRedirect
.
bits
.
isReplay
&&
ptr
===
io
.
memRedirect
.
bits
.
brTag
when
(
io
.
memRedirect
.
valid
&&
(
ptr
.
needBrFlush
(
io
.
memRedirect
.
bits
.
brTag
)
||
replayMatch
)
){
when
(
ptr
.
needBrFlush
(
io
.
memRedirect
.
bits
.
brTag
)
||
replayMatch
){
s
:=
s_invalid
}
})
when
(
io
.
memRedirect
.
valid
){
tailPtr
:=
io
.
memRedirect
.
bits
.
brTag
+
Mux
(
io
.
memRedirect
.
bits
.
isReplay
,
0.
U
,
1.
U
)
tailPtr
:=
io
.
memRedirect
.
bits
.
brTag
+
Mux
(
io
.
memRedirect
.
bits
.
isReplay
,
0.
U
,
1.
U
)
when
(
io
.
memRedirect
.
bits
.
isReplay
&&
(
redirectPtr
.
needBrFlush
(
io
.
memRedirect
.
bits
.
brTag
)
||
redirectPtr
===
io
.
memRedirect
.
bits
.
brTag
))
{
redirectPtr
:=
io
.
memRedirect
.
bits
.
brTag
}
}
// Debug info
...
...
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