XSCore: fix 'ready's

src/main/scala/xiangshan/XSCore.scala

@@ -350,22 +350,26 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow
 
 
-  memBlock.io.wakeUpIn.fastUops <> Seq(
+  integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B)
+  integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B)
+  floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B)
+  floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B)
+
+  val wakeUpMem = Seq(
     integerBlock.io.wakeUpIntOut,
     integerBlock.io.wakeUpFpOut,
     floatBlock.io.wakeUpIntOut,
     floatBlock.io.wakeUpFpOut
-  ).flatMap(_.fastUops)
-
-  memBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpIntOut.fast ++
-    integerBlock.io.wakeUpFpOut.fast ++
-    floatBlock.io.wakeUpIntOut.fast ++
-    floatBlock.io.wakeUpFpOut.fast
-
-  memBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpIntOut.slow ++
-    integerBlock.io.wakeUpFpOut.slow ++
-    floatBlock.io.wakeUpIntOut.slow ++
-    floatBlock.io.wakeUpFpOut.slow
+  )
+  memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops)
+  memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => {
+	val raw = WireInit(f)
+	raw
+  }))
+  memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => {
+	val raw = WireInit(s)
+	raw
+  }))
 
   integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags
   integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -132,6 +132,10 @@ class MemBlock
       .map(_._2)
   }
 
+  // TODO: make this better
+  io.wakeUpIn.fast.foreach(_.ready := true.B)
+  io.wakeUpIn.slow.foreach(_.ready := true.B)
+
   io.wakeUpFpOut.slow <> exeWbReqs.map(x => {
     val raw = WireInit(x)
     raw.valid := x.valid && x.bits.uop.ctrl.fpWen
@@ -144,6 +148,9 @@ class MemBlock
     raw
   })
 
+  // load always ready
+  exeWbReqs.foreach(_.ready := true.B)
+
   val dtlb = Module(new TLB(Width = DTLBWidth, isDtlb = true))
   val lsq = Module(new LsqWrappper)
   val sbuffer = Module(new NewSbuffer)
@@ -184,6 +191,7 @@ class MemBlock
     storeUnits(i).io.lsq          <> lsq.io.storeIn(i)
     io.toCtrlBlock.stOut(i).valid := lsq.io.stout(i).valid
     io.toCtrlBlock.stOut(i).bits  := lsq.io.stout(i).bits
+	lsq.io.stout(i).ready := true.B
   }
 
   // Lsq