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19d7de6c
编写于
8月 02, 2020
作者:
L
Lingrui98
浏览文件
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浏览文件
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差异文件
Merge remote-tracking branch 'origin/dev-ubtb' into dev-frontend
上级
8faf95d1
e0a8afc7
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
75 addition
and
9 deletion
+75
-9
src/main/scala/utils/LogUtils.scala
src/main/scala/utils/LogUtils.scala
+1
-1
src/main/scala/xiangshan/frontend/uBTB.scala
src/main/scala/xiangshan/frontend/uBTB.scala
+9
-8
src/test/scala/IFUtest/uBTBTest.scala
src/test/scala/IFUtest/uBTBTest.scala
+65
-0
未找到文件。
src/main/scala/utils/LogUtils.scala
浏览文件 @
19d7de6c
...
...
@@ -26,7 +26,7 @@ object XSLog {
val
logEnable
=
WireInit
(
false
.
B
)
ExcitingUtils
.
addSink
(
logEnable
,
"DISPLAY_LOG_ENABLE"
)
if
(
generateLog
){
when
(
cond
&&
logEnable
)
{
when
(
cond
){
//
&& logEnable) {
printf
((
if
(
prefix
)
commonInfo
else
p
""
)
+
pable
)
if
(
debugLevel
>=
XSLogLevel
.
ERROR
)
{
assert
(
false
.
B
)
...
...
src/main/scala/xiangshan/frontend/uBTB.scala
浏览文件 @
19d7de6c
...
...
@@ -10,7 +10,7 @@ import scala.math.min
trait
MicroBTBPatameter
{
val
nWays
=
16
val
offsetSize
=
13
val
offsetSize
=
20
}
class
MicroBTB
extends
BasePredictor
...
...
@@ -170,19 +170,20 @@ class MicroBTB extends BasePredictor
val
update_taget_offset
=
io
.
update
.
bits
.
target
.
asSInt
-
update_br_pc
.
asSInt
val
update_is_BR_or_JAL
=
(
io
.
update
.
bits
.
pd
.
brType
===
BrType
.
branch
)
||
(
io
.
update
.
bits
.
pd
.
brType
===
BrType
.
jal
)
val
uBTB
_write_valid
=
io
.
update
.
valid
&&
io
.
update
.
bits
.
isMisPred
&&
update_is_BR_or_JAL
val
uBTB_M
eta_write_valid
=
io
.
update
.
valid
&&
update_is_BR_or_JAL
val
entry
_write_valid
=
io
.
update
.
valid
&&
io
.
update
.
bits
.
isMisPred
&&
update_is_BR_or_JAL
val
m
eta_write_valid
=
io
.
update
.
valid
&&
update_is_BR_or_JAL
//write btb target when miss prediction
when
(
uBTB
_write_valid
)
when
(
entry
_write_valid
)
{
uBTB
(
update_bank
)(
update_write_way
).
offset
:=
update_taget_offset
}
//write the uBTBMeta
when
(
uBTB_M
eta_write_valid
)
when
(
m
eta_write_valid
)
{
//commit update
uBTBMeta
(
update_bank
)(
update_write_way
).
is_Br
:=
io
.
update
.
bits
.
pd
.
brType
===
BrType
.
branch
uBTBMeta
(
update_bank
)(
update_write_way
).
is_RVC
:=
io
.
update
.
bits
.
pd
.
isRVC
(
0
until
PredictWidth
).
foreach
{
b
=>
uBTBMeta
(
b
)(
update_write_way
).
valid
:=
false
.
B
}
uBTBMeta
(
update_bank
)(
update_write_way
).
valid
:=
true
.
B
uBTBMeta
(
update_bank
)(
update_write_way
).
tag
:=
update_tag
uBTBMeta
(
update_bank
)(
update_write_way
).
pred
:=
...
...
@@ -191,18 +192,18 @@ class MicroBTB extends BasePredictor
satUpdate
(
uBTBMeta
(
update_bank
)(
update_write_way
).
pred
,
2
,
update_taken
)
)
}
XSDebug
(
uBTB_M
eta_write_valid
,
"uBTB update: update fetch pc:0x%x | real pc:0x%x | update hits%b | update_write_way:%d\n"
,
update_fetch_pc
,
update_br_pc
,
update_hits
,
update_write_way
)
XSDebug
(
m
eta_write_valid
,
"uBTB update: update fetch pc:0x%x | real pc:0x%x | update hits%b | update_write_way:%d\n"
,
update_fetch_pc
,
update_br_pc
,
update_hits
,
update_write_way
)
//bypass:read-after-write
for
(
b
<-
0
until
PredictWidth
)
{
when
(
update_bank
===
b
.
U
&&
read_hit_vec
(
b
)
&&
uBTB_M
eta_write_valid
&&
read_valid
when
(
update_bank
===
b
.
U
&&
m
eta_write_valid
&&
read_valid
&&
Mux
(
b
.
U
<
update_base_bank
,
update_tag
===
read_req_tag
+
1.
U
,
update_tag
===
read_req_tag
))
//read and write is the same fetch-packet
{
io
.
out
.
targets
(
b
)
:=
io
.
update
.
bits
.
target
io
.
out
.
takens
(
b
)
:=
io
.
update
.
bits
.
taken
io
.
out
.
is_RVC
(
b
)
:=
io
.
update
.
bits
.
pd
.
isRVC
io
.
out
.
notTakens
(
b
)
:=
(
io
.
update
.
bits
.
pd
.
brType
===
BrType
.
branch
)
&&
(!
io
.
out
.
takens
(
b
))
XSDebug
(
"uBTB bypass hit!\n"
)
XSDebug
(
"uBTB bypass hit! : hitpc:0x%x | hitbanck:%d | out_target:0x%x\n"
,
io
.
pc
.
bits
+
(
b
.
U
<<
1.
U
),
b
.
U
,
io
.
out
.
targets
(
b
)
)
}
}
}
\ No newline at end of file
src/test/scala/IFUtest/uBTBTest.scala
0 → 100644
浏览文件 @
19d7de6c
package
xiangshan.frontend
import
org.scalatest._
import
chiseltest._
import
chisel3._
import
chisel3.experimental.BundleLiterals._
import
chisel3.util.experimental.BoringUtils
import
chisel3.util._
import
chiseltest.experimental.TestOptionBuilder._
import
chiseltest.internal.VerilatorBackendAnnotation
import
utils.XSLog
import
xiangshan._
import
xiangshan.testutils._
import
xiangshan.testutils.TestCaseGenerator._
class
uBTBTest
extends
FlatSpec
with
ChiselScalatestTester
with
Matchers
with
ParallelTestExecution
with
HasPartialDecoupledDriver
{
it
should
"test uBTBTest"
in
{
XSLog
.
generateLog
=
true
test
(
new
MicroBTB
)
{
c
=>
def
genUpdateReq
(
pc
:
Long
,
target
:
Long
,
taken
:
Boolean
,
fetchIdx
:
Int
,
isMiss
:
Boolean
,
write_way
:
Int
,
hit
:
Boolean
)
=
{
c
.
io
.
update
.
valid
.
poke
(
true
.
B
)
c
.
io
.
update
.
bits
.
pc
.
poke
(
pc
.
U
)
c
.
io
.
update
.
bits
.
target
.
poke
(
target
.
U
)
c
.
io
.
update
.
bits
.
taken
.
poke
(
taken
.
B
)
c
.
io
.
update
.
bits
.
fetchIdx
.
poke
(
fetchIdx
.
U
)
c
.
io
.
update
.
bits
.
isMisPred
.
poke
(
isMiss
.
B
)
c
.
io
.
update
.
bits
.
brInfo
.
ubtbWriteWay
.
poke
(
write_way
.
U
)
c
.
io
.
update
.
bits
.
brInfo
.
ubtbHits
.
poke
(
hit
.
B
)
c
.
io
.
update
.
bits
.
pd
.
brType
.
poke
(
BrType
.
branch
)
}
def
genReadReq
(
fetchpc
:
Long
){
c
.
io
.
pc
.
valid
.
poke
(
true
.
B
)
c
.
io
.
pc
.
bits
.
poke
(
fetchpc
.
U
)
c
.
io
.
inMask
.
poke
(
"b1111111111111111"
.
U
)
c
.
clock
.
step
(
1
)
c
.
io
.
pc
.
valid
.
poke
(
false
.
B
)
}
def
UpdateOnly
(
pc
:
Long
,
target
:
Long
,
taken
:
Boolean
,
fetchIdx
:
Int
,
isMiss
:
Boolean
,
write_way
:
Int
,
hit
:
Boolean
){
genUpdateReq
(
pc
,
target
,
taken
,
fetchIdx
,
isMiss
,
write_way
,
hit
)
c
.
clock
.
step
(
1
)
c
.
io
.
update
.
valid
.
poke
(
false
.
B
)
}
def
Bypass
(
pc
:
Long
,
target
:
Long
,
taken
:
Boolean
,
fetchIdx
:
Int
,
isMiss
:
Boolean
,
write_way
:
Int
,
hit
:
Boolean
){
genUpdateReq
(
pc
,
target
,
taken
,
fetchIdx
,
isMiss
,
write_way
,
hit
)
genReadReq
(
fetchpc
=
pc
+
2
)
c
.
clock
.
step
(
1
)
c
.
io
.
update
.
valid
.
poke
(
false
.
B
)
c
.
io
.
pc
.
valid
.
poke
(
false
.
B
)
}
genReadReq
(
fetchpc
=
0x60002010
)
UpdateOnly
(
pc
=
0x60002010
,
target
=
0x60001000
,
taken
=
true
,
fetchIdx
=
6
,
isMiss
=
true
,
write_way
=
0
,
hit
=
false
)
genReadReq
(
fetchpc
=
0x60002010
)
Bypass
(
pc
=
0x60002080
,
target
=
0x600020b0
,
taken
=
true
,
fetchIdx
=
5
,
isMiss
=
true
,
write_way
=
5
,
hit
=
false
)
}
}
}
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