Merge branch 'dev-ifu-predecode' into dev-frontend-ifu

debug/Makefile

@@ -20,7 +20,8 @@ cpu:
 # ------------------------------------------------------------------
 
 cputest:
-	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) $(EMU_ARGS) run 2 > cpu.log
+	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) $(EMU_ARGS) run 
+	#2 > cpu.log
 	cat cpu.log | grep different
 	cat cpu.log | grep IPC
 
@@ -37,7 +38,8 @@ amtest:
 	cat test.log | grep ISU > isu.log
 
 microbench:
-	$(MAKE) -C $(AM_HOME)/apps/microbench $(ARCH) $(EMU_ARGS) mainargs=test run 2 > microbench.log
+	$(MAKE) -C $(AM_HOME)/apps/microbench $(ARCH) $(EMU_ARGS) mainargs=test run 
+	#2 > microbench.log
 	cat microbench.log | grep IPC
 
 microbench_train:
@@ -45,7 +47,8 @@ microbench_train:
 	cat microbench.log | grep IPC
 
 coremark:
-	$(MAKE) -C $(AM_HOME)/apps/coremark $(ARCH) $(EMU_ARGS) mainargs=test run 2 > coremark.log
+	$(MAKE) -C $(AM_HOME)/apps/coremark $(ARCH) $(EMU_ARGS) mainargs=test run 
+	#2 > coremark.log
 	cat coremark.log | grep IPC
 
 dhrystone:

src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.decode.isa.predecode
 import chisel3.util._
 import xiangshan.frontend.BrType
 
-object PreDecode {
+object PreDecodeInst {
   def C_JAL     = BitPat("b????????????????_?01_?_??_???_??_???_01")  //c.jal & c.j  //C_ADDIW?
   def C_JALR    = BitPat("b????????????????_100_?_??_???_00_000_10")  //c.jalr & c.jr
   def C_BRANCH  = BitPat("b????????????????_11?_?_??_???_??_???_01")

src/main/scala/xiangshan/frontend/FakeICache.scala

@@ -21,8 +21,9 @@ class FakeIcacheReq extends XSBundle {
 }
 
 class FakeIcacheResp extends XSBundle {
-  // val icacheOut = Vec(FetchWidth, UInt(32.W))
-  val icacheOut = UInt((FetchWidth * 32).W)
+  val pc = UInt(VAddrBits.W)
+  // val data = Vec(FetchWidth, UInt(32.W))
+  val data = UInt((FetchWidth * 32).W)
   val mask = UInt(PredictWidth.W)
 }
 
@@ -158,6 +159,7 @@ class FakeCache extends XSModule with HasICacheConst {
   // tempPredecode.io.in := s3_ram_out
 
   io.out.valid := s3_valid
-  io.out.bits.icacheOut := s3_ram_out.asUInt
+  io.out.bits.pc := s3_pc
+  io.out.bits.data := s3_ram_out.asUInt
   io.out.bits.mask := mask(s3_pc)
 }
\ No newline at end of file

src/main/scala/xiangshan/frontend/PreDecode.scala

+package xiangshan.frontend
+
+import chisel3._
+import chisel3.util._
+import utils.XSDebug
+import xiangshan._
+import xiangshan.backend.decode.isa.predecode.PreDecodeInst
+
+trait HasPdconst{ this: XSModule =>
+  // val groupAlign = log2Up(FetchWidth * 4)
+  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
+  // def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
+  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
+  def brInfo(instr: UInt) = {
+    val rd = instr(11,7)
+    val rs = instr(19,15)
+    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
+    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
+    val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
+    List(brType, isCall, isRet)
+  }
+}
+
+object BrType {
+  def notBr   = "b00".U
+  def branch  = "b01".U
+  def jal     = "b10".U
+  def jalr    = "b11".U
+  def apply() = UInt(2.W)
+}
+
+object ExcType {  //TODO:add exctype
+  def notExc = "b000".U
+  def apply() = UInt(3.W)
+}
+
+class PreDecodeInfo extends XSBundle {  // 8 bit
+  val isRVC   = Bool()
+  val brType  = UInt(2.W)
+  val isCall  = Bool()
+  val isRet   = Bool()
+  val excType = UInt(3.W)
+}
+
+// class PDPacket extends PreDecodeInfo{
+//   val pc = UInt(VAddrBits.W)
+//   val inst = UInt(32.W)
+//   val mask = Bool()
+// }
+
+class PreDecodeResp extends XSBundle {
+  val instrs = Vec(PredictWidth, UInt(32.W))
+  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
+  val mask = UInt(PredictWidth.W)
+  val pd = Vec(PredictWidth, (new PreDecodeInfo))
+}
+
+// class ICacheResp extends XSBundle {
+//   val fetchPc = UInt(VAddrBits.W)
+//   val data = UInt((FetchWidth * 32).W)
+//   val mask = UInt((FetchWidth * 2).W)
+// }
+
+class FakeIcacheResp extends XSBundle {
+  val pc = UInt(VAddrBits.W)
+  // val data = Vec(FetchWidth, UInt(32.W))
+  val data = UInt((FetchWidth * 32).W)
+  val mask = UInt(PredictWidth.W)
+}
+
+class PreDecode extends XSModule with HasPdconst{
+  val io = IO(new Bundle() {
+    val in = Input(new FakeIcacheResp)
+    // val prevHalf = Input(UInt(16.W))
+    // val prevValid = Input(false.B)
+    val prev = ValidIO(UInt(16.W))
+
+    // val out = Output(Vec(PredictWidth, new PDPacket))
+    val out = Output(new PreDecodeResp)
+  })
+
+  // val gpc = groupPC(io.in.pc)
+  val data = io.in.data
+  val mask = io.in.mask
+
+  val insts = Wire(Vec(PredictWidth, UInt(32.W)))
+  val instsMask = Wire(Vec(PredictWidth, Bool()))
+  val instsRVC = Wire(Vec(PredictWidth,Bool()))
+  val instsPC = Wire(Vec(PredictWidth, UInt(VAddrBits.W)))
+  val nextHalf = Wire(UInt(16.W))
+
+  for (i <- 0 until PredictWidth) {
+    val inst = Wire(UInt(32.W))
+    val valid = Wire(Bool())
+    val pc = io.in.pc + (i << 1).U - Mux(io.prev.valid && (i.U === 0.U), 2.U, 0.U)
+
+    if (i==0) {
+      inst := Mux(io.prev.valid, Cat(data(15,0), io.prev.bits), data(31,0))
+      valid := true.B
+    } else if (i==1) {
+      inst := data(47,16)
+      valid := io.prev.valid || !(instsMask(0) && !isRVC(insts(0)))
+    } else if (i==PredictWidth-1) {
+      inst := Cat(0.U(16.W), data(i*16+15, i*16))
+      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
+    } else {
+      inst := data(i*16+31, i*16)
+      valid := !(instsMask(i-1) && !isRVC(insts(i-1)))
+    }
+
+    insts(i) := inst
+    instsRVC(i) := isRVC(inst)
+    instsMask(i) := mask(i) && valid 
+    instsPC(i) := pc
+
+    val brType::isCall::isRet::Nil = brInfo(inst)
+    io.out.pd(i).isRVC := instsRVC(i)
+    io.out.pd(i).brType := brType
+    io.out.pd(i).isCall := isCall
+    io.out.pd(i).isRet := isRet
+    io.out.pd(i).excType := ExcType.notExc
+    io.out.instrs(i) := insts(i)
+    io.out.pc(i) := instsPC(i)
+    
+  }
+  io.out.mask := instsMask.asUInt
+
+  for (i <- 0 until PredictWidth) {
+    XSDebug(true.B,
+      p"instr ${Hexdecimal(io.out.instrs(i))}, " +
+      p"mask ${Binary(instsMask(i))}, " +
+      p"pc ${Hexdecimal(io.out.pc(i))}, " +
+      p"isRVC ${Binary(io.out.pd(i).isRVC)}, " +
+      p"brType ${Binary(io.out.pd(i).brType)}, " +
+      p"isRet ${Binary(io.out.pd(i).isRet)}, " +
+      p"isCall ${Binary(io.out.pd(i).isCall)}\n"
+    )
+  }
+}

src/test/scala/xiangshan/frontend/PDtest.scala

+package xiangshan.frontend
+
+import chisel3._
+import chiseltest._
+import org.scalatest._
+
+class PDtest extends FlatSpec with ChiselScalatestTester with Matchers{
+  val cacheLine2 = ("b" +
+    "100_1_00001_00000_10" +  //rvc jalr
+    "100_0_00001_00000_10" +  //rvc jr
+    "101_00000000000_01" +  //rvc j
+    "001_00000000000_01" +  //rvc jal
+    "111_000_001_00000_01" +  //RVC bnez
+
+    "0000000_00000_00001_000_10000_1100111" +  //RET
+    "0000000_00000_00101_000_10000_1100111" +  //RET
+    "0000000_00000_00000_000_00101_1100111" +  //JALR_CALL
+    "0000000_00000_00000_000_00001_1100111" +  //JALR_CALL
+    "0000000_00000_00000_000_00101_1101111" +  //JAL_CALL
+    "0000000_00000_0000").U   //JAL_CALL_height-half
+
+  val cacheLine1 = ("b" +
+    "0_000_00001_1101111" +  //JAL_CALL_low-half
+    "110_000_001_00000_01" +  //RVC beqz
+    "0000000_00010_00011_000_10000_1100111" +  //JARL
+    "0000000_00000_00000_000_10000_1101111" +  //JAR
+    "0000000_00010_00001_101_00000_1100011" +  //Branch bge
+    "0000000_00010_00001_100_00000_1100011" +  //Branch blt
+    "0000000_00010_00001_001_00000_1100011" +  //Branch bne
+    "0000000_00010_00001_000_00000_1100011" +  //Branch beq
+    "0000000_00010_00001_000_00001_0000011").U //Notbr
+
+  it should "test PDecode" in {
+    test(new PreDecode) { c =>
+      println(s"\n--------------------cycle 1------------------\n")
+      c.io.in.fetchPc.poke(0.U)
+      c.io.in.mask.poke("b1111_1111_1111_0000".U)
+      c.io.in.data.poke(cacheLine1)
+      c.clock.step()
+      println(s"\n--------------------cycle 2------------------\n")
+      c.io.in.fetchPc.poke((1<<5).U)
+      c.io.in.mask.poke("b1111_1111_1111_1111".U)
+      c.io.in.data.poke(cacheLine2)
+      c.clock.step()
+      println(s"\n--------------------cycle 3------------------\n")
+      c.io.in.fetchPc.poke((2<<5).U)
+      c.io.in.mask.poke("b1111_1111_1111_1111".U)
+      c.io.in.data.poke(cacheLine1)
+      c.clock.step()
+      println(s"\n--------------------cycle 4------------------\n")
+      c.io.in.fetchPc.poke((3<<5).U)
+      c.io.in.mask.poke("b1111_1111_1111_1111".U)
+      c.io.in.data.poke(cacheLine2)
+      c.clock.step()
+    }
+  }
+}