core: pass mdu cputests

src/main/scala/core/Decode.scala

@@ -76,7 +76,11 @@ object Decode {
   val LsuSw   = "b1010".U
 
   /* MDU operation type */
-  private val FuOpTypeMduNum  = 0
+  private val FuOpTypeMduNum  = 8
+  val MduMul  = "b000".U
+  val MduMulh = "b001".U
+  val MduDiv  = "b100".U
+  val MduRem  = "b110".U
 
   private val FuOpTypeMaxNum = List(FuOpTypeAluNum, FuOpTypeBruNum,
     FuOpTypeLsuNum, FuOpTypeMduNum).reduce(math.max)
@@ -89,6 +93,7 @@ object Decode {
   val SLLI    = BitPat("b0000000?????_?????_001_?????_0010011")
   val SRLI    = BitPat("b0000000?????_?????_101_?????_0010011")
   val ANDI    = BitPat("b????????????_?????_111_?????_0010011")
+  val SRAI    = BitPat("b0100000?????_?????_101_?????_0010011")
 
   val ADD     = BitPat("b0000000_?????_?????_000_?????_0110011")
   val SLT     = BitPat("b0000000_?????_?????_010_?????_0110011")
@@ -113,6 +118,11 @@ object Decode {
   val LW      = BitPat("b????????????_?????_010_?????_0000011")
   val SW      = BitPat("b???????_?????_?????_010_?????_0100011")
 
+  val MUL     = BitPat("b0000001_?????_?????_000_?????_0110011")
+  val MULH    = BitPat("b0000001_?????_?????_001_?????_0110011")
+  val DIV     = BitPat("b0000001_?????_?????_100_?????_0110011")
+  val REM     = BitPat("b0000001_?????_?????_110_?????_0110011")
+
   val TRAP    = BitPat("b????????????_?????_000_?????_1101011")
 
 
@@ -126,6 +136,7 @@ object Decode {
     SLLI           -> List(InstrI, FuAlu, AluSll),
     SRLI           -> List(InstrI, FuAlu, AluSrl),
     ANDI           -> List(InstrI, FuAlu, AluAnd),
+    SRAI           -> List(InstrI, FuAlu, AluSra),
 
     ADD            -> List(InstrR, FuAlu, AluAdd),
     SLT            -> List(InstrR, FuAlu, AluSlt),
@@ -150,6 +161,11 @@ object Decode {
     LW             -> List(InstrI, FuLsu, LsuLw),
     SW             -> List(InstrS, FuLsu, LsuSw),
 
+    MUL            -> List(InstrR, FuMdu, MduMul),
+    MULH           -> List(InstrR, FuMdu, MduMulh),
+    DIV            -> List(InstrR, FuMdu, MduDiv),
+    REM            -> List(InstrR, FuMdu, MduRem),
+
     TRAP           -> List(InstrI, FuAlu, AluAdd)
   )
 }

src/main/scala/core/EXU.scala

@@ -37,7 +37,6 @@ class ALU {
 }
 
 class BRU {
-  private val useMuxTree = true
   def access(pc: UInt, offset: UInt, src1: UInt, src2: UInt, func: UInt): (UInt, Bool) = {
     val funcList = List(
       BruBeq  -> (src1 === src2),
@@ -55,7 +54,6 @@ class BRU {
 }
 
 class LSU {
-  private val useMuxTree = true
   def access(src1: UInt, src2: UInt, func: UInt): (UInt, Bool) = {
     val funcList = List(
       LsuSw   -> (src1  +  src2)
@@ -67,6 +65,20 @@ class LSU {
   }
 }
 
+class MDU {
+  def access(src1: UInt, src2: UInt, func: UInt): UInt = {
+    val mulRes = (src1.asSInt * src2.asSInt).asUInt
+    val funcList = List(
+      MduMul  -> mulRes(31, 0),
+      MduMulh -> mulRes(63, 32),
+      MduDiv  -> (src1.asSInt  /  src2.asSInt).asUInt,
+      MduRem  -> (src1.asSInt  %  src2.asSInt).asUInt
+    )
+
+    LookupTree(func, 0.U, funcList)
+  }
+}
+
 class EXU extends Module {
   val io = IO(new Bundle {
     val in = Flipped(new PcCtrlDataIO)
@@ -89,10 +101,15 @@ class EXU extends Module {
   io.dmem.out.bits.wen := (fuType === FuLsu) && dmemWen
   io.dmem.out.bits.wdata := io.in.data.dest
 
+  val mduOut = (new MDU).access(src1 = src1, src2 = src2, func = fuOpType)
+
   io.out.data := DontCare
-  io.out.data.dest := Mux(fuType === FuAlu, aluOut,
-                        Mux(fuType === FuBru, io.in.pc + 4.U,
-                          Mux(fuType === FuLsu, io.dmem.in.rdata, 0.U)))
+  io.out.data.dest := LookupTree(fuType, 0.U, List(
+    FuAlu -> aluOut,
+    FuBru -> (io.in.pc + 4.U),
+    FuLsu -> io.dmem.in.rdata,
+    FuMdu -> mduOut
+  ))
 
   io.out.ctrl := DontCare
   (io.out.ctrl, io.in.ctrl) match { case (o, i) =>