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1365c050
编写于
12月 30, 2020
作者:
Y
Yinan Xu
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差异文件
Merge remote-tracking branch 'origin/master' into debian-gogogo
上级
951c6ac9
47f2011c
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
47 addition
and
26 deletion
+47
-26
src/main/scala/xiangshan/frontend/BPU.scala
src/main/scala/xiangshan/frontend/BPU.scala
+4
-2
src/main/scala/xiangshan/frontend/Bim.scala
src/main/scala/xiangshan/frontend/Bim.scala
+2
-2
src/main/scala/xiangshan/frontend/IFU.scala
src/main/scala/xiangshan/frontend/IFU.scala
+18
-9
src/main/scala/xiangshan/frontend/Ibuffer.scala
src/main/scala/xiangshan/frontend/Ibuffer.scala
+23
-13
未找到文件。
src/main/scala/xiangshan/frontend/BPU.scala
浏览文件 @
1365c050
...
...
@@ -267,8 +267,8 @@ class BPUStage3 extends BPUStage {
val
pdLastHalf
=
s3IO
.
predecode
.
lastHalf
val
pds
=
s3IO
.
predecode
.
pd
val
btbResp
=
inLatch
.
resp
.
btb
val
btbHits
=
btbResp
.
hits
.
asUInt
val
btbResp
=
WireInit
(
inLatch
.
resp
.
btb
)
val
btbHits
=
WireInit
(
btbResp
.
hits
.
asUInt
)
val
bimTakens
=
VecInit
(
inLatch
.
resp
.
bim
.
ctrs
.
map
(
_
(
1
)))
val
brs
=
pdMask
&
Reverse
(
Cat
(
pds
.
map
(
_
.
isBr
)))
...
...
@@ -287,6 +287,8 @@ class BPUStage3 extends BPUStage {
val
prevHalfTakenMask
=
prevHalfTaken
.
asUInt
val
brTakens
=
((
brs
&
brPred
|
prevHalfTakenMask
)
&
~
loopRes
)
// VecInit((0 until PredictWidth).map(i => brs(i) && (brPred(i) || (if (i == 0) prevHalfTaken else false.B)) && !loopRes(i)))
// we should provide btb resp as well
btbHits
:=
btbResp
.
hits
.
asUInt
|
prevHalfTakenMask
// predict taken only if btb has a target, jal targets will be provided by IFU
takens
:=
VecInit
((
0
until
PredictWidth
).
map
(
i
=>
(
brTakens
(
i
)
||
jalrs
(
i
))
&&
btbHits
(
i
)
||
jals
(
i
)))
...
...
src/main/scala/xiangshan/frontend/Bim.scala
浏览文件 @
1365c050
...
...
@@ -108,9 +108,9 @@ class BIM extends BasePredictor with BimParams {
when
(
needToUpdate
)
{
when
(
wrbypass_hit
)
{
wrbypass_ctrs
(
wrbypass_hit_idx
)(
updateBank
)
:=
newCtr
wrbypass_ctr_valids
(
wrbypass_
enq
_idx
)(
updateBank
)
:=
true
.
B
wrbypass_ctr_valids
(
wrbypass_
hit
_idx
)(
updateBank
)
:=
true
.
B
}
.
otherwise
{
wrbypass_ctrs
(
wrbypass_
hit
_idx
)(
updateBank
)
:=
newCtr
wrbypass_ctrs
(
wrbypass_
enq
_idx
)(
updateBank
)
:=
newCtr
(
0
until
BimBanks
).
foreach
(
b
=>
wrbypass_ctr_valids
(
wrbypass_enq_idx
)(
b
)
:=
false
.
B
)
// reset valid bits
wrbypass_ctr_valids
(
wrbypass_enq_idx
)(
updateBank
)
:=
true
.
B
wrbypass_rows
(
wrbypass_enq_idx
)
:=
updateRow
...
...
src/main/scala/xiangshan/frontend/IFU.scala
浏览文件 @
1365c050
...
...
@@ -92,7 +92,8 @@ class PrevHalfInstr extends XSBundle {
val
target
=
UInt
(
VAddrBits
.
W
)
val
instr
=
UInt
(
16.
W
)
val
ipf
=
Bool
()
val
newPtr
=
UInt
(
log2Up
(
ExtHistoryLength
).
W
)
val
meta
=
new
BpuMeta
// val newPtr = UInt(log2Up(ExtHistoryLength).W)
}
@chiselName
...
...
@@ -200,9 +201,11 @@ class IFU extends XSModule with HasIFUConst
// set to invalid once consumed or redirect from backend
val
if3_prevHalfConsumed
=
if3_prevHalfInstrMet
&&
if3_fire
val
if3_prevHalfFlush
=
if4_flush
when
(
hasPrevHalfInstrReq
&&
!
if3_prevHalfFlush
)
{
when
(
if3_prevHalfFlush
)
{
if3_prevHalfInstr
.
valid
:=
false
.
B
}.
elsewhen
(
hasPrevHalfInstrReq
)
{
if3_prevHalfInstr
.
valid
:=
true
.
B
}.
elsewhen
(
if3_prevHalfConsumed
||
if3_prevHalfFlush
)
{
}.
elsewhen
(
if3_prevHalfConsumed
)
{
if3_prevHalfInstr
.
valid
:=
false
.
B
}
when
(
hasPrevHalfInstrReq
)
{
...
...
@@ -280,9 +283,9 @@ class IFU extends XSModule with HasIFUConst
val
if4_bp
=
Wire
(
new
BranchPrediction
)
if4_bp
:=
bpu
.
io
.
out
(
2
)
if4_bp
.
takens
:=
bpu
.
io
.
out
(
2
).
takens
&
if4_mask
if4_bp
.
brMask
:=
bpu
.
io
.
out
(
2
).
brMask
&
if4_mask
if4_bp
.
jalMask
:=
bpu
.
io
.
out
(
2
).
jalMask
&
if4_mask
//
if4_bp.takens := bpu.io.out(2).takens & if4_mask
//
if4_bp.brMask := bpu.io.out(2).brMask & if4_mask
//
if4_bp.jalMask := bpu.io.out(2).jalMask & if4_mask
if4_predicted_gh
:=
if4_gh
.
update
(
if4_bp
.
hasNotTakenBrs
,
if4_bp
.
takenOnBr
)
...
...
@@ -311,9 +314,11 @@ class IFU extends XSModule with HasIFUConst
val
if4_prevHalfFlush
=
if4_flush
val
if4_takenPrevHalf
=
WireInit
(
if4_prevHalfInstrMet
&&
if4_prevHalfInstr
.
bits
.
taken
)
when
(
if3_prevHalfConsumed
)
{
when
(
if4_prevHalfFlush
)
{
if4_prevHalfInstr
.
valid
:=
false
.
B
}.
elsewhen
(
if3_prevHalfConsumed
)
{
if4_prevHalfInstr
.
valid
:=
if3_prevHalfInstr
.
valid
}.
elsewhen
(
if4_prevHalfConsumed
||
if4_prevHalfFlush
)
{
}.
elsewhen
(
if4_prevHalfConsumed
)
{
if4_prevHalfInstr
.
valid
:=
false
.
B
}
...
...
@@ -327,7 +332,6 @@ class IFU extends XSModule with HasIFUConst
// this is result of the last half RVI
prevHalfInstrReq
.
bits
.
taken
:=
if4_bp
.
lastHalfRVITaken
prevHalfInstrReq
.
bits
.
ghInfo
:=
if4_gh
prevHalfInstrReq
.
bits
.
newPtr
:=
DontCare
prevHalfInstrReq
.
bits
.
fetchpc
:=
if4_pc
prevHalfInstrReq
.
bits
.
idx
:=
idx
prevHalfInstrReq
.
bits
.
pc
:=
if4_pd
.
pc
(
idx
)
...
...
@@ -335,6 +339,7 @@ class IFU extends XSModule with HasIFUConst
prevHalfInstrReq
.
bits
.
target
:=
if4_bp
.
lastHalfRVITarget
prevHalfInstrReq
.
bits
.
instr
:=
if4_pd
.
instrs
(
idx
)(
15
,
0
)
prevHalfInstrReq
.
bits
.
ipf
:=
if4_ipf
prevHalfInstrReq
.
bits
.
meta
:=
bpu
.
io
.
bpuMeta
(
idx
)
def
if4_nextValidPCNotEquals
(
pc
:
UInt
)
=
if3_valid
&&
if3_pc
=/=
pc
||
!
if3_valid
&&
(
if2_valid
&&
if2_pc
=/=
pc
)
||
...
...
@@ -462,6 +467,10 @@ class IFU extends XSModule with HasIFUConst
fetchPacketWire
.
pnpc
(
if4_bp
.
jmpIdx
)
:=
if4_bp
.
target
}
fetchPacketWire
.
bpuMeta
:=
bpu
.
io
.
bpuMeta
// save it for update
when
(
if4_pendingPrevHalfInstr
)
{
fetchPacketWire
.
bpuMeta
(
0
)
:=
if4_prevHalfInstr
.
bits
.
meta
}
(
0
until
PredictWidth
).
foreach
(
i
=>
{
val
meta
=
fetchPacketWire
.
bpuMeta
(
i
)
meta
.
hist
:=
final_gh
...
...
src/main/scala/xiangshan/frontend/Ibuffer.scala
浏览文件 @
1365c050
...
...
@@ -52,24 +52,33 @@ class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
}
// Ibuffer define
val
ibuf
=
Mem
(
IBufSize
,
new
IBufEntry
)
val
ibuf
=
Reg
(
Vec
(
IBufSize
,
new
IBufEntry
)
)
val
head_ptr
=
RegInit
(
IbufPtr
(
false
.
B
,
0.
U
))
val
tail_ptr
=
RegInit
(
IbufPtr
(
false
.
B
,
0.
U
))
val
tail_vec
=
RegInit
(
VecInit
((
0
until
PredictWidth
).
map
(
_
.
U
.
asTypeOf
(
new
IbufPtr
))))
val
tail_ptr
=
tail_vec
(
0
)
val
validEntries
=
distanceBetween
(
tail_ptr
,
head_ptr
)
// valid entries
// val validEntries = distanceBetween(tail_ptr, head_ptr) // valid entries
val
validEntries
=
RegInit
(
0.
U
(
log2Up
(
IBufSize
+
1
).
W
))
// valid entries
val
allowEnq
=
RegInit
(
true
.
B
)
val
enqValid
=
IBufSize
.
U
-
PredictWidth
.
U
>=
validEntries
// val enqValid = (IBufSize.U - PredictWidth.U)
>= validEntries
val
deqValid
=
validEntries
>
0.
U
val
numEnq
=
Mux
(
io
.
in
.
fire
,
PopCount
(
io
.
in
.
bits
.
mask
),
0.
U
)
val
numDeq
=
Mux
(
deqValid
,
PopCount
(
io
.
out
.
map
(
_
.
fire
)),
0.
U
)
validEntries
:=
validEntries
+
numEnq
-
numDeq
allowEnq
:=
(
IBufSize
.
U
-
PredictWidth
.
U
)
>=
(
validEntries
+
numEnq
)
// Enque
io
.
in
.
ready
:=
enqValid
io
.
in
.
ready
:=
allowEnq
val
enq_vec
=
Wire
(
Vec
(
PredictWidth
,
UInt
(
log2Up
(
IBufSize
).
W
)))
val
offset
=
Wire
(
Vec
(
PredictWidth
,
UInt
(
log2Up
(
PredictWidth
).
W
)))
for
(
i
<-
0
until
PredictWidth
)
{
if
(
i
==
0
)
{
enq_vec
(
i
)
:=
tail_ptr
.
value
offset
(
i
)
:=
0.
U
}
else
{
enq_vec
(
i
)
:=
tail_ptr
.
value
+
PopCount
(
io
.
in
.
bits
.
pdmask
(
i
-
1
,
0
))
offset
(
i
)
:=
PopCount
(
io
.
in
.
bits
.
pdmask
(
i
-
1
,
0
))
}
}
...
...
@@ -87,11 +96,11 @@ class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
inWire
.
ipf
:=
io
.
in
.
bits
.
ipf
inWire
.
acf
:=
io
.
in
.
bits
.
acf
inWire
.
crossPageIPFFix
:=
io
.
in
.
bits
.
crossPageIPFFix
ibuf
(
enq_vec
(
i
)
)
:=
inWire
ibuf
(
tail_vec
(
offset
(
i
)).
value
)
:=
inWire
}
}
tail_
ptr
:=
tail_ptr
+
PopCount
(
io
.
in
.
bits
.
mask
)
tail_
vec
:=
VecInit
(
tail_vec
.
map
(
_
+
PopCount
(
io
.
in
.
bits
.
mask
))
)
}
// Deque
...
...
@@ -125,10 +134,11 @@ class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
// Flush
when
(
io
.
flush
)
{
validEntries
:=
0.
U
allowEnq
:=
true
.
B
head_ptr
.
value
:=
0.
U
head_ptr
.
flag
:=
false
.
B
tail_ptr
.
value
:=
0.
U
tail_ptr
.
flag
:=
false
.
B
tail_vec
:=
VecInit
((
0
until
PredictWidth
).
map
(
_
.
U
.
asTypeOf
(
new
IbufPtr
)))
}
// Debug info
...
...
@@ -164,7 +174,7 @@ class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
// )
// }
XSDebug
(
p
"last_head_ptr=$head_ptr last_tail_ptr=$tail_ptr\n"
)
XSDebug
(
p
"
validEntries=$validEntries,
last_head_ptr=$head_ptr last_tail_ptr=$tail_ptr\n"
)
for
(
i
<-
0
until
IBufSize
/
8
)
{
XSDebug
(
"%x | %x | %x | %x | %x | %x | %x | %x\n"
,
ibuf
(
i
*
8
+
0
).
inst
,
...
...
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