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11f61932
编写于
1月 21, 2021
作者:
B
BigWhiteDog
浏览文件
操作
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电子邮件补丁
差异文件
add deadlock detection in Trans
上级
9b6529a7
变更
7
隐藏空白更改
内联
并排
Showing
7 changed file
with
107 addition
and
43 deletion
+107
-43
src/test/scala/cache/L1DTest/CoreAgent.scala
src/test/scala/cache/L1DTest/CoreAgent.scala
+12
-7
src/test/scala/cache/L1DTest/CoreTransatcion.scala
src/test/scala/cache/L1DTest/CoreTransatcion.scala
+16
-5
src/test/scala/cache/L1DTest/L1DTest.scala
src/test/scala/cache/L1DTest/L1DTest.scala
+6
-9
src/test/scala/cache/TLCTest/TLCAgent.scala
src/test/scala/cache/TLCTest/TLCAgent.scala
+29
-1
src/test/scala/cache/TLCTest/TLCTest.scala
src/test/scala/cache/TLCTest/TLCTest.scala
+0
-5
src/test/scala/cache/TLCTest/TLCTransaction.scala
src/test/scala/cache/TLCTest/TLCTransaction.scala
+39
-16
src/test/scala/cache/TLCTest/TLULAgent.scala
src/test/scala/cache/TLCTest/TLULAgent.scala
+5
-0
未找到文件。
src/test/scala/cache/L1DTest/CoreAgent.scala
浏览文件 @
11f61932
...
...
@@ -20,6 +20,12 @@ class CoreAgent(ID: Int, name: String, addrStateMap: mutable.Map[BigInt, AddrSta
val
outerStore
:
ListBuffer
[
DCacheStoreCallerTrans
]
=
ListBuffer
()
val
outerAMO
:
ListBuffer
[
DCacheAMOCallerTrans
]
=
ListBuffer
()
override
def
transStep
()
:
Unit
=
{
outerLoad
.
foreach
(
_
.
step
())
outerStore
.
foreach
(
_
.
step
())
outerAMO
.
foreach
(
_
.
step
())
}
private
val
maxStoreId
=
255
private
val
maxAMOId
=
0
...
...
@@ -34,7 +40,7 @@ class CoreAgent(ID: Int, name: String, addrStateMap: mutable.Map[BigInt, AddrSta
if
(
nextLoad
.
isDefined
)
{
//alloc & issue
s0_loadTrans
(
i
)
=
nextLoad
loadPortsReqMessage
(
i
)
=
Some
(
nextLoad
.
get
.
issueReq
())
loadPortsReqMessage
(
i
)
=
Some
(
nextLoad
.
get
.
issue
Load
Req
())
}
}
}
...
...
@@ -60,15 +66,14 @@ class CoreAgent(ID: Int, name: String, addrStateMap: mutable.Map[BigInt, AddrSta
def
fireLoadResp
(
i
:
Int
,
resp
:
LitDCacheWordResp
)
:
Unit
=
{
val
loadT
=
s2_loadTrans
(
i
).
get
val
loadAddr
=
loadT
.
req
.
get
.
addr
loadT
.
pairResp
(
resp
)
loadT
.
pair
Load
Resp
(
resp
)
if
(!
resp
.
miss
)
{
val
wc
=
wordInBlock
(
loadAddr
)
insertMaskedWordRead
(
loadAddr
,
resp
.
data
,
loadT
.
req
.
get
.
mask
)
outerLoad
-=
loadT
}
else
if
(
resp
.
replay
)
{
outerLoad
-=
loadT
//drop it
loadT
.
replay
()
//mark replay
loadT
.
replay
Load
()
//mark replay
outerLoad
.
append
(
loadT
)
//pushpack
}
else
{
...
...
@@ -117,7 +122,7 @@ class CoreAgent(ID: Int, name: String, addrStateMap: mutable.Map[BigInt, AddrSta
val
allocId
=
(
0
to
maxStoreId
).
find
(
i
=>
!
storeIdMap
.
contains
(
BigInt
(
i
)))
if
(
allocId
.
isDefined
)
{
//alloc & issue
storePortReqMessage
=
Some
(
nextStore
.
get
.
issueReq
(
BigInt
(
allocId
.
get
)))
storePortReqMessage
=
Some
(
nextStore
.
get
.
issue
Store
Req
(
BigInt
(
allocId
.
get
)))
storeIdMap
(
BigInt
(
allocId
.
get
))
=
nextStore
.
get
}
else
debugPrintln
(
"cann't alloc ID for core store"
)
...
...
@@ -138,7 +143,7 @@ class CoreAgent(ID: Int, name: String, addrStateMap: mutable.Map[BigInt, AddrSta
val
storeId
=
resp
.
id
val
storeTrans
=
storeIdMap
(
storeId
)
val
storeReq
=
storeTrans
.
req
.
get
storeTrans
.
pairResp
(
resp
)
storeTrans
.
pair
Store
Resp
(
resp
)
//free resource
storeIdMap
.
remove
(
storeId
)
//drop finished store
...
...
@@ -194,7 +199,7 @@ class CoreAgent(ID: Int, name: String, addrStateMap: mutable.Map[BigInt, AddrSta
s1_loadTrans
(
i
)
=
None
}
}
clock
+=
1
super
.
step
()
}
def
addLoad
(
addr
:
BigInt
)
:
Unit
=
{
...
...
src/test/scala/cache/L1DTest/CoreTransatcion.scala
浏览文件 @
11f61932
...
...
@@ -64,21 +64,28 @@ class DCacheLoadCallerTrans extends DCacheLoadTrans with TLCCallerTrans {
reqIssued
=
Some
(
false
)
}
def
issueReq
()
:
LitDCacheWordReq
=
{
def
issue
Load
Req
()
:
LitDCacheWordReq
=
{
reqIssued
=
Some
(
true
)
startTimer
()
req
.
get
}
def
replay
()
:
Unit
=
{
def
replay
Load
()
:
Unit
=
{
reqIssued
=
Some
(
false
)
resetTimer
()
}
def
pairResp
(
inResp
:
LitDCacheWordResp
)
:
Unit
=
{
def
pair
Load
Resp
(
inResp
:
LitDCacheWordResp
)
:
Unit
=
{
resp
=
Some
(
inResp
)
resetTimer
()
if
(
inResp
.
miss
&&
!
inResp
.
replay
)
{
//if it will be placed into lsq
startTimer
()
}
}
def
pairLsqResp
(
inResp
:
LitDCacheLineResp
)
:
Unit
=
{
lsqResp
=
Some
(
inResp
)
resetTimer
()
}
}
...
...
@@ -102,14 +109,16 @@ class DCacheStoreCallerTrans extends DCacheStoreTrans with TLCCallerTrans {
reqIssued
=
Some
(
false
)
}
def
issueReq
(
allocId
:
BigInt
)
:
LitDCacheLineReq
=
{
def
issue
Store
Req
(
allocId
:
BigInt
)
:
LitDCacheLineReq
=
{
req
.
get
.
id
=
allocId
reqIssued
=
Some
(
true
)
startTimer
()
req
.
get
}
def
pairResp
(
inResp
:
LitDCacheLineResp
)
:
Unit
=
{
def
pair
Store
Resp
(
inResp
:
LitDCacheLineResp
)
:
Unit
=
{
resp
=
Some
(
inResp
)
resetTimer
()
}
}
...
...
@@ -137,11 +146,13 @@ class DCacheAMOCallerTrans extends DCacheAMOTrans with TLCCallerTrans {
def
issueReq
(
allodId
:
BigInt
=
0
)
:
LitDCacheWordReq
=
{
req
.
get
.
id
=
allodId
reqIssued
=
Some
(
true
)
startTimer
()
req
.
get
}
def
pairResp
(
inResp
:
LitDCacheWordResp
)
:
Unit
=
{
resp
=
Some
(
inResp
)
resetTimer
()
}
}
src/test/scala/cache/L1DTest/L1DTest.scala
浏览文件 @
11f61932
...
...
@@ -137,24 +137,24 @@ class L1DCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
for
(
cl
<-
0
until
total_clock
)
{
//========= core trans ===========
//randomly add when low size
if
(
coreAgent
.
outerLoad
.
size
<=
4
)
{
if
(
true
)
{
if
(
true
)
{
if
(
coreAgent
.
outerLoad
.
size
<=
4
)
{
for
(
i
<-
0
until
8
)
{
val
addr
=
getRandomElement
(
addr_pool
,
rand
)
coreAgent
.
addLoad
(
addr
)
}
}
}
if
(
coreAgent
.
outerStore
.
size
<=
4
)
{
if
(
true
)
{
if
(
true
)
{
if
(
coreAgent
.
outerStore
.
size
<=
4
)
{
for
(
i
<-
0
until
8
)
{
val
addr
=
getRandomElement
(
addr_pool
,
rand
)
coreAgent
.
addStore
(
addr
)
}
}
}
if
(
coreAgent
.
outerAMO
.
size
<=
0
)
{
if
(
true
)
{
if
(
false
)
{
if
(
coreAgent
.
outerAMO
.
size
<=
0
)
{
for
(
i
<-
0
until
4
)
{
val
addr
=
getRandomElement
(
addr_pool
,
rand
)
coreAgent
.
addAMO
(
addr
)
...
...
@@ -310,8 +310,6 @@ class L1DCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
}
slaveAgent
.
tickA
()
//handle some ID
slaveAgent
.
freeSink
()
slaveAgent
.
step
()
//============ core peek ============
...
...
@@ -376,7 +374,6 @@ class L1DCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
}
c
.
io
.
dcacheIO
.
load
.
foreach
{
l
=>
l
.
s1_kill
.
poke
(
true
.
B
)
// l.s1_paddr.poke(0x80000000L.U)
l
.
req
.
valid
.
poke
(
false
.
B
)
l
.
resp
.
ready
.
poke
(
true
.
B
)
}
...
...
src/test/scala/cache/TLCTest/TLCAgent.scala
浏览文件 @
11f61932
...
...
@@ -163,7 +163,12 @@ class TLCAgent(ID: Int, name: String = "", addrStateMap: mutable.Map[BigInt, Add
var
clock
=
0
def
transStep
()
:
Unit
=
{
Unit
}
def
step
()
:
Unit
=
{
transStep
()
clock
+=
1
}
...
...
@@ -302,7 +307,7 @@ class TLCAgent(ID: Int, name: String = "", addrStateMap: mutable.Map[BigInt, Add
debugPrintln
(
f
"MaskedWrite, Addr: $alignAddr%x ,old sbData:$oldData%x , new sbData: $res%x , mask:$alignMask%x"
)
}
def
insertMaskedWordWrite
(
addr
:
BigInt
,
newWordData
:
BigInt
,
wordByteMask
:
BigInt
)
:
Unit
=
{
def
insertMaskedWordWrite
(
addr
:
BigInt
,
newWordData
:
BigInt
,
wordByteMask
:
BigInt
)
:
Unit
=
{
//addr and mask must be aligned to block
val
alignAddr
=
addrAlignBlock
(
addr
)
val
start_word
=
wordInBlock
(
addr
)
...
...
@@ -415,6 +420,14 @@ class TLCSlaveAgent(ID: Int, name: String = "", val maxSink: Int, addrStateMap:
}
}
override
def
transStep
()
:
Unit
=
{
innerAcquire
.
foreach
(
_
.
step
())
innerRelease
.
foreach
(
_
.
step
())
innerProbe
.
foreach
(
_
.
step
())
innerPut
.
foreach
(
_
.
step
())
innerGet
.
foreach
(
_
.
step
())
}
override
def
getState
(
addr
:
BigInt
)
:
AddrState
=
{
val
state
=
addrStateMap
.
getOrElse
(
addr
,
new
AddrState
())
if
(!
addrStateMap
.
contains
(
addr
))
{
//alloc new state if need
...
...
@@ -801,6 +814,11 @@ class TLCSlaveAgent(ID: Int, name: String = "", val maxSink: Int, addrStateMap:
pro
.
prepareProbe
(
addr
,
targetPerm
)
innerProbe
.
append
(
pro
)
}
override
def
step
()
:
Unit
=
{
freeSink
()
super
.
step
()
}
}
class
TLCMasterAgent
(
ID
:
Int
,
name
:
String
=
""
,
val
maxSource
:
Int
,
addrStateMap
:
mutable.Map
[
BigInt
,
AddrState
],
serialList
:
ArrayBuffer
[(
Int
,
TLCTrans
)]
...
...
@@ -827,6 +845,12 @@ class TLCMasterAgent(ID: Int, name: String = "", val maxSource: Int, addrStateMa
}
}
override
def
transStep
()
:
Unit
=
{
outerAcquire
.
foreach
(
_
.
step
())
outerRelease
.
foreach
(
_
.
step
())
outerProbe
.
foreach
(
_
.
step
())
}
val
bList
=
ListBuffer
[
TLCScalaB
]()
var
tmpD
=
new
TLCScalaD
()
...
...
@@ -1155,5 +1179,9 @@ class TLCMasterAgent(ID: Int, name: String = "", val maxSource: Int, addrStateMa
outerRelease
.
append
(
rel
)
}
override
def
step
()
:
Unit
=
{
freeSource
()
super
.
step
()
}
}
\ No newline at end of file
src/test/scala/cache/TLCTest/TLCTest.scala
浏览文件 @
11f61932
...
...
@@ -335,8 +335,6 @@ class TLCCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
if
(
AChannel_valids
(
i
)
&&
AChannel_ready
)
{
masterAgent
.
fireA
()
}
//handle some ID
masterAgent
.
freeSource
()
masterAgent
.
step
()
}
...
...
@@ -470,9 +468,6 @@ class TLCCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
}
slaveAgent
.
tickA
()
//handle some ID
slaveAgent
.
freeSink
()
slaveAgent
.
step
()
c
.
clock
.
step
()
}
...
...
src/test/scala/cache/TLCTest/TLCTransaction.scala
浏览文件 @
11f61932
...
...
@@ -266,6 +266,26 @@ trait PermissionTransition extends TLCOp {
abstract
class
TLCTrans
extends
TLCOp
with
PermissionTransition
with
BigIntExtract
{
val
blockSizeL2
=
BigInt
(
6
)
val
beatFullMask
=
BigInt
(
prefix
++
Array
.
fill
(
4
)(
0xff
.
toByte
))
private
var
timer
=
0
private
var
timerRunning
=
false
def
step
()
:
Unit
=
{
if
(
timerRunning
)
{
timer
+=
1
assert
(
timer
<=
1000
,
"transaction time out!"
)
}
}
def
startTimer
()
:
Unit
=
{
timer
=
0
timerRunning
=
true
}
def
resetTimer
()
:
Unit
=
{
timer
=
0
timerRunning
=
false
}
}
trait
TLCCallerTrans
extends
TLCTrans
{
...
...
@@ -313,6 +333,7 @@ class AcquireCallerTrans() extends AcquireTrans with TLCCallerTrans {
a
.
get
.
param
=
growParam
(
nowPerm
,
targetPerm
)
acquireIssued
=
Some
(
true
)
grantPending
=
Some
(
true
)
startTimer
()
a
.
get
}
...
...
@@ -322,6 +343,7 @@ class AcquireCallerTrans() extends AcquireTrans with TLCCallerTrans {
a
.
get
.
param
=
growParam
(
nowPerm
,
targetPerm
)
acquireIssued
=
Some
(
true
)
grantPending
=
Some
(
true
)
startTimer
()
a
.
get
}
...
...
@@ -329,6 +351,7 @@ class AcquireCallerTrans() extends AcquireTrans with TLCCallerTrans {
d
=
Some
(
inD
)
grantPending
=
Some
(
false
)
grantAckIssued
=
Some
(
false
)
resetTimer
()
}
def
issueGrantAck
()
:
TLCScalaE
=
{
...
...
@@ -363,6 +386,7 @@ class AcquireCalleeTrans() extends AcquireTrans with TLCCalleeTrans {
d
=
Some
(
genD
)
grantIssued
=
Some
(
true
)
grantAckPending
=
Some
(
true
)
startTimer
()
d
.
get
}
...
...
@@ -380,12 +404,14 @@ class AcquireCalleeTrans() extends AcquireTrans with TLCCalleeTrans {
d
=
Some
(
genD
)
grantIssued
=
Some
(
true
)
grantAckPending
=
Some
(
true
)
startTimer
()
d
.
get
}
def
pairGrantAck
(
inE
:
TLCScalaE
)
:
Unit
=
{
e
=
Some
(
inE
)
grantAckPending
=
Some
(
false
)
resetTimer
()
}
}
...
...
@@ -417,12 +443,14 @@ class ProbeCallerTrans() extends ProbeTrans with TLCCallerTrans {
def
issueProbe
()
:
TLCScalaB
=
{
probeIssued
=
Some
(
true
)
probeAckPending
=
Some
(
true
)
startTimer
()
b
.
get
}
def
pairProbeAck
(
inC
:
TLCScalaC
)
:
Unit
=
{
c
=
Some
(
inC
)
probeAckPending
=
Some
(
false
)
resetTimer
()
}
}
...
...
@@ -494,6 +522,7 @@ class ReleaseCallerTrans() extends ReleaseTrans with TLCCallerTrans {
c
.
get
.
source
=
sourceMapId
releaseIssued
=
Some
(
true
)
releaseAckPending
=
Some
(
true
)
startTimer
()
c
.
get
}
...
...
@@ -504,12 +533,14 @@ class ReleaseCallerTrans() extends ReleaseTrans with TLCCallerTrans {
c
.
get
.
data
=
inData
releaseIssued
=
Some
(
true
)
releaseAckPending
=
Some
(
true
)
startTimer
()
c
.
get
}
def
pairReleaseAck
(
inD
:
TLCScalaD
)
:
Unit
=
{
d
=
Some
(
inD
)
releaseAckPending
=
Some
(
false
)
resetTimer
()
}
}
...
...
@@ -546,12 +577,14 @@ class GetCallerTrans() extends GetTrans with TLCCallerTrans {
def
pairGet
(
inA
:
TLCScalaA
)
:
Unit
=
{
a
=
Some
(
inA
)
accessAckDataPending
=
Some
(
false
)
accessAckDataPending
=
Some
(
true
)
startTimer
()
}
def
pairAccessAckData
(
inD
:
TLCScalaD
)
:
Unit
=
{
d
=
Some
(
inD
)
accessAckDataPending
=
Some
(
true
)
accessAckDataPending
=
Some
(
false
)
resetTimer
()
}
}
...
...
@@ -589,12 +622,14 @@ class PutCallerTrans() extends GetTrans with TLCCallerTrans {
//inA will be concat in fireQueue
def
pairPut
(
inA
:
TLCScalaA
)
:
Unit
=
{
a
=
Some
(
inA
)
accessAckPending
=
Some
(
false
)
accessAckPending
=
Some
(
true
)
startTimer
()
}
def
pairAccessAck
(
inD
:
TLCScalaD
)
:
Unit
=
{
d
=
Some
(
inD
)
accessAckPending
=
Some
(
true
)
accessAckPending
=
Some
(
false
)
resetTimer
()
}
}
...
...
@@ -619,16 +654,4 @@ class PutCalleeTrans() extends GetTrans with TLCCalleeTrans {
accessAckIssued
=
Some
(
true
)
d
.
get
}
}
class
FakeTrans
(
val
addr
:
BigInt
)
extends
TLCTrans
with
BigIntExtract
{
var
data
:
BigInt
=
0
}
class
FakeReadTrans
(
addr
:
BigInt
)
extends
FakeTrans
(
addr
)
{
}
class
FakeWriteTrans
(
addr
:
BigInt
)
extends
FakeTrans
(
addr
)
{
var
newData
:
BigInt
=
0
}
\ No newline at end of file
src/test/scala/cache/TLCTest/TLULAgent.scala
浏览文件 @
11f61932
...
...
@@ -16,6 +16,11 @@ class TLULMasterAgent(ID: Int, name: String, addrStateMap: mutable.Map[BigInt, A
val
outerGet
:
mutable.Map
[
BigInt
,
GetCallerTrans
]
=
mutable
.
Map
[
BigInt
,
GetCallerTrans
]()
val
outerPut
:
mutable.Map
[
BigInt
,
PutCallerTrans
]
=
mutable
.
Map
[
BigInt
,
PutCallerTrans
]()
override
def
transStep
()
:
Unit
=
{
outerGet
.
foreach
(
_
.
_2
.
step
())
outerPut
.
foreach
(
_
.
_2
.
step
())
}
var
tmpA
=
new
TLCScalaA
()
var
a_cnt
=
0
var
a_cnt_end
=
0
...
...
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