提交 0f26349f 编写于 作者: L linjiawei

Add AXI4Ram Test

上级 0341d9bd
package device
import chipsalliance.rocketchip.config._
import chisel3._
import chisel3.util._
import chiseltest._
import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4MasterNode, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4UserYanker}
import freechips.rocketchip.diplomacy._
class AXI4BurstMaster
(
startAddr: Long = 0,
nOp: Int = 1,
beatBytes: Int = 8,
burstLen: Int = 16,
idRange: IdRange = IdRange(0, 1)
)(implicit p: Parameters) extends LazyModule {
val node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
Seq(AXI4MasterParameters("burst master", idRange))
)))
lazy val module = new LazyModuleImp(this){
val io = IO(new Bundle{
val finished = Output(Bool())
})
val (out, edge) = node.out.head
val cnt = RegInit(nOp.U)
val addr = RegInit(startAddr.U)
val s_idle :: s_addr :: s_data :: Nil = Enum(3)
val state = RegInit(s_idle)
val ar = out.ar
val r = out.r
switch(state){
is(s_idle){
when(cnt =/= 0.U){
state := s_addr
}
}
is(s_addr){
when(ar.ready){
state := s_data
}
}
is(s_data){
when(r.valid){
addr := addr + beatBytes.U
}
when(r.valid && r.bits.last){
state := s_idle
cnt := cnt - 1.U
}
}
}
io.finished := cnt === 0.U
ar.valid := state === s_addr
ar.bits.addr := addr
ar.bits.size := log2Up(beatBytes).U
ar.bits.len := (burstLen-1).U
ar.bits.burst := AXI4Parameters.BURST_INCR
r.ready := state === s_data
}
}
package device
import chipsalliance.rocketchip.config._
import chisel3._
import chiseltest._
import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4UserYanker}
import org.scalatest.{FlatSpec, Matchers}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy._
import utils.DebugIdentityNode
class AXI4RamFuzzTest()(implicit p: Parameters) extends LazyModule {
val addressSet = AddressSet(0x38000000L, 0x0000ffffL)
val fuzz = LazyModule(new TLFuzzer(
nOperations = 10,
overrideAddress = Some(addressSet),
inFlight = 1
))
val ident = LazyModule(new DebugIdentityNode())
val axiRam = LazyModule(new AXI4RAM(addressSet))
axiRam.node :=
AXI4UserYanker() :=
TLToAXI4() :=
TLFragmenter(8, 8) :=
ident.node :=
fuzz.node
lazy val module = new LazyModuleImp(this){
val finished = IO(Output(Bool()))
finished := fuzz.module.io.finished
}
}
class AXI4RamBurstTest()(implicit p: Parameters) extends LazyModule {
val addressSet = AddressSet(0x38000000L, 0x0000ffffL)
val burst = LazyModule(new AXI4BurstMaster(startAddr = addressSet.base.toLong, nOp = 3))
val axiRam = LazyModule(new AXI4RAM(addressSet))
axiRam.node := burst.node
lazy val module = new LazyModuleImp(this){
val finished = IO(Output(Bool()))
finished := burst.module.io.finished
}
}
class AXI4RamTLBurstTest()(implicit p: Parameters) extends LazyModule {
val addressSet = AddressSet(0x38000000L, 0x0000ffffL)
val tlburst = LazyModule(new TLBurstMaster(startAddr = addressSet.base.toLong, nOp = 3))
val ident = LazyModule(new DebugIdentityNode())
val axiRam = LazyModule(new AXI4RAM(addressSet))
axiRam.node :=
AXI4UserYanker() :=
TLToAXI4() :=
TLFragmenter(8, 8) :=
ident.node :=
tlburst.node
lazy val module = new LazyModuleImp(this){
val finished = IO(Output(Bool()))
finished := tlburst.module.io.finished
}
}
class AXI4RamTest extends FlatSpec with ChiselScalatestTester with Matchers {
it should "run with fuzz" in {
implicit val p = Parameters.empty
test(LazyModule(new AXI4RamFuzzTest()).module){ c =>
while (!c.finished.peek().litToBoolean){
c.clock.step(1)
}
}
}
it should "run in burst mode with axi master" in {
implicit val p = Parameters.empty
test(LazyModule(new AXI4RamBurstTest()).module){c =>
while (!c.finished.peek().litToBoolean){
c.clock.step(1)
}
}
}
it should "run in burst mode with tilelink master" in {
implicit val p = Parameters.empty
test(LazyModule(new AXI4RamTLBurstTest()).module){c =>
while (!c.finished.peek().litToBoolean){
c.clock.step(1)
}
}
}
}
package device
import chipsalliance.rocketchip.config._
import chisel3._
import chisel3.util._
import chiseltest._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy._
class TLBurstMaster
(
startAddr: Long = 0,
nOp: Int = 1,
beatBytes: Int = 8,
burstLen: Int = 16,
idRange: IdRange = IdRange(0, 1)
)(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(Seq(TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1("TLMaster", idRange))
)))
lazy val module = new LazyModuleImp(this){
val io = IO(new Bundle() {
val finished = Output(Bool())
})
val (out , edge) = node.out.head
val cnt = RegInit(nOp.U)
val addr = RegInit(startAddr.U)
val s_idle :: s_addr :: s_data :: Nil = Enum(3)
val state = RegInit(s_idle)
switch(state){
is(s_idle){
when(cnt =/= 0.U){
state := s_addr
}
}
is(s_addr){
when(out.a.fire()){
state := s_data
}
}
is(s_data){
when(out.d.fire()){
addr := addr + beatBytes.U
}
when(edge.done(out.d)){
state := s_idle
cnt := cnt - 1.U
}
}
}
io.finished := cnt===0.U
val a = out.a
val d = out.d
a.valid := state === s_addr
val (_, bundleA) = edge.Get(idRange.start.U, addr, log2Up(beatBytes*burstLen).U)
a.bits := bundleA
d.ready := state === s_data
}
}
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