Merge remote-tracking branch 'origin/master' into fix-boringutils

src/main/scala/xiangshan/frontend/PreDecode.scala

@@ -14,7 +14,7 @@ trait HasPdconst{ this: XSModule =>
     val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
     val rd = Mux(isRVC(instr), instr(12), instr(11,7))
     val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15))
-    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd)
+    val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64
     val isRet = brType === BrType.jalr && isLink(rs) && !isCall
     List(brType, isCall, isRet)
   }

src/main/scala/xiangshan/frontend/RAS.scala

@@ -104,7 +104,7 @@ class RAS extends BasePredictor
     //update commit ras
     val commit_push = !commit_is_full && io.recover.valid && io.recover.bits.pd.isCall
     val commit_pop = !commit_is_empty && io.recover.valid && io.recover.bits.pd.isRet
-    val commit_new_addr = io.recover.bits.pc + 4.U  //TODO: consider RVC
+    val commit_new_addr = Mux(io.recover.bits.pd.isRVC,io.recover.bits.pc + 2.U,io.recover.bits.pc + 4.U) 
     val commit_ras_write = WireInit(0.U.asTypeOf(rasEntry()))
     val commit_alloc_new = commit_new_addr =/= commit_ras_top_addr
     when (commit_push) {
@@ -200,4 +200,4 @@ class RAS extends BasePredictor
     //     }
     // }
 
-}
\ No newline at end of file
+}