TLB: change tlb's IO from ValidIO to DecoupledIO

.gitignore

@@ -347,3 +347,4 @@ mill.rdiB
 
 stale_outputs_checked
 
+*.snapshot

Makefile

@@ -70,6 +70,7 @@ VERILATOR_FLAGS = --top-module $(SIM_TOP) \
   +define+RANDOMIZE_MEM_INIT \
   $(VTHREAD_FLAGS) \
   --assert \
+	--trace \
   --savable \
   --stats-vars \
   --output-split 5000 \

src/main/scala/xiangshan/cache/dtlb.scala

@@ -157,10 +157,8 @@ class TlbResp extends TlbBundle {
 }
 
 class TlbRequestIO() extends TlbBundle {
-  val req = Valid(new TlbReq)
-  val resp = Flipped(Valid(new TlbResp))
-
-  // override def cloneType: this.type = (new TlbRequestIO(Width)).asInstanceOf[this.type]
+  val req = DecoupledIO(new TlbReq)
+  val resp = Flipped(DecoupledIO(new TlbResp))
 }
 
 class BlockTlbRequestIO() extends TlbBundle {
@@ -234,6 +232,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
       2.U -> Cat(hitppn(i), reqAddr(i).off)
     ))
 
+    req(i).ready := resp(i).ready
     resp(i).valid := valid(i)
     resp(i).bits.paddr := Mux(vmEnable, paddr, SignExt(req(i).bits.vaddr, PAddrBits))
     resp(i).bits.miss := miss(i)
@@ -282,7 +281,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
   }
 
   // reset pf when pf hit
-  val pfHitReset = ParallelOR(widthMap{i => Mux(valid(i), VecInit(pfHitVec(i)).asUInt, 0.U) })
+  val pfHitReset = ParallelOR(widthMap{i => Mux(resp(i).fire(), VecInit(pfHitVec(i)).asUInt, 0.U) })
   val pfHitRefill = ParallelOR(pfHitReset.asBools)
 
   // refill
@@ -359,8 +358,8 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
 
   // Log
   for(i <- 0 until Width) {
-    XSDebug(req(i).valid, p"req(${i.U}): ${req(i).bits}\n")
-    XSDebug(resp(i).valid, p"resp(${i.U}): ${resp(i).bits}\n")
+    XSDebug(req(i).valid, p"req(${i.U}): (${req(i).valid} ${req(i).ready}) ${req(i).bits}\n")
+    XSDebug(resp(i).valid, p"resp(${i.U}): (${resp(i).valid} ${resp(i).ready}) ${resp(i).bits}\n")
   }
 
   XSDebug(sfence.valid, p"Sfence: ${sfence}\n")
@@ -404,27 +403,24 @@ object TLB {
     
     if (!shouldBlock) { // dtlb
       for (i <- 0 until width) {
-        tlb.io.requestor(i).req.valid := in(i).req.valid
-        tlb.io.requestor(i).req.bits := in(i).req.bits
-        in(i).req.ready := DontCare
-
-        in(i).resp.valid := tlb.io.requestor(i).resp.valid
-        in(i).resp.bits := tlb.io.requestor(i).resp.bits
+        tlb.io.requestor(i) <> in(i)
+        // tlb.io.requestor(i).req.valid := in(i).req.valid
+        // tlb.io.requestor(i).req.bits := in(i).req.bits
+        // in(i).req.ready := tlb.io.requestor(i).req.ready
+
+        // in(i).resp.valid := tlb.io.requestor(i).resp.valid
+        // in(i).resp.bits := tlb.io.requestor(i).resp.bits
+        // tlb.io.requestor(i).resp.ready := in(i).resp.ready
       }
     } else { // itlb
       require(width == 1)
       tlb.io.requestor(0).req.valid := in(0).req.valid
       tlb.io.requestor(0).req.bits := in(0).req.bits
-      in(0).req.ready := !tlb.io.requestor(0).resp.bits.miss && in(0).resp.ready
-
-      // val pf = LookupTree(tlb.io.requestor(0).req.bits.cmd, List(
-      //   TlbCmd.read -> tlb.io.requestor(0).resp.bits.excp.pf.ld,
-      //   TlbCmd.write -> tlb.io.requestor(0).resp.bits.excp.pf.st,
-      //   TlbCmd.exec -> tlb.io.requestor(0).resp.bits.excp.pf.instr
-      // ))
+      in(0).req.ready := !tlb.io.requestor(0).resp.bits.miss && in(0).resp.ready && tlb.io.requestor(0).req.ready
 
       in(0).resp.valid := tlb.io.requestor(0).resp.valid && !tlb.io.requestor(0).resp.bits.miss
       in(0).resp.bits := tlb.io.requestor(0).resp.bits
+      tlb.io.requestor(0).resp.ready := in(0).resp.ready
     }
 
     tlb.io.ptw

src/main/scala/xiangshan/cache/ptw.scala

@@ -439,4 +439,6 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
   XSDebug(memRespFire, p"mem resp fire rdata:0x${Hexadecimal(mem.d.bits.data)} Pte:${memPte}\n")
 
   XSDebug(sfenceLatch, p"ptw has a flushed req waiting for resp... state:${state} mem.a(${mem.a.valid} ${mem.a.ready}) d($memValid} ${memRespReady})\n")
+
+  // TODO: add ptw perf cnt
 }

src/main/scala/xiangshan/mem/Memend.scala

@@ -186,6 +186,7 @@ class Memend extends XSModule {
   atomicsUnit.io.dtlb.resp.valid := false.B
   atomicsUnit.io.dtlb.resp.bits  := DontCare
   atomicsUnit.io.out.ready       := false.B
+  atomicsUnit.io.dtlb.req.ready  := dtlb.io.requestor(0).req.ready
 
   // dispatch 0 takes priority
   atomicsUnit.io.in.valid := st0_atomics || st1_atomics

src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala

@@ -45,6 +45,7 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
 
   io.dtlb.req.valid    := false.B
   io.dtlb.req.bits     := DontCare
+  io.dtlb.resp.ready   := false.B
 
   io.flush_sbuffer.valid := false.B
 
@@ -78,8 +79,9 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
     io.dtlb.req.bits.cmd    := Mux(is_lr, TlbCmd.read, TlbCmd.write)
     io.dtlb.req.bits.debug.pc := in.uop.cf.pc
     io.dtlb.req.bits.debug.lsroqIdx := in.uop.lsroqIdx // FIXME: need update
+    io.dtlb.resp.ready := true.B
 
-    when(io.dtlb.resp.valid && !io.dtlb.resp.bits.miss){
+    when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){
       // exception handling
       val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List(
         "b00".U   -> true.B,              //b

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -21,8 +21,8 @@ class LoadUnit_S0 extends XSModule {
     val in = Flipped(Decoupled(new ExuInput))
     val out = Decoupled(new LsPipelineBundle)
     val redirect = Flipped(ValidIO(new Redirect))
-    val dtlbReq = Valid(new TlbReq)
-    val dtlbResp = Flipped(Valid(new TlbResp))
+    val dtlbReq = DecoupledIO(new TlbReq)
+    val dtlbResp = Flipped(DecoupledIO(new TlbResp))
     val tlbFeedback = ValidIO(new TlbFeedback)
     val dcacheReq = DecoupledIO(new DCacheLoadReq)
   })
@@ -40,7 +40,9 @@ class LoadUnit_S0 extends XSModule {
   io.dtlbReq.bits.roqIdx := s0_uop.roqIdx
   io.dtlbReq.bits.debug.pc := s0_uop.cf.pc
   io.dtlbReq.bits.debug.lsroqIdx := s0_uop.lsroqIdx
-  
+  io.dtlbResp.ready := io.out.ready
+  // FIXME: tlb change to DecoupledIO, need to fix tlb's usage
+
   // feedback tlb result to RS
   // Note: can be moved to s1
   io.tlbFeedback.valid := io.out.valid

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -59,6 +59,7 @@ class StoreUnit extends XSModule {
   io.dtlb.req.bits.roqIdx := io.stin.bits.uop.roqIdx
   io.dtlb.req.bits.debug.pc := io.stin.bits.uop.cf.pc
   io.dtlb.req.bits.debug.lsroqIdx := io.stin.bits.uop.lsroqIdx // FIXME: need update
+  io.dtlb.resp.ready := s2_out.ready
 
   s2_out.bits := DontCare
   s2_out.bits.vaddr := saddr