Merge pull request #313 from RISCVERS/icache-access-fault

Icache access fault

src/main/scala/xiangshan/Bundle.scala

@@ -24,6 +24,7 @@ class FetchPacket extends XSBundle {
   val brInfo = Vec(PredictWidth, new BranchInfo)
   val pd = Vec(PredictWidth, new PreDecodeInfo)
   val ipf = Bool()
+  val acf = Bool()
   val crossPageIPFFix = Bool()
   val predTaken = Bool()
 }

src/main/scala/xiangshan/cache/icache.scala

@@ -30,6 +30,9 @@ case class ICacheParameters(
 trait HasICacheParameters extends HasL1CacheParameters {
   val cacheParams = icacheParameters
 
+  //TODO: temp set
+  def accessBorder =  0x80000000L
+
   // the width of inner CPU data interface
   def cacheID = 0
   // RVC instruction length
@@ -88,6 +91,7 @@ class ICacheResp extends ICacheBundle
   val data = UInt((FetchWidth * 32).W)
   val mask = UInt(PredictWidth.W)
   val ipf = Bool()
+  val acf = Bool()
 }
 
 
@@ -282,6 +286,7 @@ class ICache extends ICacheModule
   
   // SRAM(Meta and Data) read request
   val s1_idx = get_idx(s1_req_pc)
+
   metaArray.io.read.valid := s1_valid
   metaArray.io.read.bits  :=s1_idx
   dataArray.io.read.valid := s1_valid
@@ -298,11 +303,16 @@ class ICache extends ICacheModule
   val s2_tlb_resp = WireInit(io.tlb.resp.bits)
   val s2_tag = get_tag(s2_tlb_resp.paddr)
   val s2_hit = WireInit(false.B)
+  val s2_access_fault = WireInit(false.B)
   s2_fire := s2_valid && s3_ready && !io.flush(0) && io.tlb.resp.fire()
   when(io.flush(0)) {s2_valid := s1_fire}
   .elsewhen(s1_fire) { s2_valid := s1_valid}
   .elsewhen(s2_fire) { s2_valid := false.B}
 
+  //physical address < 0x80000000
+  //TODO: May have bugs
+  s2_access_fault := (s2_tlb_resp.paddr(31,0) < accessBorder.U(31,0)) && s2_valid
+
   // SRAM(Meta and Data) read reseponse
   val metas = metaArray.io.readResp
   val datas =RegEnable(next=dataArray.io.readResp, enable=s2_fire)
@@ -318,10 +328,10 @@ class ICache extends ICacheModule
   
   val waymask = Mux(s2_hit, hitVec.asUInt, Mux(hasInvalidWay, refillInvalidWaymask, victimWayMask))
  
-  s2_hit := ParallelOR(hitVec) || s2_tlb_resp.excp.pf.instr
+  s2_hit := ParallelOR(hitVec) || s2_tlb_resp.excp.pf.instr || s2_access_fault
   s2_ready := s2_fire || !s2_valid || io.flush(0)
 
-  XSDebug("[Stage 2] v : r : f  (%d  %d  %d)  pc: 0x%x  mask: %b\n",s2_valid,s3_ready,s2_fire,s2_req_pc,s2_req_mask)
+  XSDebug("[Stage 2] v : r : f  (%d  %d  %d)  pc: 0x%x  mask: %b acf:%d\n",s2_valid,s3_ready,s2_fire,s2_req_pc,s2_req_mask,s2_access_fault)
   XSDebug(p"[Stage 2] tlb req:  v ${io.tlb.req.valid} r ${io.tlb.req.ready} ${io.tlb.req.bits}\n")
   XSDebug(p"[Stage 2] tlb resp: v ${io.tlb.resp.valid} r ${io.tlb.resp.ready} ${s2_tlb_resp}\n")
   XSDebug("[Stage 2] tag: %x  hit:%d\n",s2_tag,s2_hit)
@@ -338,6 +348,7 @@ class ICache extends ICacheModule
   val s3_wayMask = RegEnable(next=waymask,init=0.U,enable=s2_fire)
   val s3_miss = s3_valid && !s3_hit
   val s3_idx = get_idx(s3_req_pc)
+  val s3_access_fault = RegEnable(s2_access_fault,init=false.B,enable=s2_fire)
   when(io.flush(1)) { s3_valid := false.B }
   .elsewhen(s2_fire) { s3_valid := s2_valid }
   .elsewhen(io.resp.fire()) { s3_valid := false.B } 
@@ -411,7 +422,7 @@ class ICache extends ICacheModule
   s3_ready := ((io.resp.fire() || !s3_valid) && !blocking) || (blocking && icacheMissQueue.io.resp.fire())
 
   //TODO: coherence
-  XSDebug("[Stage 3] valid:%d   pc: 0x%x  mask: %b ipf:%d\n",s3_valid,s3_req_pc,s3_req_mask,s3_tlb_resp.excp.pf.instr)
+  XSDebug("[Stage 3] valid:%d   pc: 0x%x  mask: %b ipf:%d acf:%d \n",s3_valid,s3_req_pc,s3_req_mask,s3_tlb_resp.excp.pf.instr,s3_access_fault)
   XSDebug("[Stage 3] hit:%d  miss:%d  waymask:%x blocking:%d\n",s3_hit,s3_miss,s3_wayMask.asUInt,blocking)
   XSDebug("[Stage 3] tag: %x    idx: %d\n",s3_tag,get_idx(s3_req_pc))
   XSDebug(p"[Stage 3] tlb resp: ${s3_tlb_resp}\n")
@@ -436,6 +447,7 @@ class ICache extends ICacheModule
   io.resp.bits.mask := s3_req_mask
   io.resp.bits.pc := s3_req_pc
   io.resp.bits.ipf := s3_tlb_resp.excp.pf.instr
+  io.resp.bits.acf := s3_access_fault
 
   //to itlb
   io.tlb.resp.ready := s3_ready

src/main/scala/xiangshan/frontend/IFU.scala

@@ -278,6 +278,7 @@ class IFU extends XSModule with HasIFUConst
   //********************** IF4 ****************************//
   val if4_pd = RegEnable(pd.io.out, if3_fire)
   val if4_ipf = RegEnable(icacheResp.ipf || if3_prevHalfInstrMet && if3_prevHalfInstr.ipf, if3_fire)
+  val if4_acf = RegEnable(icacheResp.acf, if3_fire)
   val if4_crossPageIPF = RegEnable(crossPageIPF, if3_fire)
   val if4_valid = RegInit(false.B)
   val if4_fire = if4_valid && io.fetchPacket.ready
@@ -513,6 +514,7 @@ class IFU extends XSModule with HasIFUConst
   (0 until PredictWidth).foreach(i => fetchPacketWire.brInfo(i).predHistPtr := if4_predHistPtr)
   fetchPacketWire.pd := if4_pd.pd
   fetchPacketWire.ipf := if4_ipf
+  fetchPacketWire.acf := if4_acf
   fetchPacketWire.crossPageIPFFix := if4_crossPageIPF
 
   // predTaken Vec
@@ -561,8 +563,8 @@ class IFU extends XSModule with HasIFUConst
     XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n",
       if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr, if4_prevHalfInstr.ipf)
     if4_GHInfo.debug("if4")
-    XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d crossPageIPF=%d\n",
-      io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask, io.fetchPacket.bits.ipf, io.fetchPacket.bits.crossPageIPFFix)
+    XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d acf=%d crossPageIPF=%d\n",
+      io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask, io.fetchPacket.bits.ipf,io.fetchPacket.bits.acf , io.fetchPacket.bits.crossPageIPFFix)
     for (i <- 0 until PredictWidth) {
       XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n",
         io.fetchPacket.bits.mask(i),

src/test/csrc/ram.cpp

@@ -215,9 +215,7 @@ void ram_finish() {
 
 extern "C" uint64_t ram_read_helper(uint8_t en, uint64_t rIdx) {
   if (en && rIdx >= RAMSIZE / sizeof(uint64_t)) {
-    printf("WARN: ram rIdx = 0x%lx out of bound!\n", rIdx);
-    // assert(rIdx < RAMSIZE / sizeof(uint64_t));
-    return 0x12345678deadbeafULL;
+    rIdx %= RAMSIZE / sizeof(uint64_t);
   }
   return (en) ? ram[rIdx] : 0;
 }