[DONT MERGE] 2-bit store set perf

08fcf6e6 · William Wang · 7fc13d33 · 08fcf6e6
隐藏空白更改
内联并排

Showing with 2 addition and 2 deletion

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala +2 -2

未找到文件。
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
@@ -151,8 +151,8 @@ class Dispatch1 extends XSModule with HasExceptionNO {
    lfst.io.lookup.raddr(i) := updatedUop(i).cf.ssid
    lfst.io.lookup.ren(i) := updatedUop(i).cf.storeSetHit
    // updatedUop(i).cf.loadWaitBit := lfst.io.lookup.rdata(i) // classic store set
-    updatedUop(i).cf.loadWaitBit := lfst.io.lookup.rdata(i) && !isStore(i) // store set lite
-    // updatedUop(i).cf.loadWaitBit := lfst.io.lookup.rdata(i) && io.fromRename(i).bits.cf.loadWaitBit && !isStore(i) // 2-bit store set
+    // updatedUop(i).cf.loadWaitBit := lfst.io.lookup.rdata(i) && !isStore(i) // store set lite
+    updatedUop(i).cf.loadWaitBit := lfst.io.lookup.rdata(i) && io.fromRename(i).bits.cf.loadWaitBit && !isStore(i) // 2-bit store set

    // update store set LFST
    io.lfst(i).valid := io.fromRename(i).valid && updatedUop(i).cf.storeSetHit && isStore(i)