backend: fix div valid signal

The nanhu version make div valid signal ahead of data by one cycle to
optimize timing of wbArbiter. We make `io.valid` signal assert at the
same time of data valid as normal now, and add `io.validNext` signal
which asserts one cycle ahead of `io.valid`.

src/main/scala/xiangshan/backend/fu/SRT16Divider.scala

@@ -34,6 +34,7 @@ class SRT16DividerDataModule(len: Int) extends Module {
     val valid, sign, kill_w, kill_r, isHi, isW = Input(Bool())
     val in_ready = Output(Bool())
     val out_valid = Output(Bool())
+    val out_validNext = Output(Bool())
     val out_data = Output(UInt(len.W))
     val out_ready = Input(Bool())
   })
@@ -90,9 +91,9 @@ class SRT16DividerDataModule(len: Int) extends Module {
     state := Mux(finalIter, UIntToOH(s_post_0, 7), UIntToOH(s_iter, 7))
   } .elsewhen(state(s_post_0)) { // if rem < 0, rem = rem + d
     state := UIntToOH(s_post_1, 7)
-  } .elsewhen(state(s_post_1) && out_fire) {
+  } .elsewhen(state(s_post_1)) {
     state := UIntToOH(s_finish, 7)
-  } .elsewhen(state(s_finish)) {
+  } .elsewhen(state(s_finish) && io.out_ready) {
     state := UIntToOH(s_idle, 7)
   } .otherwise {
     state := state
@@ -389,8 +390,8 @@ class SRT16DividerDataModule(len: Int) extends Module {
     res
   )
   io.in_ready := state(s_idle)
-  io.out_valid := state(s_post_1)
-
+  io.out_valid := state(s_finish)
+  io.out_validNext := state(s_post_1)
 }
 
 object mLookUpTable2 {

src/main/scala/xiangshan/v2backend/fu/DivUnit.scala

@@ -38,13 +38,15 @@ class DivUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) {
   divDataModule.io.valid := io.in.valid
   divDataModule.io.src(0) := divInputCvtFunc(io.in.bits.src(0))
   divDataModule.io.src(1) := divInputCvtFunc(io.in.bits.src(1))
-  divDataModule.io.sign := ctrl.sign // Todo: check it if assign with ctrlReg
+  divDataModule.io.sign := ctrl.sign
   divDataModule.io.kill_w := kill_w
   divDataModule.io.kill_r := kill_r
   divDataModule.io.isHi := ctrlReg.isHi
   divDataModule.io.isW := ctrlReg.isW
   divDataModule.io.out_ready := io.out.ready
 
+  val validNext = divDataModule.io.out_validNext // if high, io.valid will assert next cycle
+
   io.in.ready := divDataModule.io.in_ready
   io.out.valid := divDataModule.io.out_valid
   io.out.bits.data := divDataModule.io.out_data