Merge branch 'master' into alu-jr

add jump to ALU and ALU's log info

src/main/scala/xiangshan/Bundle.scala

@@ -8,7 +8,7 @@ import xiangshan.backend.rename.FreeListPtr
 // Fetch FetchWidth x 32-bit insts from Icache
 class FetchPacket extends XSBundle {
   val instrs = Vec(FetchWidth, UInt(32.W))
-  val mask = UInt(FetchWidth.W)
+  val mask = UInt((FetchWidth*2).W)
   val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
 }
 
@@ -104,4 +104,4 @@ class FrontendToBackendIO extends XSBundle {
   // from backend
   val redirect = Flipped(ValidIO(new Redirect))
   val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred
-}
\ No newline at end of file
+}

src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala

@@ -212,19 +212,22 @@ class Dispatch2 extends XSModule {
 //      Mux(src3Type(i)(0), io.intPregRdy(src3Index(i)), io.fpPregRdy(src3Index(i))))
     val src1 = Mux(src1Type(i)(1), 0.U,
       Mux(src1Type(i)(0), io.readFpRf(src1Index(i)).data, io.readIntRf(src1Index(i)).data))
-    io.enqIQData(i).bits.src1 := Mux(index_reg(i)(2), 0.U, src1)
+    io.enqIQData(i).bits.src1 := Mux(io.enqIQData(i).bits.uop.ctrl.src1Type === SrcType.pc,
+        io.enqIQData(i).bits.uop.cf.pc, Mux(index_reg(i)(2), 0.U, src1))
     val src2 = Mux(src2Type(i)(1), 0.U,
       Mux(src2Type(i)(0), io.readFpRf(src2Index(i)).data, io.readIntRf(src2Index(i)).data))
-    io.enqIQData(i).bits.src2 := Mux(index_reg(i)(2), 0.U, src2)
+    io.enqIQData(i).bits.src2 := Mux(io.enqIQData(i).bits.uop.ctrl.src1Type === SrcType.imm,
+      io.enqIQData(i).bits.uop.ctrl.imm, Mux(index_reg(i)(2), 0.U, src2))
     val src3 = Mux(src3Type(i)(1), 0.U,
       Mux(src3Type(i)(0), io.readFpRf(src3Index(i)).data, io.readIntRf(src3Index(i)).data))
     io.enqIQData(i).bits.src3 := Mux(index_reg(i)(2), 0.U, src3)
 
     XSDebug(io.enqIQData(i).valid,
       "instruction 0x%x reads operands from (%d, %d, %d, %x), (%d, %d, %d, %x), (%d, %d, %d, %x)\n",
-      io.enqIQData(i).bits.uop.cf.pc, src1Type(i), src1Index(i), io.enqIQData(i).bits.uop.psrc1, src1,
-      src2Type(i), src2Index(i), io.enqIQData(i).bits.uop.psrc2, src2,
-      src3Type(i), src3Index(i), io.enqIQData(i).bits.uop.psrc3, src3)
+      io.enqIQData(i).bits.uop.cf.pc,
+      src1Type(i), src1Index(i), io.enqIQData(i).bits.uop.psrc1, io.enqIQData(i).bits.src1,
+      src2Type(i), src2Index(i), io.enqIQData(i).bits.uop.psrc2, io.enqIQData(i).bits.src2,
+      src3Type(i), src3Index(i), io.enqIQData(i).bits.uop.psrc3, io.enqIQData(i).bits.src3)
   }
 
 }

src/main/scala/xiangshan/backend/issue/IssueQueue.scala

@@ -28,38 +28,26 @@ sealed class CmpInputBundle extends IQBundle{
 }
 
 
-sealed class CompareCircuitUnit extends IQModule {
-  val io = IO(new Bundle(){
-    val in1 = new CmpInputBundle
-    val in2 = new CmpInputBundle
-    val out = Flipped(new CmpInputBundle)
-  })
-
-  val roqIdx1 = io.in1.roqIdx
-  val roqIdx2 = io.in2.roqIdx
-  val iqIdx1  = io.in1.iqIdx
-  val iqIdx2  = io.in2.iqIdx
-
-  val inst1Rdy = io.in1.instRdy
-  val inst2Rdy = io.in2.instRdy
-
-  io.out.instRdy := inst1Rdy | inst2Rdy
-  io.out.roqIdx := roqIdx2
-  io.out.iqIdx := iqIdx2
-
-  when((inst1Rdy && !inst2Rdy) || (inst1Rdy && inst2Rdy && (roqIdx1 < roqIdx2))){
-    io.out.roqIdx := roqIdx1
-    io.out.iqIdx := iqIdx1
-  }
-
-}
-
-object CCU{
+object CompareCircuitUnit{
   def apply(in1: CmpInputBundle, in2: CmpInputBundle) = {
-    val CCU = Module(new CompareCircuitUnit)
-    CCU.io.in1 <> in1
-    CCU.io.in2 <> in2
-    CCU.io.out
+    val out = Wire(new CmpInputBundle)
+    val roqIdx1 = in1.roqIdx
+    val roqIdx2 = in2.roqIdx
+    val iqIdx1  = in1.iqIdx
+    val iqIdx2  = in2.iqIdx
+
+    val inst1Rdy = in1.instRdy
+    val inst2Rdy = in2.instRdy
+
+    out.instRdy := inst1Rdy | inst2Rdy
+    out.roqIdx := roqIdx2
+    out.iqIdx := iqIdx2
+
+    when((inst1Rdy && !inst2Rdy) || (inst1Rdy && inst2Rdy && (roqIdx1 < roqIdx2))){
+      out.roqIdx := roqIdx1
+      out.iqIdx := iqIdx1
+    }
+    out
   }
 }
 
@@ -67,7 +55,7 @@ object ParallelSel {
   def apply(iq: Seq[CmpInputBundle]):  CmpInputBundle = {
     iq match {
       case Seq(a) => a
-      case Seq(a, b) => CCU(a, b)
+      case Seq(a, b) => CompareCircuitUnit(a, b)
       case _ =>
         apply(Seq(apply(iq take iq.size/2), apply(iq drop iq.size/2)))
     }

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -13,13 +13,6 @@ class Ibuffer extends XSModule {
     val out = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
   })
 
-  when(io.in.valid) {
-    XSDebug("cache data\n")
-    for (i <- 0 until FetchWidth) {
-      XSDebug("%b\n", io.in.bits.instrs(i))
-    }
-  }
-
   // ignore
   for(i <- 0 until DecodeWidth) {
     io.out(i).bits.exceptionVec := DontCare
@@ -27,9 +20,13 @@ class Ibuffer extends XSModule {
     io.out(i).bits.isBr := DontCare
   }
 
+  //mask initial
+  //  val mask = Wire(Vec(FetchWidth*2, false.B))
+  //  (0 until 16).map(i => mask(i.U) := (io.in.bits.pc(4,1) <= i.U))
+
   // ibuf define
-  val ibuf = RegInit(VecInit(Seq.fill(IBufSize*2)(0.U(16.W))))
-  val ibuf_pc = RegInit(VecInit(Seq.fill(IBufSize*2)(0.U(VAddrBits.W))))
+  val ibuf = Reg(Vec(IBufSize*2, UInt(16.W)))
+  val ibuf_pc = Reg(Vec(IBufSize*2, UInt(VAddrBits.W)))
   val ibuf_valid = RegInit(VecInit(Seq.fill(IBufSize*2)(false.B)))
   val head_ptr = RegInit(0.U(log2Up(IBufSize*2).W))
   val tail_ptr = RegInit(0.U(log2Up(IBufSize*2).W))
@@ -46,35 +43,22 @@ class Ibuffer extends XSModule {
 
   // enque
   when(enqValid) {
-    XSInfo("Enque start\n")
-
     var enq_idx = 0.U(log2Up(FetchWidth*2+1).W)
-    for(i <- 0 until FetchWidth) {
+    for(i <- 0 until FetchWidth*2) {
       when(io.in.bits.mask(i)) {
-        ibuf(tail_ptr + enq_idx) := io.in.bits.instrs(i)(15,0)
-        ibuf_pc(tail_ptr + enq_idx) := io.in.bits.pc + enq_idx + enq_idx
+        ibuf(tail_ptr + enq_idx) := Mux(i.U(0), io.in.bits.instrs(i>>1)(31,16), io.in.bits.instrs(i>>1)(15,0))
+        ibuf_pc(tail_ptr + enq_idx) := io.in.bits.pc + (enq_idx<<1).asUInt
         ibuf_valid(tail_ptr + enq_idx) := true.B
-
-        ibuf(tail_ptr + enq_idx+1.U) := io.in.bits.instrs(i)(31,16)
-        ibuf_pc(tail_ptr + enq_idx+1.U) := io.in.bits.pc + enq_idx + enq_idx + 2.U
-        ibuf_valid(tail_ptr + enq_idx+1.U) := true.B
-
-        XSDebug("Enque: %b\n", io.in.bits.instrs(i)(15,0))
-        XSDebug("Enque: %b\n", io.in.bits.instrs(i)(31,16))
       }
-      enq_idx = enq_idx + io.in.bits.mask(i) + io.in.bits.mask(i)
+      enq_idx = enq_idx + io.in.bits.mask(i)
     }
 
     tail_ptr := tail_ptr + enq_idx
     last_enq := true.B
-
-    XSInfo("Enque finished, tail_ptr=%d\n", tail_ptr + enq_idx)
   }
 
   // deque
   when(deqValid) {
-    XSInfo("Deque start\n")
-
     var deq_idx = 0.U(log2Up(DecodeWidth*2+1).W)
     for(i <- 0 until DecodeWidth) {
       when(io.out(i).ready && ibuf_valid(head_ptr + deq_idx)) {
@@ -82,8 +66,6 @@ class Ibuffer extends XSModule {
           // is RVC
           io.out(i).bits.instr := Cat(0.U(16.W), ibuf(head_ptr + deq_idx))
           io.out(i).bits.pc := ibuf_pc(head_ptr + deq_idx)
-          XSDebug("%b[RVC] PC=%d\n", Cat(0.U(16.W), ibuf(head_ptr + deq_idx)), ibuf_pc(head_ptr + deq_idx))
-
           io.out(i).bits.isRVC := true.B
           io.out(i).valid := true.B
           ibuf_valid(head_ptr + deq_idx) := false.B
@@ -91,8 +73,6 @@ class Ibuffer extends XSModule {
           // isn't RVC
           io.out(i).bits.instr := Cat(ibuf(head_ptr + deq_idx+1.U), ibuf(head_ptr + deq_idx))
           io.out(i).bits.pc := ibuf_pc(head_ptr + deq_idx)
-          XSDebug("%b[NORVC] PC=%d\n", Cat(ibuf(head_ptr + deq_idx+1.U), ibuf(head_ptr + deq_idx)), ibuf_pc(head_ptr + deq_idx))
-
           io.out(i).bits.isRVC := false.B
           io.out(i).valid := true.B
           ibuf_valid(head_ptr + deq_idx) := false.B
@@ -100,15 +80,11 @@ class Ibuffer extends XSModule {
         }.otherwise {
           // half inst keep in buffer
           io.out(i).bits.instr := 0.U(32.W)
-          XSWarn("This is half inst\n")
-
           io.out(i).bits.pc := 0.U(VAddrBits.W)
           io.out(i).bits.isRVC := false.B
           io.out(i).valid := false.B
         }
       }.otherwise {
-        XSWarn("This output is not ready, or buffer is empty\n")
-
         io.out(i).bits.instr := 0.U
         io.out(i).bits.pc := 0.U
         io.out(i).bits.isRVC := false.B
@@ -119,15 +95,14 @@ class Ibuffer extends XSModule {
       // when RVC deque, deq_idx+1
       // when not RVC deque, deq_idx+2
       // when only have half inst, keep it in buffer
-      deq_idx = deq_idx +
-                (io.out(i).ready && ibuf_valid(head_ptr + deq_idx) && ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) +
-                (io.out(i).ready && ibuf_valid(head_ptr + deq_idx) && !(ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) && ibuf_valid(head_ptr + deq_idx + 1.U)) +
-                (io.out(i).ready && ibuf_valid(head_ptr + deq_idx) && !(ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) && ibuf_valid(head_ptr + deq_idx + 1.U))
+      deq_idx = deq_idx + PriorityMux(Seq(
+        !(io.out(i).ready && ibuf_valid(head_ptr + deq_idx)) -> 0.U,
+        (ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) -> 1.U,
+        ibuf_valid(head_ptr + deq_idx + 1.U) -> 2.U
+      ))
     }
     head_ptr := head_ptr + deq_idx
 
-    XSInfo("Deque finished\n")
-    XSInfo("head_prt=%d, tail_ptr=%d\n", head_ptr + deq_idx, tail_ptr)
     last_enq := false.B
   }.otherwise {
     for(i <- 0 until DecodeWidth) {
@@ -140,7 +115,6 @@ class Ibuffer extends XSModule {
 
   // flush
   when(io.flush) {
-    XSInfo("Flush signal received, clear buffer\n")
     for(i <- 0 until IBufSize) {
       ibuf_valid(i) := false.B
       head_ptr := 0.U
@@ -151,4 +125,18 @@ class Ibuffer extends XSModule {
       io.out(i).valid := false.B
     }
   }
+
+  //Debug Info
+//  XSDebug(enqValid, "Enque:\n")
+//  for(i <- 0 until FetchWidth) {
+//    XSDebug(enqValid, p"${Binary(io.in.bits.instrs(i))}\n")
+//  }
+
+  XSInfo(io.flush, "Flush signal received, clear buffer\n")
+  XSDebug(deqValid, "Deque:\n")
+  for(i <- 0 until DecodeWidth) {
+    XSDebug(deqValid, p"${Binary(io.out(i).bits.instr)}  PC=${Hexadecimal(io.out(i).bits.pc)}\n")
+  }
+//  XSDebug(enqValid, p"last_head_ptr=$head_ptr  last_tail_ptr=$tail_ptr\n")
+//  XSInfo(full, "Queue is full\n")
 }
\ No newline at end of file