Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OpenXiangShan
XiangShan
提交
02328a5f
X
XiangShan
项目概览
OpenXiangShan
/
XiangShan
10 个月 前同步成功
通知
1183
Star
3914
Fork
526
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
X
XiangShan
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
未验证
提交
02328a5f
编写于
12月 15, 2020
作者:
Y
Yinan Xu
提交者:
GitHub
12月 15, 2020
浏览文件
操作
浏览文件
下载
差异文件
Merge pull request #322 from RISCVERS/ifu-register-naming
Ifu register naming
上级
6140f0d4
425cd60b
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
152 addition
and
152 deletion
+152
-152
src/main/scala/xiangshan/frontend/Bim.scala
src/main/scala/xiangshan/frontend/Bim.scala
+15
-15
src/main/scala/xiangshan/frontend/Btb.scala
src/main/scala/xiangshan/frontend/Btb.scala
+49
-49
src/main/scala/xiangshan/frontend/Tage.scala
src/main/scala/xiangshan/frontend/Tage.scala
+88
-88
未找到文件。
src/main/scala/xiangshan/frontend/Bim.scala
浏览文件 @
02328a5f
...
...
@@ -35,8 +35,8 @@ class BIM extends BasePredictor with BimParams {
val
bimAddr
=
new
TableAddr
(
log2Up
(
BimSize
),
BimBanks
)
val
bankAlignedPC
=
bankAligned
(
io
.
pc
.
bits
)
val
pcLatch
=
RegEnable
(
bankAlignedPC
,
io
.
pc
.
valid
)
val
if1_
bankAlignedPC
=
bankAligned
(
io
.
pc
.
bits
)
val
if2_pc
=
RegEnable
(
if1_
bankAlignedPC
,
io
.
pc
.
valid
)
val
bim
=
List
.
fill
(
BimBanks
)
{
Module
(
new
SRAMTemplate
(
UInt
(
2.
W
),
set
=
nRows
,
shouldReset
=
false
,
holdRead
=
true
))
...
...
@@ -48,34 +48,34 @@ class BIM extends BasePredictor with BimParams {
when
(
resetRow
===
(
nRows
-
1
).
U
)
{
doing_reset
:=
false
.
B
}
// this bank means cache bank
val
startsAtOddBank
=
bankInGroup
(
bankAlignedPC
)(
0
)
val
if1_startsAtOddBank
=
bankInGroup
(
if1_
bankAlignedPC
)(
0
)
val
realMask
=
Mux
(
startsAtOddBank
,
val
if1_realMask
=
Mux
(
if1_
startsAtOddBank
,
Cat
(
io
.
inMask
(
bankWidth
-
1
,
0
),
io
.
inMask
(
PredictWidth
-
1
,
bankWidth
)),
io
.
inMask
)
val
i
sInNextRow
=
VecInit
((
0
until
BimBanks
).
map
(
i
=>
Mux
(
startsAtOddBank
,
(
i
<
bankWidth
).
B
,
false
.
B
)))
val
i
f1_isInNextRow
=
VecInit
((
0
until
BimBanks
).
map
(
i
=>
Mux
(
if1_
startsAtOddBank
,
(
i
<
bankWidth
).
B
,
false
.
B
)))
val
baseRow
=
bimAddr
.
getBankIdx
(
bankAlignedPC
)
val
if1_baseRow
=
bimAddr
.
getBankIdx
(
if1_
bankAlignedPC
)
val
realRow
=
VecInit
((
0
until
BimBanks
).
map
(
b
=>
Mux
(
isInNextRow
(
b
),
(
baseRow
+
1.
U
)(
log2Up
(
nRows
)-
1
,
0
),
baseRow
)))
val
if1_realRow
=
VecInit
((
0
until
BimBanks
).
map
(
b
=>
Mux
(
if1_isInNextRow
(
b
),
(
if1_baseRow
+
1.
U
)(
log2Up
(
nRows
)-
1
,
0
),
if1_
baseRow
)))
val
realRowLatch
=
VecInit
(
realRow
.
map
(
RegEnable
(
_
,
enable
=
io
.
pc
.
valid
)))
val
if2_realRow
=
VecInit
(
if1_
realRow
.
map
(
RegEnable
(
_
,
enable
=
io
.
pc
.
valid
)))
for
(
b
<-
0
until
BimBanks
)
{
bim
(
b
).
io
.
r
.
req
.
valid
:=
realMask
(
b
)
&&
io
.
pc
.
valid
bim
(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
realRow
(
b
)
bim
(
b
).
io
.
r
.
req
.
valid
:=
if1_
realMask
(
b
)
&&
io
.
pc
.
valid
bim
(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
if1_
realRow
(
b
)
}
val
bimRead
=
VecInit
(
bim
.
map
(
_
.
io
.
r
.
resp
.
data
(
0
)))
val
if2_
bimRead
=
VecInit
(
bim
.
map
(
_
.
io
.
r
.
resp
.
data
(
0
)))
val
startsAtOddBankLatch
=
bankInGroup
(
pcLatch
)(
0
)
val
if2_startsAtOddBank
=
bankInGroup
(
if2_pc
)(
0
)
for
(
b
<-
0
until
BimBanks
)
{
val
realBank
=
(
if
(
b
<
bankWidth
)
Mux
(
startsAtOddBankLatch
,
(
b
+
bankWidth
).
U
,
b
.
U
)
else
Mux
(
startsAtOddBankLatch
,
(
b
-
bankWidth
).
U
,
b
.
U
))
val
ctr
=
bimRead
(
realBank
)
val
realBank
=
(
if
(
b
<
bankWidth
)
Mux
(
if2_startsAtOddBank
,
(
b
+
bankWidth
).
U
,
b
.
U
)
else
Mux
(
if2_startsAtOddBank
,
(
b
-
bankWidth
).
U
,
b
.
U
))
val
ctr
=
if2_
bimRead
(
realBank
)
io
.
resp
.
ctrs
(
b
)
:=
ctr
io
.
meta
.
ctrs
(
b
)
:=
ctr
}
...
...
src/main/scala/xiangshan/frontend/Btb.scala
浏览文件 @
02328a5f
...
...
@@ -72,9 +72,9 @@ class BTB extends BasePredictor with BTBParams{
override
val
io
=
IO
(
new
BTBIO
)
val
btbAddr
=
new
TableAddr
(
log2Up
(
BtbSize
/
BtbWays
),
BtbBanks
)
val
bankAlignedPC
=
bankAligned
(
io
.
pc
.
bits
)
val
if1_
bankAlignedPC
=
bankAligned
(
io
.
pc
.
bits
)
val
pcLatch
=
RegEnable
(
bankAlignedPC
,
io
.
pc
.
valid
)
val
if2_pc
=
RegEnable
(
if1_
bankAlignedPC
,
io
.
pc
.
valid
)
val
data
=
List
.
fill
(
BtbWays
)
{
List
.
fill
(
BtbBanks
)
{
...
...
@@ -91,61 +91,61 @@ class BTB extends BasePredictor with BTBParams{
// BTB read requests
// this bank means cache bank
val
startsAtOddBank
=
bankInGroup
(
bankAlignedPC
)(
0
)
val
if1_startsAtOddBank
=
bankInGroup
(
if1_
bankAlignedPC
)(
0
)
val
baseBank
=
btbAddr
.
getBank
(
bankAlignedPC
)
val
if1_baseBank
=
btbAddr
.
getBank
(
if1_
bankAlignedPC
)
val
realMask
=
Mux
(
startsAtOddBank
,
val
if1_realMask
=
Mux
(
if1_
startsAtOddBank
,
Cat
(
io
.
inMask
(
bankWidth
-
1
,
0
),
io
.
inMask
(
PredictWidth
-
1
,
bankWidth
)),
io
.
inMask
)
val
realMaskLatch
=
RegEnable
(
realMask
,
io
.
pc
.
valid
)
val
if2_realMask
=
RegEnable
(
if1_
realMask
,
io
.
pc
.
valid
)
val
i
sInNextRow
=
VecInit
((
0
until
BtbBanks
).
map
(
i
=>
Mux
(
startsAtOddBank
,
(
i
<
bankWidth
).
B
,
false
.
B
)))
val
i
f1_isInNextRow
=
VecInit
((
0
until
BtbBanks
).
map
(
i
=>
Mux
(
if1_
startsAtOddBank
,
(
i
<
bankWidth
).
B
,
false
.
B
)))
val
baseRow
=
btbAddr
.
getBankIdx
(
bankAlignedPC
)
val
if1_baseRow
=
btbAddr
.
getBankIdx
(
if1_
bankAlignedPC
)
val
nextRowStartsUp
=
baseRow
.
andR
val
if1_nextRowStartsUp
=
if1_
baseRow
.
andR
val
realRow
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
Mux
(
isInNextRow
(
b
),
(
baseRow
+
1.
U
)(
log2Up
(
nRows
)-
1
,
0
),
baseRow
)))
val
if1_realRow
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
Mux
(
if1_isInNextRow
(
b
),
(
if1_baseRow
+
1.
U
)(
log2Up
(
nRows
)-
1
,
0
),
if1_
baseRow
)))
val
realRowLatch
=
VecInit
(
realRow
.
map
(
RegEnable
(
_
,
enable
=
io
.
pc
.
valid
)))
val
if2_realRow
=
VecInit
(
if1_
realRow
.
map
(
RegEnable
(
_
,
enable
=
io
.
pc
.
valid
)))
for
(
w
<-
0
until
BtbWays
)
{
for
(
b
<-
0
until
BtbBanks
)
{
meta
(
w
)(
b
).
io
.
r
.
req
.
valid
:=
realMask
(
b
)
&&
io
.
pc
.
valid
meta
(
w
)(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
realRow
(
b
)
data
(
w
)(
b
).
io
.
r
.
req
.
valid
:=
realMask
(
b
)
&&
io
.
pc
.
valid
data
(
w
)(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
realRow
(
b
)
meta
(
w
)(
b
).
io
.
r
.
req
.
valid
:=
if1_
realMask
(
b
)
&&
io
.
pc
.
valid
meta
(
w
)(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
if1_
realRow
(
b
)
data
(
w
)(
b
).
io
.
r
.
req
.
valid
:=
if1_
realMask
(
b
)
&&
io
.
pc
.
valid
data
(
w
)(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
if1_
realRow
(
b
)
}
}
for
(
b
<-
0
to
1
)
{
edata
(
b
).
io
.
r
.
req
.
valid
:=
io
.
pc
.
valid
val
row
=
if
(
b
==
0
)
{
Mux
(
startsAtOddBank
,
realRow
(
bankWidth
),
realRow
(
0
))
}
else
{
Mux
(
startsAtOddBank
,
realRow
(
0
),
realRow
(
bankWidth
))}
val
row
=
if
(
b
==
0
)
{
Mux
(
if1_startsAtOddBank
,
if1_realRow
(
bankWidth
),
if1_
realRow
(
0
))
}
else
{
Mux
(
if1_startsAtOddBank
,
if1_realRow
(
0
),
if1_
realRow
(
bankWidth
))}
edata
(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
row
}
// Entries read from SRAM
val
metaRead
=
VecInit
((
0
until
BtbWays
).
map
(
w
=>
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
meta
(
w
)(
b
).
io
.
r
.
resp
.
data
(
0
)))))
val
dataRead
=
VecInit
((
0
until
BtbWays
).
map
(
w
=>
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
data
(
w
)(
b
).
io
.
r
.
resp
.
data
(
0
)))))
val
edataRead
=
VecInit
((
0
to
1
).
map
(
i
=>
edata
(
i
).
io
.
r
.
resp
.
data
(
0
)))
val
if2_
metaRead
=
VecInit
((
0
until
BtbWays
).
map
(
w
=>
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
meta
(
w
)(
b
).
io
.
r
.
resp
.
data
(
0
)))))
val
if2_
dataRead
=
VecInit
((
0
until
BtbWays
).
map
(
w
=>
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
data
(
w
)(
b
).
io
.
r
.
resp
.
data
(
0
)))))
val
if2_
edataRead
=
VecInit
((
0
to
1
).
map
(
i
=>
edata
(
i
).
io
.
r
.
resp
.
data
(
0
)))
val
baseBankLatch
=
btbAddr
.
getBank
(
pcLatch
)
val
startsAtOddBankLatch
=
bankInGroup
(
pcLatch
)(
0
)
val
baseTag
=
btbAddr
.
getTag
(
pcLatch
)
val
if2_baseBank
=
btbAddr
.
getBank
(
if2_pc
)
val
if2_startsAtOddBank
=
bankInGroup
(
if2_pc
)(
0
)
val
if2_baseTag
=
btbAddr
.
getTag
(
if2_pc
)
val
tagIncremented
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
RegEnable
(
isInNextRow
(
b
.
U
)
&&
nextRowStartsUp
,
io
.
pc
.
valid
)))
val
realTags
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
Mux
(
tagIncremented
(
b
),
baseTag
+
1.
U
,
baseTag
)))
val
if2_tagIncremented
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
RegEnable
(
if1_isInNextRow
(
b
.
U
)
&&
if1_
nextRowStartsUp
,
io
.
pc
.
valid
)))
val
if2_realTags
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
Mux
(
if2_tagIncremented
(
b
),
if2_baseTag
+
1.
U
,
if2_
baseTag
)))
val
totalHits
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
val
if2_
totalHits
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
VecInit
((
0
until
BtbWays
).
map
(
w
=>
// This should correspond to the real mask from last valid cycle!
metaRead
(
w
)(
b
).
tag
===
realTags
(
b
)
&&
metaRead
(
w
)(
b
).
valid
&&
realMaskLatch
(
b
)
if2_metaRead
(
w
)(
b
).
tag
===
if2_realTags
(
b
)
&&
if2_metaRead
(
w
)(
b
).
valid
&&
if2_realMask
(
b
)
))
))
val
bankHits
=
VecInit
(
totalHits
.
map
(
_
.
reduce
(
_
||
_
)))
val
bankHitWays
=
VecInit
(
totalHits
.
map
(
PriorityEncoder
(
_
)))
val
if2_bankHits
=
VecInit
(
if2_
totalHits
.
map
(
_
.
reduce
(
_
||
_
)))
val
if2_bankHitWays
=
VecInit
(
if2_
totalHits
.
map
(
PriorityEncoder
(
_
)))
def
allocWay
(
valids
:
UInt
,
meta_tags
:
UInt
,
req_tag
:
UInt
)
=
{
...
...
@@ -167,30 +167,30 @@ class BTB extends BasePredictor with BTBParams{
}
}
val
allocWays
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
allocWay
(
VecInit
(
metaRead
.
map
(
w
=>
w
(
b
).
valid
)).
asUInt
,
VecInit
(
metaRead
.
map
(
w
=>
w
(
b
).
tag
)).
asUInt
,
realTags
(
b
))))
allocWay
(
VecInit
(
if2_
metaRead
.
map
(
w
=>
w
(
b
).
valid
)).
asUInt
,
VecInit
(
if2_
metaRead
.
map
(
w
=>
w
(
b
).
tag
)).
asUInt
,
if2_
realTags
(
b
))))
val
writeWay
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
Mux
(
bankHits
(
b
),
bankHitWays
(
b
),
allocWays
(
b
))
b
=>
Mux
(
if2_bankHits
(
b
),
if2_
bankHitWays
(
b
),
allocWays
(
b
))
))
for
(
b
<-
0
until
BtbBanks
)
{
val
realBank
=
(
if
(
b
<
bankWidth
)
Mux
(
startsAtOddBankLatch
,
(
b
+
bankWidth
).
U
,
b
.
U
)
else
Mux
(
startsAtOddBankLatch
,
(
b
-
bankWidth
).
U
,
b
.
U
))
val
meta_entry
=
metaRead
(
bankHitWays
(
realBank
))(
realBank
)
val
data_entry
=
dataRead
(
bankHitWays
(
realBank
))(
realBank
)
val
edataBank
=
(
if
(
b
<
bankWidth
)
Mux
(
startsAtOddBankLatch
,
1.
U
,
0.
U
)
else
Mux
(
startsAtOddBankLatch
,
0.
U
,
1.
U
))
val
realBank
=
(
if
(
b
<
bankWidth
)
Mux
(
if2_startsAtOddBank
,
(
b
+
bankWidth
).
U
,
b
.
U
)
else
Mux
(
if2_startsAtOddBank
,
(
b
-
bankWidth
).
U
,
b
.
U
))
val
meta_entry
=
if2_metaRead
(
if2_
bankHitWays
(
realBank
))(
realBank
)
val
data_entry
=
if2_dataRead
(
if2_
bankHitWays
(
realBank
))(
realBank
)
val
edataBank
=
(
if
(
b
<
bankWidth
)
Mux
(
if2_startsAtOddBank
,
1.
U
,
0.
U
)
else
Mux
(
if2_startsAtOddBank
,
0.
U
,
1.
U
))
// Use real pc to calculate the target
io
.
resp
.
targets
(
b
)
:=
Mux
(
data_entry
.
extended
,
edataRead
(
edataBank
),
(
pcLatch
.
asSInt
+
(
b
<<
1
).
S
+
data_entry
.
offset
).
asUInt
)
io
.
resp
.
hits
(
b
)
:=
bankHits
(
realBank
)
io
.
resp
.
targets
(
b
)
:=
Mux
(
data_entry
.
extended
,
if2_edataRead
(
edataBank
),
(
if2_pc
.
asSInt
+
(
b
<<
1
).
S
+
data_entry
.
offset
).
asUInt
)
io
.
resp
.
hits
(
b
)
:=
if2_
bankHits
(
realBank
)
io
.
resp
.
types
(
b
)
:=
meta_entry
.
btbType
io
.
resp
.
isRVC
(
b
)
:=
meta_entry
.
isRVC
io
.
meta
.
writeWay
(
b
)
:=
writeWay
(
realBank
)
io
.
meta
.
hitJal
(
b
)
:=
bankHits
(
realBank
)
&&
meta_entry
.
btbType
===
BTBtype
.
J
io
.
meta
.
hitJal
(
b
)
:=
if2_
bankHits
(
realBank
)
&&
meta_entry
.
btbType
===
BTBtype
.
J
}
def
pdInfoToBTBtype
(
pd
:
PreDecodeInfo
)
=
{
...
...
@@ -244,35 +244,35 @@ class BTB extends BasePredictor with BTBParams{
XSDebug
(
"isInNextRow: "
)
(
0
until
BtbBanks
).
foreach
(
i
=>
{
XSDebug
(
false
,
true
.
B
,
"%d "
,
isInNextRow
(
i
))
XSDebug
(
false
,
true
.
B
,
"%d "
,
i
f1_i
sInNextRow
(
i
))
if
(
i
==
BtbBanks
-
1
)
{
XSDebug
(
false
,
true
.
B
,
"\n"
)
}
})
val
validLatch
=
RegNext
(
io
.
pc
.
valid
)
XSDebug
(
io
.
pc
.
valid
,
"read: pc=0x%x, baseBank=%d, realMask=%b\n"
,
bankAlignedPC
,
baseBank
,
realMask
)
XSDebug
(
io
.
pc
.
valid
,
"read: pc=0x%x, baseBank=%d, realMask=%b\n"
,
if1_bankAlignedPC
,
if1_baseBank
,
if1_
realMask
)
XSDebug
(
validLatch
,
"read_resp: pc=0x%x, readIdx=%d-------------------------------\n"
,
pcLatch
,
btbAddr
.
getIdx
(
pcLatch
))
if2_pc
,
btbAddr
.
getIdx
(
if2_pc
))
if
(
debug_verbose
)
{
for
(
i
<-
0
until
BtbBanks
){
for
(
j
<-
0
until
BtbWays
)
{
XSDebug
(
validLatch
,
"read_resp[w=%d][b=%d][r=%d] is valid(%d) mask(%d), tag=0x%x, offset=0x%x, type=%d, isExtend=%d, isRVC=%d\n"
,
j
.
U
,
i
.
U
,
realRowLatch
(
i
),
metaRead
(
j
)(
i
).
valid
,
realMaskLatch
(
i
),
metaRead
(
j
)(
i
).
tag
,
dataRead
(
j
)(
i
).
offset
,
metaRead
(
j
)(
i
).
btbType
,
dataRead
(
j
)(
i
).
extended
,
metaRead
(
j
)(
i
).
isRVC
)
j
.
U
,
i
.
U
,
if2_realRow
(
i
),
if2_metaRead
(
j
)(
i
).
valid
,
if2_realMask
(
i
),
if2_metaRead
(
j
)(
i
).
tag
,
if2_dataRead
(
j
)(
i
).
offset
,
if2_metaRead
(
j
)(
i
).
btbType
,
if2_dataRead
(
j
)(
i
).
extended
,
if2_
metaRead
(
j
)(
i
).
isRVC
)
}
}
}
// e.g: baseBank == 5 => (5, 6,..., 15, 0, 1, 2, 3, 4)
val
bankIdxInOrder
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
(
baseBankLatch
+&
b
.
U
)(
log2Up
(
BtbBanks
)-
1
,
0
)))
val
bankIdxInOrder
=
VecInit
((
0
until
BtbBanks
).
map
(
b
=>
(
if2_baseBank
+&
b
.
U
)(
log2Up
(
BtbBanks
)-
1
,
0
)))
for
(
i
<-
0
until
BtbBanks
)
{
val
idx
=
bankIdxInOrder
(
i
)
XSDebug
(
validLatch
&&
bankHits
(
bankIdxInOrder
(
i
)),
"resp(%d): bank(%d) hits, tgt=%x, isRVC=%d, type=%d\n"
,
XSDebug
(
validLatch
&&
if2_
bankHits
(
bankIdxInOrder
(
i
)),
"resp(%d): bank(%d) hits, tgt=%x, isRVC=%d, type=%d\n"
,
i
.
U
,
idx
,
io
.
resp
.
targets
(
i
),
io
.
resp
.
isRVC
(
i
),
io
.
resp
.
types
(
i
))
}
XSDebug
(
updateValid
,
"update_req: cycle=%d, pc=0x%x, target=0x%x, misPred=%d, offset=%x, extended=%d, way=%d, bank=%d, row=0x%x\n"
,
u
.
brInfo
.
debug_btb_cycle
,
u
.
pc
,
new_target
,
u
.
isMisPred
,
new_offset
,
new_extended
,
updateWay
,
updateBankIdx
,
updateRow
)
for
(
i
<-
0
until
BtbBanks
)
{
// Conflict when not hit and allocating a valid entry
val
conflict
=
metaRead
(
allocWays
(
i
))(
i
).
valid
&&
!
bankHits
(
i
)
val
conflict
=
if2_metaRead
(
allocWays
(
i
))(
i
).
valid
&&
!
if2_
bankHits
(
i
)
XSDebug
(
conflict
,
"bank(%d) is trying to allocate a valid way(%d)\n"
,
i
.
U
,
allocWays
(
i
))
// There is another circumstance when a branch is on its way to update while another
// branch chose the same way to udpate, then after the first branch is wrote in,
...
...
src/main/scala/xiangshan/frontend/Tage.scala
浏览文件 @
02328a5f
...
...
@@ -121,26 +121,26 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio
val
tageEntrySz
=
1
+
tagLen
+
TageCtrBits
val
bankAlignedPC
=
bankAligned
(
io
.
req
.
bits
.
pc
)
val
if2_
bankAlignedPC
=
bankAligned
(
io
.
req
.
bits
.
pc
)
// this bank means cache bank
val
startsAtOddBank
=
bankInGroup
(
bankAlignedPC
)(
0
)
val
if2_startsAtOddBank
=
bankInGroup
(
if2_
bankAlignedPC
)(
0
)
// use real address to index
// val unhashed_idxes = VecInit((0 until TageBanks).map(b => ((io.req.bits.pc >> 1.U) + b.U) >> log2Up(TageBanks).U))
val
unhashed_idx
=
Wire
(
Vec
(
2
,
UInt
((
log2Ceil
(
nRows
)+
tagLen
).
W
)))
val
if2_
unhashed_idx
=
Wire
(
Vec
(
2
,
UInt
((
log2Ceil
(
nRows
)+
tagLen
).
W
)))
// the first bank idx always correspond with pc
unhashed_idx
(
0
)
:=
io
.
req
.
bits
.
pc
>>
(
1
+
log2Ceil
(
TageBanks
))
if2_
unhashed_idx
(
0
)
:=
io
.
req
.
bits
.
pc
>>
(
1
+
log2Ceil
(
TageBanks
))
// when pc is at odd bank, the second bank is at the next idx
unhashed_idx
(
1
)
:=
unhashed_idx
(
0
)
+
startsAtOddBank
if2_unhashed_idx
(
1
)
:=
if2_unhashed_idx
(
0
)
+
if2_
startsAtOddBank
// val idxes_and_tags = (0 until TageBanks).map(b => compute_tag_and_hash(unhashed_idxes(b.U), io.req.bits.hist))
// val (idx, tag) = compute_tag_and_hash(unhashed_idx, io.req.bits.hist)
val
i
dxes_and_tags
=
unhashed_idx
.
map
(
compute_tag_and_hash
(
_
,
io
.
req
.
bits
.
hist
))
// val idxes = VecInit(idxes_and_tags.map(_._1))
// val tags = VecInit(idxes_and_tags.map(_._2))
// val idxes_and_tags = (0 until TageBanks).map(b => compute_tag_and_hash(
if2_
unhashed_idxes(b.U), io.req.bits.hist))
// val (idx, tag) = compute_tag_and_hash(
if2_
unhashed_idx, io.req.bits.hist)
val
i
f2_idxes_and_tags
=
if2_
unhashed_idx
.
map
(
compute_tag_and_hash
(
_
,
io
.
req
.
bits
.
hist
))
// val idxes = VecInit(i
f2_i
dxes_and_tags.map(_._1))
// val tags = VecInit(i
f2_i
dxes_and_tags.map(_._2))
val
i
dxes_latch
=
RegEnable
(
VecInit
(
idxes_and_tags
.
map
(
_
.
_1
)),
io
.
req
.
valid
)
val
tags_latch
=
RegEnable
(
VecInit
(
idxes_and_tags
.
map
(
_
.
_2
)),
io
.
req
.
valid
)
// and_
tags_latch = RegEnable(
idxes_and_tags, enable=io.req.valid)
val
i
f3_idxes
=
RegEnable
(
VecInit
(
if2_
idxes_and_tags
.
map
(
_
.
_1
)),
io
.
req
.
valid
)
val
if3_tags
=
RegEnable
(
VecInit
(
if2_
idxes_and_tags
.
map
(
_
.
_2
)),
io
.
req
.
valid
)
// and_
if3_tags = RegEnable(if2_
idxes_and_tags, enable=io.req.valid)
// val idxLatch = RegEnable(idx, enable=io.req.valid)
// val tagLatch = RegEnable(tag, enable=io.req.valid)
...
...
@@ -175,59 +175,59 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio
val
lo_us
=
List
.
fill
(
TageBanks
)(
Module
(
new
HL_Bank
(
nRows
)))
val
table
=
List
.
fill
(
TageBanks
)(
Module
(
new
SRAMTemplate
(
new
TageEntry
,
set
=
nRows
,
shouldReset
=
false
,
holdRead
=
true
,
singlePort
=
false
)))
val
hi_us_r
=
WireInit
(
0.
U
.
asTypeOf
(
Vec
(
TageBanks
,
Bool
())))
val
lo_us_r
=
WireInit
(
0.
U
.
asTypeOf
(
Vec
(
TageBanks
,
Bool
())))
val
table_r
=
WireInit
(
0.
U
.
asTypeOf
(
Vec
(
TageBanks
,
new
TageEntry
)))
val
if3_
hi_us_r
=
WireInit
(
0.
U
.
asTypeOf
(
Vec
(
TageBanks
,
Bool
())))
val
if3_
lo_us_r
=
WireInit
(
0.
U
.
asTypeOf
(
Vec
(
TageBanks
,
Bool
())))
val
if3_
table_r
=
WireInit
(
0.
U
.
asTypeOf
(
Vec
(
TageBanks
,
new
TageEntry
)))
val
baseBank
=
io
.
req
.
bits
.
pc
(
log2Up
(
TageBanks
),
1
)
val
baseBankLatch
=
RegEnable
(
baseBank
,
enable
=
io
.
req
.
valid
)
val
if2_
baseBank
=
io
.
req
.
bits
.
pc
(
log2Up
(
TageBanks
),
1
)
val
if3_baseBank
=
RegEnable
(
if2_
baseBank
,
enable
=
io
.
req
.
valid
)
val
bankIdxInOrder
=
VecInit
((
0
until
TageBanks
).
map
(
b
=>
(
baseBankLatch
+&
b
.
U
)(
log2Up
(
TageBanks
)-
1
,
0
)))
val
if3_bankIdxInOrder
=
VecInit
((
0
until
TageBanks
).
map
(
b
=>
(
if3_baseBank
+&
b
.
U
)(
log2Up
(
TageBanks
)-
1
,
0
)))
val
realMask
=
Mux
(
startsAtOddBank
,
val
if2_realMask
=
Mux
(
if2_
startsAtOddBank
,
Cat
(
io
.
req
.
bits
.
mask
(
bankWidth
-
1
,
0
),
io
.
req
.
bits
.
mask
(
PredictWidth
-
1
,
bankWidth
)),
io
.
req
.
bits
.
mask
)
val
maskLatch
=
RegEnable
(
realMask
,
enable
=
io
.
req
.
valid
)
val
if3_realMask
=
RegEnable
(
if2_
realMask
,
enable
=
io
.
req
.
valid
)
(
0
until
TageBanks
).
map
(
b
=>
{
val
idxes
=
VecInit
(
idxes_and_tags
.
map
(
_
.
_1
))
val
idx
=
(
if
(
b
<
bankWidth
)
Mux
(
startsAtOddBank
,
idxes
(
1
),
idxes
(
0
))
else
Mux
(
startsAtOddBank
,
idxes
(
0
),
idxes
(
1
)))
hi_us
(
b
).
io
.
r
.
req
.
valid
:=
io
.
req
.
valid
&&
realMask
(
b
)
val
idxes
=
VecInit
(
i
f2_i
dxes_and_tags
.
map
(
_
.
_1
))
val
idx
=
(
if
(
b
<
bankWidth
)
Mux
(
if2_
startsAtOddBank
,
idxes
(
1
),
idxes
(
0
))
else
Mux
(
if2_
startsAtOddBank
,
idxes
(
0
),
idxes
(
1
)))
hi_us
(
b
).
io
.
r
.
req
.
valid
:=
io
.
req
.
valid
&&
if2_
realMask
(
b
)
hi_us
(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
idx
lo_us
(
b
).
io
.
r
.
req
.
valid
:=
io
.
req
.
valid
&&
realMask
(
b
)
lo_us
(
b
).
io
.
r
.
req
.
valid
:=
io
.
req
.
valid
&&
if2_
realMask
(
b
)
lo_us
(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
idx
table
(
b
).
reset
:=
reset
.
asBool
table
(
b
).
io
.
r
.
req
.
valid
:=
io
.
req
.
valid
&&
realMask
(
b
)
table
(
b
).
io
.
r
.
req
.
valid
:=
io
.
req
.
valid
&&
if2_
realMask
(
b
)
table
(
b
).
io
.
r
.
req
.
bits
.
setIdx
:=
idx
hi_us_r
(
b
)
:=
hi_us
(
b
).
io
.
r
.
resp
.
data
lo_us_r
(
b
)
:=
lo_us
(
b
).
io
.
r
.
resp
.
data
table_r
(
b
)
:=
table
(
b
).
io
.
r
.
resp
.
data
(
0
)
if3_
hi_us_r
(
b
)
:=
hi_us
(
b
).
io
.
r
.
resp
.
data
if3_
lo_us_r
(
b
)
:=
lo_us
(
b
).
io
.
r
.
resp
.
data
if3_
table_r
(
b
)
:=
table
(
b
).
io
.
r
.
resp
.
data
(
0
)
}
)
val
startsAtOddBankLatch
=
RegEnable
(
startsAtOddBank
,
io
.
req
.
valid
)
val
if3_startsAtOddBank
=
RegEnable
(
if2_
startsAtOddBank
,
io
.
req
.
valid
)
val
req_rhits
=
VecInit
((
0
until
TageBanks
).
map
(
b
=>
{
val
tag
=
(
if
(
b
<
bankWidth
)
Mux
(
startsAtOddBank
,
tags_latch
(
1
),
tags_latch
(
0
))
else
Mux
(
startsAtOddBank
,
tags_latch
(
0
),
tags_latch
(
1
)))
val
bank
=
(
if
(
b
<
bankWidth
)
Mux
(
startsAtOddBankLatch
,
(
b
+
bankWidth
).
U
,
b
.
U
)
else
Mux
(
startsAtOddBankLatch
,
(
b
-
bankWidth
).
U
,
b
.
U
))
table_r
(
bank
).
valid
&&
table_r
(
bank
).
tag
===
tag
val
if3_
req_rhits
=
VecInit
((
0
until
TageBanks
).
map
(
b
=>
{
val
tag
=
(
if
(
b
<
bankWidth
)
Mux
(
if3_startsAtOddBank
,
if3_tags
(
1
),
if3_tags
(
0
))
else
Mux
(
if3_startsAtOddBank
,
if3_tags
(
0
),
if3_tags
(
1
)))
val
bank
=
(
if
(
b
<
bankWidth
)
Mux
(
if3_startsAtOddBank
,
(
b
+
bankWidth
).
U
,
b
.
U
)
else
Mux
(
if3_startsAtOddBank
,
(
b
-
bankWidth
).
U
,
b
.
U
))
if3_table_r
(
bank
).
valid
&&
if3_
table_r
(
bank
).
tag
===
tag
}))
(
0
until
TageBanks
).
map
(
b
=>
{
val
bank
=
(
if
(
b
<
bankWidth
)
Mux
(
startsAtOddBankLatch
,
(
b
+
bankWidth
).
U
,
b
.
U
)
else
Mux
(
startsAtOddBankLatch
,
(
b
-
bankWidth
).
U
,
b
.
U
))
io
.
resp
(
b
).
valid
:=
req_rhits
(
b
)
&&
maskLatch
(
b
)
io
.
resp
(
b
).
bits
.
ctr
:=
table_r
(
bank
).
ctr
io
.
resp
(
b
).
bits
.
u
:=
Cat
(
hi_us_r
(
bank
),
lo_us_r
(
bank
))
val
bank
=
(
if
(
b
<
bankWidth
)
Mux
(
if3_startsAtOddBank
,
(
b
+
bankWidth
).
U
,
b
.
U
)
else
Mux
(
if3_startsAtOddBank
,
(
b
-
bankWidth
).
U
,
b
.
U
))
io
.
resp
(
b
).
valid
:=
if3_req_rhits
(
b
)
&&
if3_realMask
(
b
)
io
.
resp
(
b
).
bits
.
ctr
:=
if3_
table_r
(
bank
).
ctr
io
.
resp
(
b
).
bits
.
u
:=
Cat
(
if3_hi_us_r
(
bank
),
if3_
lo_us_r
(
bank
))
})
...
...
@@ -292,7 +292,7 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio
// when (RegNext(wrbypass_rhit)) {
// for (b <- 0 until TageBanks) {
// when (RegNext(wrbypass_rctr_hits(b.U + baseBank))) {
// io.resp(b).bits.ctr := rhit_ctrs(bankIdxInOrder(b))
// io.resp(b).bits.ctr := rhit_ctrs(
if3_
bankIdxInOrder(b))
// }
// }
// }
...
...
@@ -335,17 +335,17 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio
val
u
=
io
.
update
val
b
=
PriorityEncoder
(
u
.
mask
)
val
ub
=
PriorityEncoder
(
u
.
uMask
)
val
idx
=
idxes_and_tags
.
map
(
_
.
_1
)
val
tag
=
idxes_and_tags
.
map
(
_
.
_2
)
val
idx
=
i
f2_i
dxes_and_tags
.
map
(
_
.
_1
)
val
tag
=
i
f2_i
dxes_and_tags
.
map
(
_
.
_2
)
XSDebug
(
io
.
req
.
valid
,
"tableReq: pc=0x%x, hist=%x, idx=(%d,%d), tag=(%x,%x), baseBank=%d, mask=%b, realMask=%b\n"
,
io
.
req
.
bits
.
pc
,
io
.
req
.
bits
.
hist
,
idx
(
0
),
idx
(
1
),
tag
(
0
),
tag
(
1
),
baseBank
,
io
.
req
.
bits
.
mask
,
realMask
)
io
.
req
.
bits
.
pc
,
io
.
req
.
bits
.
hist
,
idx
(
0
),
idx
(
1
),
tag
(
0
),
tag
(
1
),
if2_baseBank
,
io
.
req
.
bits
.
mask
,
if2_
realMask
)
for
(
i
<-
0
until
TageBanks
)
{
XSDebug
(
RegNext
(
io
.
req
.
valid
)
&&
req_rhits
(
i
),
"TageTableResp[%d]: idx=(%d,%d), hit:%d, ctr:%d, u:%d\n"
,
i
.
U
,
i
dxes_latch
(
0
),
idxes_latch
(
1
),
req_rhits
(
i
),
io
.
resp
(
i
).
bits
.
ctr
,
io
.
resp
(
i
).
bits
.
u
)
XSDebug
(
RegNext
(
io
.
req
.
valid
)
&&
if3_
req_rhits
(
i
),
"TageTableResp[%d]: idx=(%d,%d), hit:%d, ctr:%d, u:%d\n"
,
i
.
U
,
i
f3_idxes
(
0
),
if3_idxes
(
1
),
if3_
req_rhits
(
i
),
io
.
resp
(
i
).
bits
.
ctr
,
io
.
resp
(
i
).
bits
.
u
)
}
XSDebug
(
RegNext
(
io
.
req
.
valid
),
"TageTableResp: hits:%b, maskLatch is %b\n"
,
req_rhits
.
asUInt
,
maskLatch
)
XSDebug
(
RegNext
(
io
.
req
.
valid
)
&&
!
req_rhits
.
reduce
(
_
||
_
),
"TageTableResp: no hits!\n"
)
XSDebug
(
RegNext
(
io
.
req
.
valid
),
"TageTableResp: hits:%b, maskLatch is %b\n"
,
if3_req_rhits
.
asUInt
,
if3_realMask
)
XSDebug
(
RegNext
(
io
.
req
.
valid
)
&&
!
if3_
req_rhits
.
reduce
(
_
||
_
),
"TageTableResp: no hits!\n"
)
XSDebug
(
io
.
update
.
mask
.
reduce
(
_
||
_
),
"update Table: pc:%x, fetchIdx:%d, hist:%x, bank:%d, taken:%d, alloc:%d, oldCtr:%d\n"
,
u
.
pc
,
u
.
fetchIdx
,
u
.
hist
,
b
,
u
.
taken
(
b
),
u
.
alloc
(
b
),
u
.
oldCtr
(
b
))
...
...
@@ -435,12 +435,12 @@ class Tage extends BaseTage {
override
val
debug
=
true
// Keep the table responses to process in s3
val
resps
=
VecInit
(
tables
.
map
(
t
=>
RegEnable
(
t
.
io
.
resp
,
enable
=
io
.
s3Fire
))
)
val
scResps
=
VecInit
(
scTables
.
map
(
t
=>
RegEnable
(
t
.
io
.
resp
,
enable
=
io
.
s3Fire
))
)
val
if4_resps
=
RegEnable
(
VecInit
(
tables
.
map
(
t
=>
t
.
io
.
resp
)),
enable
=
io
.
s3Fire
)
val
if4_scResps
=
RegEnable
(
VecInit
(
scTables
.
map
(
t
=>
t
.
io
.
resp
)),
enable
=
io
.
s3Fire
)
// val flushLatch = RegNext(io.flush)
val
s2
_bim
=
RegEnable
(
io
.
bim
,
enable
=
io
.
pc
.
valid
)
// actually it is s2Fire
val
s3_bim
=
RegEnable
(
s2
_bim
,
enable
=
io
.
s3Fire
)
val
if3
_bim
=
RegEnable
(
io
.
bim
,
enable
=
io
.
pc
.
valid
)
// actually it is s2Fire
val
if4_bim
=
RegEnable
(
if3
_bim
,
enable
=
io
.
s3Fire
)
val
debug_pc_s2
=
RegEnable
(
io
.
pc
.
bits
,
enable
=
io
.
pc
.
valid
)
val
debug_pc_s3
=
RegEnable
(
debug_pc_s2
,
enable
=
io
.
s3Fire
)
...
...
@@ -482,37 +482,37 @@ class Tage extends BaseTage {
// access tag tables and output meta info
for
(
w
<-
0
until
TageBanks
)
{
val
tageTaken
=
WireInit
(
s3
_bim
.
ctrs
(
w
)(
1
).
asBool
)
var
altPred
=
s3
_bim
.
ctrs
(
w
)(
1
)
val
finalAltPred
=
WireInit
(
s3
_bim
.
ctrs
(
w
)(
1
))
var
provided
=
false
.
B
var
provider
=
0.
U
io
.
resp
.
takens
(
w
)
:=
s3
_bim
.
ctrs
(
w
)(
1
)
val
if4_tageTaken
=
WireInit
(
if4
_bim
.
ctrs
(
w
)(
1
).
asBool
)
var
if4_altPred
=
if4
_bim
.
ctrs
(
w
)(
1
)
val
if4_finalAltPred
=
WireInit
(
if4
_bim
.
ctrs
(
w
)(
1
))
var
if4_
provided
=
false
.
B
var
if4_
provider
=
0.
U
io
.
resp
.
takens
(
w
)
:=
if4
_bim
.
ctrs
(
w
)(
1
)
for
(
i
<-
0
until
TageNTables
)
{
val
hit
=
resps
(
i
)(
w
).
valid
val
ctr
=
resps
(
i
)(
w
).
bits
.
ctr
val
hit
=
if4_
resps
(
i
)(
w
).
valid
val
ctr
=
if4_
resps
(
i
)(
w
).
bits
.
ctr
when
(
hit
)
{
io
.
resp
.
takens
(
w
)
:=
Mux
(
ctr
===
3.
U
||
ctr
===
4.
U
,
altPred
,
ctr
(
2
))
// Use altpred on weak taken
tageTaken
:=
Mux
(
ctr
===
3.
U
||
ctr
===
4.
U
,
altPred
,
ctr
(
2
))
finalAltPred
:=
altPred
io
.
resp
.
takens
(
w
)
:=
Mux
(
ctr
===
3.
U
||
ctr
===
4.
U
,
if4_
altPred
,
ctr
(
2
))
// Use altpred on weak taken
if4_tageTaken
:=
Mux
(
ctr
===
3.
U
||
ctr
===
4.
U
,
if4_
altPred
,
ctr
(
2
))
if4_finalAltPred
:=
if4_
altPred
}
provided
=
provided
||
hit
// Once hit then provide
provider
=
Mux
(
hit
,
i
.
U
,
provider
)
// Use the last hit as provider
altPred
=
Mux
(
hit
,
ctr
(
2
),
altPred
)
// Save current pred as potential altpred
if4_provided
=
if4_
provided
||
hit
// Once hit then provide
if4_provider
=
Mux
(
hit
,
i
.
U
,
if4_
provider
)
// Use the last hit as provider
if4_altPred
=
Mux
(
hit
,
ctr
(
2
),
if4_
altPred
)
// Save current pred as potential altpred
}
io
.
resp
.
hits
(
w
)
:=
provided
io
.
meta
(
w
).
provider
.
valid
:=
provided
io
.
meta
(
w
).
provider
.
bits
:=
provider
io
.
meta
(
w
).
altDiffers
:=
finalAltPred
=/=
io
.
resp
.
takens
(
w
)
io
.
meta
(
w
).
providerU
:=
resps
(
provider
)(
w
).
bits
.
u
io
.
meta
(
w
).
providerCtr
:=
resps
(
provider
)(
w
).
bits
.
ctr
io
.
meta
(
w
).
taken
:=
tageTaken
io
.
resp
.
hits
(
w
)
:=
if4_
provided
io
.
meta
(
w
).
provider
.
valid
:=
if4_
provided
io
.
meta
(
w
).
provider
.
bits
:=
if4_
provider
io
.
meta
(
w
).
altDiffers
:=
if4_
finalAltPred
=/=
io
.
resp
.
takens
(
w
)
io
.
meta
(
w
).
providerU
:=
if4_resps
(
if4_
provider
)(
w
).
bits
.
u
io
.
meta
(
w
).
providerCtr
:=
if4_resps
(
if4_
provider
)(
w
).
bits
.
ctr
io
.
meta
(
w
).
taken
:=
if4_
tageTaken
// Create a mask fo tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val
allocatableSlots
=
(
VecInit
(
resps
.
map
(
r
=>
!
r
(
w
).
valid
&&
r
(
w
).
bits
.
u
===
0.
U
)).
asUInt
&
~(
LowerMask
(
UIntToOH
(
provider
),
TageNTables
)
&
Fill
(
TageNTables
,
provided
.
asUInt
))
val
allocatableSlots
=
(
VecInit
(
if4_
resps
.
map
(
r
=>
!
r
(
w
).
valid
&&
r
(
w
).
bits
.
u
===
0.
U
)).
asUInt
&
~(
LowerMask
(
UIntToOH
(
if4_provider
),
TageNTables
)
&
Fill
(
TageNTables
,
if4_
provided
.
asUInt
))
)
val
allocLFSR
=
LFSR64
()(
TageNTables
-
1
,
0
)
val
firstEntry
=
PriorityEncoder
(
allocatableSlots
)
...
...
@@ -525,12 +525,12 @@ class Tage extends BaseTage {
scMeta
:=
DontCare
val
scTableSums
=
VecInit
(
(
0
to
1
)
map
{
i
=>
{
// val providerCtr =
resps(
provider)(w).bits.ctr.zext()
// val providerCtr =
if4_resps(if4_
provider)(w).bits.ctr.zext()
// val pvdrCtrCentered = (((providerCtr - 4.S) << 1) + 1.S) << 3
// sum += pvdrCtrCentered
if
(
EnableSC
)
{
(
0
until
SCNTables
)
map
{
j
=>
scTables
(
j
).
getCenteredValue
(
scResps
(
j
)(
w
).
ctr
(
i
))
scTables
(
j
).
getCenteredValue
(
if4_
scResps
(
j
)(
w
).
ctr
(
i
))
}
reduce
(
_
+
_
)
// TODO: rewrite with adder tree
}
else
0.
S
...
...
@@ -539,21 +539,21 @@ class Tage extends BaseTage {
)
if
(
EnableSC
)
{
scMeta
.
tageTaken
:=
tageTaken
scMeta
.
scUsed
:=
provided
scMeta
.
scPred
:=
tageTaken
scMeta
.
tageTaken
:=
if4_
tageTaken
scMeta
.
scUsed
:=
if4_
provided
scMeta
.
scPred
:=
if4_
tageTaken
scMeta
.
sumAbs
:=
0.
U
when
(
provided
)
{
val
providerCtr
=
resps
(
provider
)(
w
).
bits
.
ctr
.
zext
()
when
(
if4_
provided
)
{
val
providerCtr
=
if4_resps
(
if4_
provider
)(
w
).
bits
.
ctr
.
zext
()
val
pvdrCtrCentered
=
((((
providerCtr
-
4.
S
)
<<
1
).
asSInt
+
1.
S
)
<<
3
).
asSInt
val
totalSum
=
scTableSums
(
tageTaken
.
asUInt
)
+
pvdrCtrCentered
val
totalSum
=
scTableSums
(
if4_
tageTaken
.
asUInt
)
+
pvdrCtrCentered
val
sumAbs
=
totalSum
.
abs
().
asUInt
val
sumBelowThreshold
=
totalSum
.
abs
.
asUInt
<
useThreshold
val
scPred
=
totalSum
>=
0.
S
scMeta
.
sumAbs
:=
sumAbs
scMeta
.
ctrs
:=
VecInit
(
scResps
.
map
(
r
=>
r
(
w
).
ctr
(
tageTaken
.
asUInt
)))
scMeta
.
ctrs
:=
VecInit
(
if4_scResps
.
map
(
r
=>
r
(
w
).
ctr
(
if4_
tageTaken
.
asUInt
)))
for
(
i
<-
0
until
SCNTables
)
{
XSDebug
(
RegNext
(
io
.
s3Fire
),
p
"SCTable(${i.U})(${w.U}): ctr:(${
scResps(i)(w).ctr(0)},${
scResps(i)(w).ctr(1)})\n"
)
XSDebug
(
RegNext
(
io
.
s3Fire
),
p
"SCTable(${i.U})(${w.U}): ctr:(${
if4_scResps(i)(w).ctr(0)},${if4_
scResps(i)(w).ctr(1)})\n"
)
}
XSDebug
(
RegNext
(
io
.
s3Fire
),
p
"SC(${w.U}): pvdCtr(${providerCtr}), pvdCentred(${pvdrCtrCentered}), totalSum(${totalSum}), abs(${sumAbs}) useThres(${useThreshold}), scPred(${scPred})\n"
)
// Use prediction from Statistical Corrector
...
...
@@ -664,7 +664,7 @@ class Tage extends BaseTage {
XSDebug
(
RegNext
(
io
.
s3Fire
),
"s3FireOnLastCycle: resp: pc=%x, hist=%x, hits=%b, takens=%b\n"
,
debug_pc_s3
,
debug_hist_s3
,
io
.
resp
.
hits
.
asUInt
,
io
.
resp
.
takens
.
asUInt
)
for
(
i
<-
0
until
TageNTables
)
{
XSDebug
(
RegNext
(
io
.
s3Fire
),
"TageTable(%d): valids:%b, resp_ctrs:%b, resp_us:%b\n"
,
i
.
U
,
VecInit
(
resps
(
i
).
map
(
_
.
valid
)).
asUInt
,
Cat
(
resps
(
i
).
map
(
_
.
bits
.
ctr
)),
Cat
(
resps
(
i
).
map
(
_
.
bits
.
u
)))
XSDebug
(
RegNext
(
io
.
s3Fire
),
"TageTable(%d): valids:%b, resp_ctrs:%b, resp_us:%b\n"
,
i
.
U
,
VecInit
(
if4_resps
(
i
).
map
(
_
.
valid
)).
asUInt
,
Cat
(
if4_resps
(
i
).
map
(
_
.
bits
.
ctr
)),
Cat
(
if4_
resps
(
i
).
map
(
_
.
bits
.
u
)))
}
XSDebug
(
io
.
update
.
valid
,
"update: pc=%x, fetchpc=%x, cycle=%d, hist=%x, taken:%d, misPred:%d, bimctr:%d, pvdr(%d):%d, altDiff:%d, pvdrU:%d, pvdrCtr:%d, alloc(%d):%d\n"
,
u
.
pc
,
u
.
pc
-
(
bri
.
fetchIdx
<<
1.
U
),
bri
.
debug_tage_cycle
,
updateHist
,
u
.
taken
,
u
.
isMisPred
,
bri
.
bimCtr
,
m
.
provider
.
valid
,
m
.
provider
.
bits
,
m
.
altDiffers
,
m
.
providerU
,
m
.
providerCtr
,
m
.
allocate
.
valid
,
m
.
allocate
.
bits
)
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录