1. 03 11月, 2012 1 次提交
    • H
      PCI/PM: Fix deadlock when unbinding device if parent in D3cold · 90b5c1d7
      Huang Ying 提交于
      If a PCI device and its parents are put into D3cold, unbinding the
      device will trigger deadlock as follow:
      
      - driver_unbind
        - device_release_driver
          - device_lock(dev)				<--- previous lock here
          - __device_release_driver
            - pm_runtime_get_sync
              ...
                - rpm_resume(dev)
                  - rpm_resume(dev->parent)
                    ...
                      - pci_pm_runtime_resume
                        ...
                        - pci_set_power_state
                          - __pci_start_power_transition
                            - pci_wakeup_bus(dev->parent->subordinate)
                              - pci_walk_bus
                                - device_lock(dev)	<--- deadlock here
      
      
      If we do not do device_lock in pci_walk_bus, we can avoid deadlock.
      Device_lock in pci_walk_bus is introduced in commit:
      d71374da, corresponding email thread
      is: https://lkml.org/lkml/2006/5/26/38.  The patch author Zhang Yanmin
      said device_lock is added to pci_walk_bus because:
      
        Some error handling functions call pci_walk_bus. For example, PCIe
        aer. Here we lock the device, so the driver wouldn't detach from the
        device, as the cb might call driver's callback function.
      
      So I fixed the deadlock as follows:
      
      - remove device_lock from pci_walk_bus
      - add device_lock into callback if callback will call driver's callback
      
      I checked pci_walk_bus users one by one, and found only PCIe aer needs
      device lock.
      Signed-off-by: NHuang Ying <ying.huang@intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      CC: stable@vger.kernel.org		# v3.6+
      CC: Zhang Yanmin <yanmin.zhang@intel.com>
      90b5c1d7
  2. 08 9月, 2012 1 次提交
  3. 25 8月, 2012 1 次提交
  4. 24 8月, 2012 1 次提交
  5. 23 8月, 2012 1 次提交
  6. 13 1月, 2012 1 次提交
  7. 22 7月, 2011 1 次提交
    • H
      PCI: PCIe AER: add aer_recover_queue · 0918472c
      Huang Ying 提交于
      In addition to native PCIe AER, now APEI (ACPI Platform Error
      Interface) GHES (Generic Hardware Error Source) can be used to report
      PCIe AER errors too.  To add support to APEI GHES PCIe AER recovery,
      aer_recover_queue is added to export the recovery function in native
      PCIe AER driver.
      
      Recoverable PCIe AER errors are reported via NMI in APEI GHES.  Then
      APEI GHES uses irq_work to delay the error processing into an IRQ
      handler.  But PCIe AER recovery can be very time-consuming, so
      aer_recover_queue, which can be used in IRQ handler, delays the real
      recovery action into the process context, that is, work queue.
      Signed-off-by: NHuang Ying <ying.huang@intel.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      0918472c
  8. 16 10月, 2010 1 次提交
  9. 25 8月, 2010 1 次提交
    • R
      PCI: PCIe: Ask BIOS for control of all native services at once · 28eb5f27
      Rafael J. Wysocki 提交于
      After commit 852972ac (ACPI: Disable
      ASPM if the platform won't provide _OSC control for PCIe) control of
      the PCIe Capability Structure is unconditionally requested by
      acpi_pci_root_add(), which in principle may cause problems to
      happen in two ways.  First, the BIOS may refuse to give control of
      the PCIe Capability Structure if it is not asked for any of the
      _OSC features depending on it at the same time.  Second, the BIOS may
      assume that control of the _OSC features depending on the PCIe
      Capability Structure will be requested in the future and may behave
      incorrectly if that doesn't happen.  For this reason, control of
      the PCIe Capability Structure should always be requested along with
      control of any other _OSC features that may depend on it (ie. PCIe
      native PME, PCIe native hot-plug, PCIe AER).
      
      Rework the PCIe port driver so that (1) it checks which native PCIe
      port services can be enabled, according to the BIOS, and (2) it
      requests control of all these services simultaneously.  In
      particular, this causes pcie_portdrv_probe() to fail if the BIOS
      refuses to grant control of the PCIe Capability Structure, which
      means that no native PCIe port services can be enabled for the PCIe
      Root Complex the given port belongs to.  If that happens, ASPM is
      disabled to avoid problems with mishandling it by the part of the
      PCIe hierarchy for which control of the PCIe Capability Structure
      has not been received.
      
      Make it possible to override this behavior using 'pcie_ports=native'
      (use the PCIe native services regardless of the BIOS response to the
      control request), or 'pcie_ports=compat' (do not use the PCIe native
      services at all).
      
      Accordingly, rework the existing PCIe port service drivers so that
      they don't request control of the services directly.
      Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      28eb5f27
  10. 31 7月, 2010 1 次提交
  11. 20 5月, 2010 1 次提交
  12. 12 5月, 2010 14 次提交
  13. 30 3月, 2010 1 次提交
    • T
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking... · 5a0e3ad6
      Tejun Heo 提交于
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
      
      percpu.h is included by sched.h and module.h and thus ends up being
      included when building most .c files.  percpu.h includes slab.h which
      in turn includes gfp.h making everything defined by the two files
      universally available and complicating inclusion dependencies.
      
      percpu.h -> slab.h dependency is about to be removed.  Prepare for
      this change by updating users of gfp and slab facilities include those
      headers directly instead of assuming availability.  As this conversion
      needs to touch large number of source files, the following script is
      used as the basis of conversion.
      
        http://userweb.kernel.org/~tj/misc/slabh-sweep.py
      
      The script does the followings.
      
      * Scan files for gfp and slab usages and update includes such that
        only the necessary includes are there.  ie. if only gfp is used,
        gfp.h, if slab is used, slab.h.
      
      * When the script inserts a new include, it looks at the include
        blocks and try to put the new include such that its order conforms
        to its surrounding.  It's put in the include block which contains
        core kernel includes, in the same order that the rest are ordered -
        alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
        doesn't seem to be any matching order.
      
      * If the script can't find a place to put a new include (mostly
        because the file doesn't have fitting include block), it prints out
        an error message indicating which .h file needs to be added to the
        file.
      
      The conversion was done in the following steps.
      
      1. The initial automatic conversion of all .c files updated slightly
         over 4000 files, deleting around 700 includes and adding ~480 gfp.h
         and ~3000 slab.h inclusions.  The script emitted errors for ~400
         files.
      
      2. Each error was manually checked.  Some didn't need the inclusion,
         some needed manual addition while adding it to implementation .h or
         embedding .c file was more appropriate for others.  This step added
         inclusions to around 150 files.
      
      3. The script was run again and the output was compared to the edits
         from #2 to make sure no file was left behind.
      
      4. Several build tests were done and a couple of problems were fixed.
         e.g. lib/decompress_*.c used malloc/free() wrappers around slab
         APIs requiring slab.h to be added manually.
      
      5. The script was run on all .h files but without automatically
         editing them as sprinkling gfp.h and slab.h inclusions around .h
         files could easily lead to inclusion dependency hell.  Most gfp.h
         inclusion directives were ignored as stuff from gfp.h was usually
         wildly available and often used in preprocessor macros.  Each
         slab.h inclusion directive was examined and added manually as
         necessary.
      
      6. percpu.h was updated not to include slab.h.
      
      7. Build test were done on the following configurations and failures
         were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
         distributed build env didn't work with gcov compiles) and a few
         more options had to be turned off depending on archs to make things
         build (like ipr on powerpc/64 which failed due to missing writeq).
      
         * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
         * powerpc and powerpc64 SMP allmodconfig
         * sparc and sparc64 SMP allmodconfig
         * ia64 SMP allmodconfig
         * s390 SMP allmodconfig
         * alpha SMP allmodconfig
         * um on x86_64 SMP allmodconfig
      
      8. percpu.h modifications were reverted so that it could be applied as
         a separate patch and serve as bisection point.
      
      Given the fact that I had only a couple of failures from tests on step
      6, I'm fairly confident about the coverage of this conversion patch.
      If there is a breakage, it's likely to be something in one of the arch
      headers which should be easily discoverable easily on most builds of
      the specific arch.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
      5a0e3ad6
  14. 17 12月, 2009 1 次提交
  15. 05 12月, 2009 3 次提交
  16. 25 11月, 2009 1 次提交
  17. 05 11月, 2009 1 次提交
    • M
      PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode · 05843961
      Matt Domsch 提交于
      Feedback from Hidetoshi Seto and Kenji Kaneshige incorporated.  This
      correctly handles PCI-X bridges, PCIe root ports and endpoints, and
      prints debug messages when invalid/reserved types are found in the
      HEST.  PCI devices not in domain/segment 0 are not represented in
      HEST, thus will be ignored.
      
      Today, the PCIe Advanced Error Reporting (AER) driver attaches itself
      to every PCIe root port for which BIOS reports it should, via ACPI
      _OSC.
      
      However, _OSC alone is insufficient for newer BIOSes.  Part of ACPI
      4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way
      for OS and BIOS to handshake over which errors for which components
      each will handle.  One table in ACPI 4.0 is the Hardware Error Source
      Table (HEST), where BIOS can define that errors for certain PCIe
      devices (or all devices), should be handled by BIOS ("Firmware First
      mode"), rather than be handled by the OS.
      
      Dell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so
      that it may manage such errors, log them to the System Event Log, and
      possibly take other actions.  The aer driver should honor this, and
      not attach itself to devices noted as such.
      
      Furthermore, Kenji Kaneshige reminded us to disallow changing the AER
      registers when respecting Firmware First mode.  Platform firmware is
      expected to manage these, and if changes to them are allowed, it could
      break that firmware's behavior.
      
      The HEST parsing code may be replaced in the future by a more
      feature-rich implementation.  This patch provides the minimum needed
      to prevent breakage until that implementation is available.
      Reviewed-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Reviewed-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NMatt Domsch <Matt_Domsch@dell.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      05843961
  18. 10 9月, 2009 7 次提交
    • H
      PCI: pcie, aer: report all error before recovery · b1c089b7
      Hidetoshi Seto 提交于
      This patch is required not to lost error records by action invoked on
      error recovery, such as slot reset etc.
      
      Following sample (real machine + dummy record injected by aer-inject)
      shows that record of 28:00.1 could not be retrieved by recovery of 28:00.0:
      
      - Before:
      
      pcieport-driver 0000:00:02.0: AER: Multiple Uncorrected (Non-Fatal) error received: id=2801
      e1000e 0000:28:00.0: PCIE Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, id=2800(Receiver ID)
      e1000e 0000:28:00.0:   device [8086:1096] error status/mask=00001000/00100000
      e1000e 0000:28:00.0:    [12] Poisoned TLP           (First)
      e1000e 0000:28:00.0:   TLP Header: 00000000 00000001 00000002 00000003
      e1000e 0000:28:00.0: broadcast error_detected message
      e1000e 0000:28:00.0: broadcast slot_reset message
      e1000e 0000:28:00.0: setting latency timer to 64
      e1000e 0000:28:00.0: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)
      e1000e 0000:28:00.0: PME# disabled
      e1000e 0000:28:00.0: PME# disabled
      e1000e 0000:28:00.1: setting latency timer to 64
      e1000e 0000:28:00.1: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)
      e1000e 0000:28:00.1: PME# disabled
      e1000e 0000:28:00.1: PME# disabled
      e1000e 0000:28:00.0: broadcast resume message
      e1000e 0000:28:00.0: AER driver successfully recovered
      e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX
      
      - After:
      
      pcieport-driver 0000:00:02.0: AER: Multiple Uncorrected (Non-Fatal) error received: id=2801
      e1000e 0000:28:00.0: PCIE Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, id=2800(Receiver ID)
      e1000e 0000:28:00.0:   device [8086:1096] error status/mask=00001000/00100000
      e1000e 0000:28:00.0:    [12] Poisoned TLP           (First)
      e1000e 0000:28:00.0:   TLP Header: 00000000 00000001 00000002 00000003
      e1000e 0000:28:00.1: PCIE Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, id=2801(Receiver ID)
      e1000e 0000:28:00.1:   device [8086:1096] error status/mask=00081000/00100000
      e1000e 0000:28:00.1:    [12] Poisoned TLP           (First)
      e1000e 0000:28:00.1:    [19] ECRC
      e1000e 0000:28:00.1:   TLP Header: 00000000 00000001 00000002 00000003
      e1000e 0000:28:00.1:   Error of this Agent(2801) is reported first
      e1000e 0000:28:00.0: broadcast error_detected message
      e1000e 0000:28:00.0: broadcast slot_reset message
      e1000e 0000:28:00.0: setting latency timer to 64
      e1000e 0000:28:00.0: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)
      e1000e 0000:28:00.0: PME# disabled
      e1000e 0000:28:00.0: PME# disabled
      e1000e 0000:28:00.1: setting latency timer to 64
      e1000e 0000:28:00.1: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)
      e1000e 0000:28:00.1: PME# disabled
      e1000e 0000:28:00.1: PME# disabled
      e1000e 0000:28:00.0: broadcast resume message
      e1000e 0000:28:00.0: AER driver successfully recovered
      e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      b1c089b7
    • H
      PCI: pcie, aer: change error print format · 79e4b89b
      Hidetoshi Seto 提交于
      Use dev_printk like format.
      
      Sample (real machine + dummy error injected by aer-inject):
      
      - Before:
      
      +------ PCI-Express Device Error ------+
      Error Severity          : Corrected
      PCIE Bus Error type     : Data Link Layer
      Bad TLP                 :
      Receiver ID             : 2800
      VendorID=8086h, DeviceID=1096h, Bus=28h, Device=00h, Function=00h
      +------ PCI-Express Device Error ------+
      Error Severity          : Corrected
      PCIE Bus Error type     : Data Link Layer
      Bad TLP                 :
      Bad DLLP                :
      Receiver ID             : 2801
      VendorID=8086h, DeviceID=1096h, Bus=28h, Device=00h, Function=01h
      Error of this Agent(2801) is reported first
      
      - After:
      
      pcieport-driver 0000:00:02.0: AER: Multiple Corrected error received: id=2801
      e1000e 0000:28:00.0: PCIE Bus Error: severity=Corrected, type=Data Link Layer, id=2800(Receiver ID)
      e1000e 0000:28:00.0:   device [8086:1096] error status/mask=00000040/00000000
      e1000e 0000:28:00.0:    [ 6] Bad TLP
      e1000e 0000:28:00.1: PCIE Bus Error: severity=Corrected, type=Data Link Layer, id=2801(Receiver ID)
      e1000e 0000:28:00.1:   device [8086:1096] error status/mask=000000c0/00000000
      e1000e 0000:28:00.1:    [ 6] Bad TLP
      e1000e 0000:28:00.1:    [ 7] Bad DLLP
      e1000e 0000:28:00.1:   Error of this Agent(2801) is reported first
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      79e4b89b
    • H
      PCI: pcie, aer: flags to bits · 273024de
      Hidetoshi Seto 提交于
      Compact struct and codes.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      273024de
    • H
      PCI: pcie, aer: report multiple/first error on a device · e7a0d92b
      Hidetoshi Seto 提交于
      Multiple bits might be set in the Uncorrectable Error Status
      register.  But aer_print_error_source() only report a error of
      the lowest bit set in the error status register.
      
      So print strings for all bits unmasked and set.
      
      And check First Error Pointer to mark the error occured first.
      This FEP is not valid when the corresponing bit of the Uncorrectable
      Error Status register is not set, or unimplemented or undefined.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      e7a0d92b
    • H
      PCI: pcie, aer: refer mask state in mask register properly · 0d90c3ac
      Hidetoshi Seto 提交于
      ERR_{,UN}CORRECTABLE_ERROR_MASK are set of error bits which linux know,
      set of PCI_ERR_COR_* and PCI_ERR_UNC_* defined in linux/pci_regs.h.
      This masks make aerdrv not to report errors of unknown bit, while aerdrv
      have ability to report such undefined errors as "Unknown Error Bit %2d".
      
      OTOH aerdrv_errprint does not have any check of setting in mask register.
      So it could report masked wrong error by finding bit in status without
      knowing that the bit is masked in the mask register.
      
      This patch changes aerdrv to use mask state in mask register propely
      instead of defined/hardcoded ERR_{,UN}CORRECTABLE_ERROR_MASK.
      This change prevents aerdrv from reporting masked error, and also enable
      reporting unknown errors.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Reviewed-by: NAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      0d90c3ac
    • H
      PCI: pcie, aer: init struct aer_err_info for reuse · 1b4ffcf8
      Hidetoshi Seto 提交于
      In case of multiple errors, struct aer_err_info would be reused among
      all reported devices.  So the info->status should be initialized before
      recycled.  Otherwise error of one device might be reported as the error
      of another device.  Also info->flags has similar problem on reporting
      TLP header.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      1b4ffcf8
    • H
      PCI: pcie, aer: checkpatch style cleanup in pcie/aer/* · c9a91883
      Hidetoshi Seto 提交于
      Before:
       drivers/pci/pcie/aer/aer_inject.c
        total: 4 errors, 4 warnings, 473 lines checked
       drivers/pci/pcie/aer/aerdrv.c
        total: 5 errors, 2 warnings, 333 lines checked
       drivers/pci/pcie/aer/aerdrv.h
        total: 1 errors, 0 warnings, 139 lines checked
       drivers/pci/pcie/aer/aerdrv_core.c
        total: 4 errors, 3 warnings, 872 lines checked
       drivers/pci/pcie/aer/aerdrv_errprint.c
        total: 12 errors, 11 warnings, 248 lines checked
      
      After:
       drivers/pci/pcie/aer/aer_inject.c
        total: 0 errors, 0 warnings, 466 lines checked
       drivers/pci/pcie/aer/aerdrv.c
        total: 0 errors, 0 warnings, 335 lines checked
       drivers/pci/pcie/aer/aerdrv.h
        total: 0 errors, 0 warnings, 139 lines checked
       drivers/pci/pcie/aer/aerdrv_core.c
        total: 0 errors, 0 warnings, 869 lines checked
       drivers/pci/pcie/aer/aerdrv_errprint.c
        total: 0 errors, 10 warnings, 247 lines checked
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Reviewed-by: NAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      c9a91883
  19. 17 6月, 2009 1 次提交