add Vango V85xx first version

bsp/Vango_V85xx/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+    
+# you can change the RTT_ROOT default: "rt-thread"
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_SERIES_GD32F1
+    bool
+    default y
+
+config SOC_GD32103C
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select SOC_SERIES_GD32F1
+    default y
+
+menu "On-chip Peripheral Drivers"
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "using uart0"
+                default n
+            config BSP_USING_UART1
+                bool "using uart1"
+                default n
+            config BSP_USING_UART2
+                bool "using uart2"
+                default y
+            config BSP_USING_UART3
+                bool "using uart3"
+                default n
+            config BSP_USING_UART4
+                bool "using uart4"
+                default n
+        endif
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC0
+                bool "using adc0"
+                default n
+            config BSP_USING_ADC1
+                bool "using adc1"
+                default n
+        endif
+    menuconfig BSP_USING_HWTIMER
+        bool "Enable hwtimer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_HWTIMER
+            config BSP_USING_HWTIMER0
+                bool "using hwtimer0"
+                default n
+            config BSP_USING_HWTIMER1
+                bool "using hwtimer1"
+                default n
+            config BSP_USING_HWTIMER2
+                bool "using hwtimer2"
+                default n
+            config BSP_USING_HWTIMER3
+                bool "using hwtimer3"
+                default n
+            config BSP_USING_HWTIMER4
+                bool "using hwtimer4"
+                default n
+            config BSP_USING_HWTIMER5
+                bool "using hwtimer5"
+                default n
+            config BSP_USING_HWTIMER6
+                bool "using hwtimer6"
+                default n
+            config BSP_USING_HWTIMER7
+                bool "using hwtimer7"
+                default n
+        endif
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
+    config BSP_USING_RTC
+        bool "using internal rtc"
+        default n
+        select RT_USING_RTC
+
+endmenu

bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/gd32f10x_conf.h

+/**
+  ******************************************************************************
+  * @brief   Configuration file.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GD32F10X_CONF_H
+#define __GD32F10X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "lib_ana.h"
+#include "lib_adc.h"
+#include "lib_adc_tiny.h"
+#include "lib_clk.h"
+#include "lib_comp.h"
+#include "lib_crypt.h"
+#include "lib_dma.h"
+#include "lib_flash.h"
+#include "lib_gpio.h"
+#include "lib_i2c.h"
+#include "lib_iso7816.h"
+#include "lib_lcd.h"
+#include "lib_misc.h"
+#include "lib_pmu.h"
+#include "lib_pwm.h"
+#include "lib_rtc.h"
+#include "lib_spi.h"
+#include "lib_tmr.h"
+#include "lib_u32k.h"
+#include "lib_uart.h"
+#include "lib_version.h"
+#include "lib_wdt.h"
+#include "lib_LoadNVR.h"
+#include "lib_CodeRAM.h"
+#include "lib_cortex.h"
+
+#endif /* __GD32F10X_CONF_H */
+

bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h

+/**
+  ******************************************************************************
+  * @file    lib_CodeRAM.h 
+  * @author  Application Team
+  * @version V4.4.0
+  * @date    2019-01-18
+  * @brief   Codes executed in SRAM.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __LIB_CODERAM_H
+#define __LIB_CODERAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "target.h"   
+
+#ifndef __GNUC__
+
+#ifdef __ICCARM__          /* EWARM */
+  #define __RAM_FUNC       __ramfunc
+#endif
+
+#ifdef __CC_ARM            /* MDK-ARM */
+  #define __RAM_FUNC       __attribute__((used))
+#endif
+
+/* Exported Functions ------------------------------------------------------- */
+
+__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void);
+
+#endif /* __GNUC__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_CODERAM_H */
+
+/*********************************** END OF FILE ******************************/

bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h

+/**
+  ******************************************************************************
+  * @file    lib_LoadNVR.h 
+  * @author  Application Team
+  * @version V4.7.0
+  * @date    2019-12-12
+  * @brief   Load information from NVR.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __LIB_LOADNVR_H
+#define __LIB_LOADNVR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "target.h"
+
+/* BAT measure result */
+typedef struct
+{
+  float  BATRESResult;  // BAT Resistor division Measure Result 
+  float  BATCAPResult;  // BATRTC Cap division Measure Result 
+} NVR_BATMEARES;
+
+/* Power Measure Result */
+typedef struct
+{
+  uint32_t  AVCCMEAResult;  // LDO33 Measure Result
+  uint32_t  DVCCMEAResult;  // LDO15 Measure Result
+  uint32_t  BGPMEAResult;    // BGP Measure Result
+  uint32_t  RCLMEAResult;    // RCL Measure Result
+  uint32_t  RCHMEAResult;    // RCH Measure Result
+} NVR_MISCGain;
+
+/* Chip ID */
+typedef struct
+{
+  uint32_t  ChipID0;        // ID word 0
+  uint32_t  ChipID1;        // ID word 1
+} NVR_CHIPID;
+
+/* Temperature information */
+typedef struct
+{
+  float  TempOffset; 
+} NVR_TEMPINFO;
+
+/* LCD information */
+typedef struct
+{
+  uint32_t  MEALCDLDO;     // Measure LCD LDO pre trim value
+  uint32_t  MEALCDVol;     // VLCD setting
+} NVR_LCDINFO;
+
+/* RTC(temp) information */
+typedef struct
+{
+  int16_t RTCTempP0; //P0
+  int16_t RTCTempP1; //P1
+  int32_t RTCTempP2; //P2
+  int16_t RTCTempP4; //P4
+  int16_t RTCTempP5; //P5
+  int16_t RTCTempP6; //P6
+  int16_t RTCTempP7; //P7 
+  int16_t RTCTempK1; //K1
+  int16_t RTCTempK2; //K2
+  int16_t RTCTempK3; //K3
+  int16_t RTCTempK4; //K4
+  int16_t RTCTempK5; //K5
+  int16_t RTCACTI;      //Center temperature
+  uint32_t RTCACKTemp;  //section X temperature
+  int16_t RTCTempDelta; //Temperature delta
+  uint32_t RTCACF200;   //RTC_ACF200
+  uint32_t APBClock;    //APB clock
+} NVR_RTCINFO;
+
+/* ADC Voltage Parameters */
+typedef struct
+{
+  float aParameter;
+  float bParameter;
+} NVR_ADCVOLPARA;
+//Mode
+#define NVR_3V_EXTERNAL_NODIV    (0x000UL)    // Power supply: 3.3V;    Channel: External;    Divider modeL: None
+#define NVR_3V_EXTERNAL_RESDIV   (0x001UL)    // Power supply: 3.3V;    Channel: External;    Divider modeL: Resistive
+#define NVR_3V_EXTERNAL_CAPDIV   (0x002UL)    // Power supply: 3.3V;    Channel: External;    Divider modeL: Capacitive
+#define NVR_3V_VDD_RESDIV        (0x003UL)    // Power supply: 3.3V;    Channel: VDD;         Divider modeL: Resistive
+#define NVR_3V_VDD_CAPDIV        (0x004UL)    // Power supply: 3.3V;    Channel: VDD;         Divider modeL: Capacitive
+#define NVR_3V_BATRTC_RESDIV     (0x005UL)    // Power supply: 3.3V;    Channel: BATRTC;      Divider modeL: Resistive
+#define NVR_3V_BATRTC_CAPDIV     (0x006UL)    // Power supply: 3.3V;    Channel: BATRTC;      Divider modeL: Capacitive
+#define NVR_5V_EXTERNAL_NODIV    (0x100UL)    // Power supply: 5V;      Channel: External;    Divider modeL: None
+#define NVR_5V_EXTERNAL_RESDIV   (0x101UL)    // Power supply: 5V;      Channel: External;    Divider modeL: Resistive
+#define NVR_5V_EXTERNAL_CAPDIV   (0x102UL)    // Power supply: 5V;      Channel: External;    Divider modeL: Capacitive
+#define NVR_5V_VDD_RESDIV        (0x103UL)    // Power supply: 5V;      Channel: VDD;         Divider modeL: Resistive
+#define NVR_5V_VDD_CAPDIV        (0x104UL)    // Power supply: 5V;      Channel: VDD;         Divider modeL: Capacitive
+#define NVR_5V_BATRTC_RESDIV     (0x105UL)    // Power supply: 5V;      Channel: BATRTC;      Divider modeL: Resistive
+#define NVR_5V_BATRTC_CAPDIV     (0x106UL)    // Power supply: 5V;      Channel: BATRTC;      Divider modeL: Capacitive
+#define IS_NVR_ADCVOL_MODE(__MODE__)  (((__MODE__) == NVR_3V_EXTERNAL_NODIV)   ||\
+                                       ((__MODE__) == NVR_3V_EXTERNAL_RESDIV)  ||\
+                                       ((__MODE__) == NVR_3V_EXTERNAL_CAPDIV)  ||\
+                                       ((__MODE__) == NVR_3V_VDD_RESDIV)       ||\
+                                       ((__MODE__) == NVR_3V_VDD_CAPDIV)       ||\
+                                       ((__MODE__) == NVR_3V_BATRTC_RESDIV)    ||\
+                                       ((__MODE__) == NVR_3V_BATRTC_CAPDIV)    ||\
+                                       ((__MODE__) == NVR_5V_EXTERNAL_NODIV)   ||\
+                                       ((__MODE__) == NVR_5V_EXTERNAL_RESDIV)  ||\
+                                       ((__MODE__) == NVR_5V_EXTERNAL_CAPDIV)  ||\
+                                       ((__MODE__) == NVR_5V_VDD_RESDIV)       ||\
+                                       ((__MODE__) == NVR_5V_VDD_CAPDIV)       ||\
+                                       ((__MODE__) == NVR_5V_BATRTC_RESDIV)    ||\
+                                       ((__MODE__) == NVR_5V_BATRTC_CAPDIV))
+
+/********** NVR Address **********/
+//ADC Voltage Parameters
+#define NVR_3VPARA_BASEADDR1          (__IO uint32_t *)(0x40400)
+#define NVR_3VPARA_BASEADDR2          (__IO uint32_t *)(0x40440)
+#define NVR_5VPARA_BASEADDR1          (__IO uint32_t *)(0x40480)
+#define NVR_5VPARA_BASEADDR2          (__IO uint32_t *)(0x404C0)
+//RTC DATA
+//P4
+#define NVR_RTC1_P4                   (__IO uint32_t *)(0x40800)
+#define NVR_RTC1_P4_CHKSUM            (__IO uint32_t *)(0x40804)
+#define NVR_RTC2_P4                   (__IO uint32_t *)(0x40808)
+#define NVR_RTC2_P4_CHKSUM            (__IO uint32_t *)(0x4080C)
+//ACK1~ACK5
+#define NVR_RTC1_ACK1                 (__IO uint32_t *)(0x40810)
+#define NVR_RTC1_ACK2                 (__IO uint32_t *)(0x40814)
+#define NVR_RTC1_ACK3                 (__IO uint32_t *)(0x40818)
+#define NVR_RTC1_ACK4                 (__IO uint32_t *)(0x4081C)
+#define NVR_RTC1_ACK5                 (__IO uint32_t *)(0x40820)
+#define NVR_RTC1_ACK_CHKSUM           (__IO uint32_t *)(0x40824)
+#define NVR_RTC2_ACK1                 (__IO uint32_t *)(0x40828)
+#define NVR_RTC2_ACK2                 (__IO uint32_t *)(0x4082C)
+#define NVR_RTC2_ACK3                 (__IO uint32_t *)(0x40830)
+#define NVR_RTC2_ACK4                 (__IO uint32_t *)(0x40834)
+#define NVR_RTC2_ACK5                 (__IO uint32_t *)(0x40838)
+#define NVR_RTC2_ACK_CHKSUM           (__IO uint32_t *)(0x4083C)
+//ACTI
+#define NVR_RTC1_ACTI                 (__IO uint32_t *)(0x40840)
+#define NVR_RTC1_ACTI_CHKSUM          (__IO uint32_t *)(0x40844)
+#define NVR_RTC2_ACTI                 (__IO uint32_t *)(0x40848)
+#define NVR_RTC2_ACTI_CHKSUM          (__IO uint32_t *)(0x4084C)
+//ACKTEMP
+#define NVR_RTC1_ACKTEMP              (__IO uint32_t *)(0x40850)
+#define NVR_RTC1_ACKTEMP_CHKSUM       (__IO uint32_t *)(0x40854)
+#define NVR_RTC2_ACKTEMP              (__IO uint32_t *)(0x40858)
+#define NVR_RTC2_ACKTEMP_CHKSUM       (__IO uint32_t *)(0x4085C)
+//Analog trim data
+#define NVR_ANA_TRIMDATA1             (__IO uint32_t *)(0x40DC0)
+#define NVR_ANA_OPREG1                (__IO uint32_t *)(0x40DC4)
+#define NVR_ANA_KEYREG1               (__IO uint32_t *)(0x40DC8)
+#define NVR_ANA_CHECKSUM1             (__IO uint32_t *)(0x40DCC)
+#define NVR_ANA_TRIMDATA2             (__IO uint32_t *)(0x40DD0)
+#define NVR_ANA_OPREG2                (__IO uint32_t *)(0x40DD4)
+#define NVR_ANA_KEYREG2               (__IO uint32_t *)(0x40DD8)
+#define NVR_ANA_CHECKSUM2             (__IO uint32_t *)(0x40DDC)
+//BAT Measure Result 
+#define NVR_BAT_R1                    (__IO uint32_t *)(0x40CE0)
+#define NVR_BAT_C1                    (__IO uint32_t *)(0x40CE4)
+#define NVR_BATMEA_CHECHSUM1          (__IO uint32_t *)(0x40CE8)
+#define NVR_BAT_R2                    (__IO uint32_t *)(0x40CF0)
+#define NVR_BAT_C2                    (__IO uint32_t *)(0x40CF4)
+#define NVR_BATMEA_CHECHSUM2          (__IO uint32_t *)(0x40CF8)
+//RTC AutoCal Px pramameters
+#define NVR_RTC1_P1_P0                (__IO uint32_t *)(0x40D00)
+#define NVR_RTC1_P2                   (__IO uint32_t *)(0x40D04)
+#define NVR_RTC1_P5_P4                (__IO uint32_t *)(0x40D08)
+#define NVR_RTC1_P7_P6                (__IO uint32_t *)(0x40D0C)
+#define NVR_RTC1_PCHECHSUM            (__IO uint32_t *)(0x40D10)
+#define NVR_RTC2_P1_P0                (__IO uint32_t *)(0x40D14)
+#define NVR_RTC2_P2                   (__IO uint32_t *)(0x40D18)
+#define NVR_RTC2_P5_P4                (__IO uint32_t *)(0x40D1C)
+#define NVR_RTC2_P7_P6                (__IO uint32_t *)(0x40D20)
+#define NVR_RTC2_PCHECHSUM            (__IO uint32_t *)(0x40D24)
+//Power Measure Result
+#define NVR_DVCC_MEA1                 (__IO uint32_t *)(0x40D28)
+#define NVR_AVCC_MEA1                 (__IO uint32_t *)(0x40D2C)
+#define NVR_BGP_MEA1                  (__IO uint32_t *)(0x40D30)
+#define NVR_RCL_MEA1                  (__IO uint32_t *)(0x40D34)
+#define NVR_RCH_MEA1                  (__IO uint32_t *)(0x40D38)
+#define NVR_PWR_CHECKSUM1             (__IO uint32_t *)(0x40D3C)
+#define NVR_DVCC_MEA2                 (__IO uint32_t *)(0x40D40)
+#define NVR_AVCC_MEA2                 (__IO uint32_t *)(0x40D44)
+#define NVR_BGP_MEA2                  (__IO uint32_t *)(0x40D48)
+#define NVR_RCL_MEA2                  (__IO uint32_t *)(0x40D4C)
+#define NVR_RCH_MEA2                  (__IO uint32_t *)(0x40D50)
+#define NVR_PWR_CHECKSUM2             (__IO uint32_t *)(0x40D54)
+//Chip ID
+#define NVR_CHIP1_ID0                 (__IO uint32_t *)(0x40D58)
+#define NVR_CHIP1_ID1                 (__IO uint32_t *)(0x40D5C)
+#define NVR_CHIP1_CHECKSUM            (__IO uint32_t *)(0x40D60)
+#define NVR_CHIP2_ID0                 (__IO uint32_t *)(0x40D64)
+#define NVR_CHIP2_ID1                 (__IO uint32_t *)(0x40D68)
+#define NVR_CHIP2_CHECKSUM            (__IO uint32_t *)(0x40D6C)
+//Temperature information
+#define NVR_REALTEMP1                 (__IO uint32_t *)(0x40D70)
+#define NVR_MEATEMP1                  (__IO uint32_t *)(0x40D74)
+#define NVR_TEMP_CHECKSUM1            (__IO uint32_t *)(0x40D78)
+#define NVR_REALTEMP2                 (__IO uint32_t *)(0x40D7C)
+#define NVR_MEATEMP2                  (__IO uint32_t *)(0x40D80)
+#define NVR_TEMP_CHECKSUM2            (__IO uint32_t *)(0x40D84)
+//LCD Information
+#define NVR_LCD_LDO1                  (__IO uint32_t *)(0x40D90)
+#define NVR_LCD_VOL1                  (__IO uint32_t *)(0x40D94)
+#define NVR_LCD_CHECKSUM1             (__IO uint32_t *)(0x40D98)
+#define NVR_LCD_LDO2                  (__IO uint32_t *)(0x40D9C)
+#define NVR_LCD_VOL2                  (__IO uint32_t *)(0x40DA0)
+#define NVR_LCD_CHECKSUM2             (__IO uint32_t *)(0x40DA4)
+
+
+uint32_t NVR_LoadANADataManual(void);
+uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter);
+uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult);
+uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData);
+uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult);
+uint32_t NVR_GetChipID(NVR_CHIPID *ChipID);
+uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_LOADNVR_H */
+
+/*********************************** END OF FILE ******************************/

bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h

+/**
+  ******************************************************************************
+  * @file    lib_conf.c 
+  * @author  Application Team
+  * @version V4.4.0
+  * @date    2018-09-27
+  * @brief   Dirver configuration.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __LIB_CONF_H
+#define __LIB_CONF_H
+
+/* ########################## Assert Selection ############################## */
+
+//#define ASSERT_NDEBUG    1
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+#include "lib_ana.h"
+#include "lib_adc.h"
+#include "lib_adc_tiny.h"
+#include "lib_clk.h"
+#include "lib_comp.h"
+#include "lib_crypt.h"
+#include "lib_dma.h"
+#include "lib_flash.h"
+#include "lib_gpio.h"
+#include "lib_i2c.h"
+#include "lib_iso7816.h"
+#include "lib_lcd.h"
+#include "lib_misc.h"
+#include "lib_pmu.h"
+#include "lib_pwm.h"
+#include "lib_rtc.h"
+#include "lib_spi.h"
+#include "lib_tmr.h"
+#include "lib_u32k.h"
+#include "lib_uart.h"
+#include "lib_version.h"
+#include "lib_wdt.h"
+#include "lib_LoadNVR.h"
+#include "lib_CodeRAM.h"
+#include "lib_cortex.h"
+
+/* Exported macro ------------------------------------------------------------*/
+#ifndef  ASSERT_NDEBUG
+  #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_errhandler(uint8_t* file, uint32_t line);
+#else
+  #define assert_parameters(expr) ((void)0U)
+#endif /* ASSERT_NDEBUG */ 
+
+#endif
+
+/*********************************** END OF FILE ******************************/

bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h

+/**
+  ******************************************************************************
+  * @file    lib_Cortex.h 
+  * @author  Application Team
+  * @version V4.4.0
+  * @date    2018-09-27
+  * @brief   Cortex module driver.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __LIB_CORTEX_H
+#define __LIB_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "target.h"   
+
+
+#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ)  ((IRQ) >= 0x00)
+   
+#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x4)
+   
+/* Exported Functions ------------------------------------------------------- */
+void     CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority);
+   
+void     CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn);
+void     CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn);
+uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void     CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void     CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn);
+void     CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority);
+void     CORTEX_NVIC_SystemReset(void);
+uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIB_CORTEX_H */
+
+/*********************************** END OF FILE ******************************/

bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h

+/**
+  ******************************************************************************
+  * @file    system_target.c 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   system source file.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+#ifndef __SYSTEM_TARGET_H
+#define __SYSTEM_TARGET_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "type_def.h"
+
+#define NVR_REGINFOCOUNT1        (0x80400)
+#define NVR_REGINFOBAKOFFSET     (0x100)
+
+/* ########################### System Configuration ######################### */         
+
+extern void SystemInit(void);
+extern void SystemUpdate(void);
+
+
+#ifdef USE_TARGET_DRIVER
+    #include "lib_conf.h"
+#endif /* USE_TARGET_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_TARGET_H */
+
+/*********************************** END OF FILE ******************************/

bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h

+/**
+  ******************************************************************************
+  * @file    type_def.h 
+  * @author  Application Team
+  * @version V4.4.0
+  * @date    2018-09-27
+  * @brief   Typedef file
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+
+#ifndef __TYPE_DEF_H
+#define __TYPE_DEF_H
+
+#define ENABLE  1
+#define DISABLE 0
+#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE))
+
+#define BIT0			0x00000001
+#define BIT1			0x00000002
+#define BIT2			0x00000004
+#define BIT3			0x00000008
+#define BIT4			0x00000010
+#define BIT5			0x00000020
+#define BIT6			0x00000040
+#define BIT7			0x00000080
+#define BIT8			0x00000100
+#define BIT9			0x00000200
+#define BIT10			0x00000400
+#define BIT11			0x00000800
+#define BIT12			0x00001000
+#define BIT13			0x00002000
+#define BIT14			0x00004000
+#define BIT15			0x00008000
+#define BIT16			0x00010000
+#define BIT17			0x00020000
+#define BIT18			0x00040000
+#define BIT19			0x00080000
+#define BIT20			0x00100000
+#define BIT21			0x00200000
+#define BIT22			0x00400000
+#define BIT23			0x00800000
+#define BIT24			0x01000000
+#define BIT25			0x02000000
+#define BIT26			0x04000000
+#define BIT27			0x08000000
+#define BIT28			0x10000000
+#define BIT29			0x20000000
+#define BIT30			0x40000000
+#define BIT31			0x80000000
+
+#if  defined ( __GNUC__ )
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+  * @brief  __NOINLINE definition
+  */
+#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
+/* ARM & GNUCompiler
+   ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#endif /* __TYPE_DEF_H */
+
+/*********************************** END OF FILE ******************************/

bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S

+;/**
+;* @file    startup_target.s
+;* @author  Application Team
+;* @version V1.1.0
+;* @date    2019-10-28
+;* @brief   Target Devices vector table.
+;******************************************************************************/
+
+  .syntax unified
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.equ __CHIPINITIAL, 1
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/*************************************************************************
+* Chip init.
+*      1. Load flash configuration
+*      2. Load ANA_REG(B/C/D/E) information
+*      3. Load ANA_REG10 information
+
+**************************************************************************/
+.if (__CHIPINITIAL != 0)
+  .section .chipinit_section.__CHIP_INIT
+__CHIP_INIT:
+CONFIG1_START:
+        /*-------------------------------*/
+        /* 1. Load flash configuration */
+        /* Unlock flash */
+        LDR     R0, =0x000FFFE0
+        LDR     R1, =0x55AAAA55
+        STR     R1, [R0]
+        /* Load configure word 0 to 7
+           Compare bit[7:0] */
+        LDR     R0, =0x00080E00
+        LDR     R1, =0x20
+        LDR     R2, =0x000FFFE8
+        LDR     R3, =0x000FFFF0
+        LDR     R4, =0x0
+        LDR     R7, =0x0FF
+FLASH_CONF_START_1:
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+        BNE     FLASH_CONF_AGAIN_1
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_1
+        B       FLASH_CONF_START_1
+FLASH_CONF_AGAIN_1:
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+FLASH_CONF_WHILELOOP_1:
+        BNE     FLASH_CONF_WHILELOOP_1
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_1
+        B       FLASH_CONF_START_1
+FLASH_CONF_END_1:
+        /* Load configure word 8 to 11
+           Compare bit 31,24,23:16,8,7:0 */
+        LDR     R1, =0x30
+        LDR     R7, =0x81FF81FF
+FLASH_CONF_START_2:
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+        BNE     FLASH_CONF_AGAIN_1
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_2
+        B       FLASH_CONF_START_2
+FLASH_CONF_AGAIN_2:
+        LDR     R5, [R0]
+        STR     R4, [R2]
+        STR     R5, [R3]
+        LDR     R6, [R3]
+        ANDS    R5, R7
+        ANDS    R6, R7
+        CMP     R5, R6
+FLASH_CONF_WHILELOOP_2:
+        BNE     FLASH_CONF_WHILELOOP_2
+        ADDS    R4, #4
+        ADDS    R0, #4
+        CMP     R1, R4
+        BEQ     FLASH_CONF_END_2
+        B       FLASH_CONF_START_2
+FLASH_CONF_END_2:
+        /* Lock flash */
+        LDR     R0, =0x000FFFE0
+        LDR     R1, =0x0
+        STR     R1, [R0]
+        /*-------------------------------*/
+        /* 2. Load ANA_REG(B/C/D/E) information */
+CONFIG2_START:
+        LDR     R4, =0x4001422C
+        LDR     R5, =0x40014230
+        LDR     R6, =0x40014234
+        LDR     R7, =0x40014238
+        LDR     R0, =0x80DC0
+        LDR     R0, [R0]
+        LDR     R1, =0x80DC4
+        LDR     R1, [R1]
+        ADDS    R2, R0, R1
+        ADDS    R2, #0x0FFFFFFFF
+        MVNS    R2, R2
+        LDR     R3, =0x80DCC
+        LDR     R3, [R3]
+        CMP     R3, R2
+        BEQ     ANADAT_CHECKSUM1_OK
+        B       ANADAT_CHECKSUM1_ERR
+ANADAT_CHECKSUM1_OK:
+        /* ANA_REGB */
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R4]
+        /* ANA_REGC */
+        LDR     R1, =0x0FF00
+        ANDS    R1, R0
+        LSRS    R1, R1, #8
+        STR     R1, [R5]
+        /* ANA_REGD */
+        LDR     R1, =0x0FF0000
+        ANDS    R1, R0
+        LSRS    R1, R1, #16
+        STR     R1, [R6]
+        /* ANA_REGE */
+        LDR     R1, =0x0FF000000
+        ANDS    R1, R0
+        LSRS    R1, R1, #24
+        STR     R1, [R7]
+        B       CONFIG3_START
+ANADAT_CHECKSUM1_ERR:
+        LDR     R0, =0x80DD0
+        LDR     R0, [R0]
+        LDR     R1, =0x80DD4
+        LDR     R1, [R1]
+        ADDS    R2, R0, R1
+        ADDS    R2, #0x0FFFFFFFF
+        MVNS    R2, R2
+        LDR     R3, =0x80DDC
+        LDR     R3, [R3]
+        CMP     R3, R2
+        BEQ     ANADAT_CHECKSUM2_OK
+        B       ANADAT_CHECKSUM2_ERR
+ANADAT_CHECKSUM2_OK:
+        /* ANA_REGB */
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R4]
+        /* ANA_REGC */
+        LDR     R1, =0x0FF00
+        ANDS    R1, R0
+        LSRS    R1, R1, #8
+        STR     R1, [R5]
+        /* ANA_REGD */
+        LDR     R1, =0x0FF0000
+        ANDS    R1, R0
+        LSRS    R1, R1, #16
+        STR     R1, [R6]
+        /* ANA_REGE */
+        LDR     R1, =0x0FF000000
+        ANDS    R1, R0
+        LSRS    R1, R1, #24
+        STR     R1, [R7]
+        B       CONFIG3_START
+ANADAT_CHECKSUM2_ERR:
+        B       ANADAT_CHECKSUM2_ERR
+        /*-------------------------------*/
+        /* 3. Load ANA_REG10 information */
+CONFIG3_START:
+        LDR     R7, =0x40014240
+        LDR     R0, =0x80DE0
+        LDR     R0, [R0]
+        LDR     R1, =0x80DE4
+        LDR     R1, [R1]
+        MVNS    R1, R1
+        CMP     R1, R0
+        BEQ     ANADAT10_CHECKSUM1_OK
+        B       ANADAT10_CHECKSUM1_ERR
+ANADAT10_CHECKSUM1_OK:
+        /* ANA_REG10 */
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R7]
+        BX      LR
+ANADAT10_CHECKSUM1_ERR:
+        LDR     R0, =0x80DE8
+        LDR     R0, [R0]
+        LDR     R1, =0x80DEC
+        LDR     R1, [R1]
+        MVNS    R1, R1
+        CMP     R1, R0
+        BEQ     ANADAT10_CHECKSUM2_OK
+        B       ANADAT10_CHECKSUM2_ERR
+ANADAT10_CHECKSUM2_OK:
+        /* ANA_REG10 */
+        LDR     R1, =0x0FF
+        ANDS    R1, R0
+        STR     R1, [R7]
+        BX      LR
+ANADAT10_CHECKSUM2_ERR:
+        B       ANADAT10_CHECKSUM2_ERR
+.size __CHIP_INIT, .-__CHIP_INIT
+.endif
+
+
+.if (__CHIPINITIAL != 0)
+  .global __CHIP_INIT
+  .section .chipinit_section.Reset_Handler
+.else
+  .section .text.Reset_Handler
+.endif
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+.if (__CHIPINITIAL != 0)
+/* Chip Initiliazation */  
+  bl    __CHIP_INIT
+/* System Initiliazation */
+  bl SystemInit
+.endif
+
+/* set stack pointer */
+  ldr   r0, =_estack
+  mov   sp, r0
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  0
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word  PMU_IRQHandler                    /*  0: PMU       */
+  .word  RTC_IRQHandler                    /*  1: RTC       */
+  .word  U32K0_IRQHandler                  /*  2: U32K0     */
+  .word  U32K1_IRQHandler                  /*  3: U32K1     */
+  .word  I2C_IRQHandler                    /*  4: I2C       */
+  .word  SPI1_IRQHandler                   /*  5: SPI1      */
+  .word  UART0_IRQHandler                  /*  6: UART0     */
+  .word  UART1_IRQHandler                  /*  7: UART1     */
+  .word  UART2_IRQHandler                  /*  8: UART2     */
+  .word  UART3_IRQHandler                  /*  9: UART3     */
+  .word  UART4_IRQHandler                  /* 10: UART4     */
+  .word  UART5_IRQHandler                  /* 11: UART5     */
+  .word  ISO78160_IRQHandler               /* 12: ISO78160  */
+  .word  ISO78161_IRQHandler               /* 13: ISO78161  */
+  .word  TMR0_IRQHandler                   /* 14: TMR0      */
+  .word  TMR1_IRQHandler                   /* 15: TMR1      */
+  .word  TMR2_IRQHandler                   /* 16: TMR2      */
+  .word  TMR3_IRQHandler                   /* 17: TMR3      */
+  .word  PWM0_IRQHandler                   /* 18: PWM0      */
+  .word  PWM1_IRQHandler                   /* 19: PWM1      */
+  .word  PWM2_IRQHandler                   /* 20: PWM2      */
+  .word  PWM3_IRQHandler                   /* 21: PWM3      */
+  .word  DMA_IRQHandler                    /* 22: DMA       */
+  .word  FLASH_IRQHandler                  /* 23: FLASH     */
+  .word  ANA_IRQHandler                    /* 24: ANA       */
+  .word  0                                 /* 25: Reserved  */
+  .word  0                                 /* 26: Reserved  */
+  .word  SPI2_IRQHandler                   /* 27: SPI2      */
+  .word  SPI3_IRQHandler                   /* 28: SPI3      */
+  .word  0                                 /* 29: Reserved  */
+  .word  0                                 /* 30: Reserved  */
+  .word  0                                 /* 31: Reserved  */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      PMU_IRQHandler
+  .thumb_set PMU_IRQHandler,Default_Handler
+
+  .weak      RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak      U32K0_IRQHandler
+  .thumb_set U32K0_IRQHandler,Default_Handler
+
+  .weak      U32K1_IRQHandler
+  .thumb_set U32K1_IRQHandler,Default_Handler
+
+  .weak      I2C_IRQHandler
+  .thumb_set I2C_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak      UART0_IRQHandler
+  .thumb_set UART0_IRQHandler,Default_Handler
+
+  .weak      UART1_IRQHandler
+  .thumb_set UART1_IRQHandler,Default_Handler
+
+  .weak      UART2_IRQHandler
+  .thumb_set UART2_IRQHandler,Default_Handler
+
+  .weak      UART3_IRQHandler
+  .thumb_set UART3_IRQHandler,Default_Handler
+
+  .weak      UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak      UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+
+  .weak      ISO78160_IRQHandler
+  .thumb_set ISO78160_IRQHandler,Default_Handler
+
+  .weak      ISO78161_IRQHandler
+  .thumb_set ISO78161_IRQHandler,Default_Handler
+
+  .weak      TMR0_IRQHandler
+  .thumb_set TMR0_IRQHandler,Default_Handler
+
+  .weak      TMR1_IRQHandler
+  .thumb_set TMR1_IRQHandler,Default_Handler
+
+  .weak      TMR2_IRQHandler
+  .thumb_set TMR2_IRQHandler,Default_Handler
+
+  .weak      TMR3_IRQHandler
+  .thumb_set TMR3_IRQHandler,Default_Handler
+
+  .weak      PWM0_IRQHandler
+  .thumb_set PWM0_IRQHandler,Default_Handler
+
+  .weak      PWM1_IRQHandler
+  .thumb_set PWM1_IRQHandler,Default_Handler
+
+  .weak      PWM2_IRQHandler
+  .thumb_set PWM2_IRQHandler,Default_Handler
+
+  .weak      PWM3_IRQHandler
+  .thumb_set PWM3_IRQHandler,Default_Handler
+
+  .weak      DMA_IRQHandler
+  .thumb_set DMA_IRQHandler,Default_Handler
+
+  .weak      FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak      ANA_IRQHandler
+  .thumb_set ANA_IRQHandler,Default_Handler
+
+  .weak      SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak      SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler

bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/system_target.c

+/**
+  ******************************************************************************
+  * @file    system_target.c 
+  * @author  Application Team
+  * @version V1.1.0
+  * @date    2019-10-28
+  * @brief   system source file.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+#include "target.h"
+
+#define NVR_REGINFOCOUNT1        (0x80400)
+#define NVR_REGINFOBAKOFFSET     (0x100)
+
+/**
+  * @brief  Setup the microcontroller system
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  uint32_t i,nCount,nValue,nAddress,nChecksum;
+  
+  nCount = *(__IO uint32_t *)NVR_REGINFOCOUNT1;
+  nChecksum = nCount;
+  nChecksum = ~nChecksum;
+  if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+4))
+  {
+    nCount = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET);
+    nChecksum = nCount;
+    nChecksum = ~nChecksum;
+    if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+4))
+    {
+      while(1);
+    }
+  }
+  
+  for(i=0; i<nCount; i++)
+  {
+    nAddress = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+8+i*12);
+    nValue = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+12+i*12);
+    nChecksum = nAddress + nValue;
+    nChecksum = ~nChecksum;
+    if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+16+i*12))
+    {
+      nAddress = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+8+i*12);
+      nValue = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+12+i*12);
+      nChecksum = nAddress + nValue;
+      nChecksum = ~nChecksum;
+      if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+16+i*12))
+      {
+        while(1);
+      }
+    }
+    if((nAddress>=0x40014800) && (nAddress<=0x40015000))
+    {
+      RTC_WriteRegisters(nAddress, &nValue, 1);
+    }
+    else
+    {
+      *(__IO uint32_t *)(nAddress) = nValue;
+    }
+  }
+}
+
+/**
+  * @brief  Initializes registers.
+  * @param  None
+  * @retval None
+  */
+void SystemUpdate(void)
+{
+ 
+}
+
+
+/*********************************** END OF FILE ******************************/

bsp/Vango_V85xx/Libraries/CMSIS/cmsis_compiler.h

+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/Vango_V85xx/Libraries/CMSIS/cmsis_version.h

+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/Vango_V85xx/Libraries/SConscript

+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Glob('VangoV85xx_standard_peripheral/Source/*.c')
+src += [cwd + '/CMSIS/Vango/V85xx/Source/system_target.c']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [cwd + '/CMSIS/Vango/V85xx/Source/GCC/startup_target.S']
+
+path = [
+    cwd + '/CMSIS/Vango/V85xx/Include',
+    cwd + '/CMSIS',
+    cwd + '/VangoV85xx_standard_peripheral/Include',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'V85xx','USE_TARGET_DRIVER']
+
+group = DefineGroup('Vango_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc.h

+/**
+  ******************************************************************************
+  * @file    lib_adc.h 
+  * @author  Application Team
+  * @version V4.6.0
+  * @date    2019-06-18
+  * @brief   ADC library.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+#ifndef __LIB_ADC_H
+#define __LIB_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+  uint32_t TrigMode; 
+  uint32_t ConvMode;  
+  uint32_t ClockSource;  
+  uint32_t ClockDivider;
+  uint32_t Channel;
+} ADCInitType;
+
+//TrigMode
+#define ADC_TRIGMODE_AUTO   0
+#define ADC_TRIGMODE_MANUAL ANA_ADCCTRL_MTRIG
+#define IS_ADC_TRIGMODE(__TRIGMODE__)  (((__TRIGMODE__) == ADC_TRIGMODE_AUTO) ||\
+                                        ((__TRIGMODE__) == ADC_TRIGMODE_MANUAL))
+
+//ConvMode
+#define ADC_CONVMODE_SINGLECHANNEL 0
+#define ADC_CONVMODE_MULTICHANNEL  1
+#define IS_ADC_CONVMODE(__CONVMODE__)  (((__CONVMODE__) == ADC_CONVMODE_SINGLECHANNEL) ||\
+                                        ((__CONVMODE__) == ADC_CONVMODE_MULTICHANNEL))
+
+//ClockSource
+#define ADC_CLKSRC_RCH  0
+#define ADC_CLKSRC_PLLL ANA_ADCCTRL_CLKSEL
+#define IS_ADC_CLKSRC(__CLKSRC__)  (((__CLKSRC__) == ADC_CLKSRC_RCH) ||\
+                                    ((__CLKSRC__) == ADC_CLKSRC_PLLL))
+
+//TrigSource
+#define ADC_TRIGSOURCE_OFF      ANA_ADCCTRL_AEN_OFF
+#define ADC_TRIGSOURCE_TIM0     ANA_ADCCTRL_AEN_TMR0 
+#define ADC_TRIGSOURCE_TIM1     ANA_ADCCTRL_AEN_TMR1 
+#define ADC_TRIGSOURCE_TIM2     ANA_ADCCTRL_AEN_TMR2 
+#define ADC_TRIGSOURCE_TIM3     ANA_ADCCTRL_AEN_TMR3 
+#define IS_ADC_TRIGSOURCE(__TRIGSOURCE__)  (((__TRIGSOURCE__) == ADC_TRIGSOURCE_OFF) ||\
+                                            ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM0) ||\
+                                            ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM1) ||\
+                                            ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM2) ||\
+                                            ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM3))
+
+//ClockDivider
+#define ADC_CLKDIV_1    ANA_ADCCTRL_CLKDIV_1
+#define ADC_CLKDIV_2    ANA_ADCCTRL_CLKDIV_2
+#define ADC_CLKDIV_3    ANA_ADCCTRL_CLKDIV_3
+#define ADC_CLKDIV_4    ANA_ADCCTRL_CLKDIV_4
+#define ADC_CLKDIV_5    ANA_ADCCTRL_CLKDIV_5
+#define ADC_CLKDIV_6    ANA_ADCCTRL_CLKDIV_6
+#define ADC_CLKDIV_7    ANA_ADCCTRL_CLKDIV_7
+#define ADC_CLKDIV_8    ANA_ADCCTRL_CLKDIV_8
+#define ADC_CLKDIV_9    ANA_ADCCTRL_CLKDIV_9
+#define ADC_CLKDIV_10   ANA_ADCCTRL_CLKDIV_10
+#define ADC_CLKDIV_11   ANA_ADCCTRL_CLKDIV_11
+#define ADC_CLKDIV_12   ANA_ADCCTRL_CLKDIV_12
+#define ADC_CLKDIV_13   ANA_ADCCTRL_CLKDIV_13
+#define ADC_CLKDIV_14   ANA_ADCCTRL_CLKDIV_14
+#define ADC_CLKDIV_15   ANA_ADCCTRL_CLKDIV_15
+#define ADC_CLKDIV_16   ANA_ADCCTRL_CLKDIV_16
+#define IS_ADC_CLKDIV(__CLKDIV__)  (((__CLKDIV__) == ADC_CLKDIV_1)  ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_2)  ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_3)  ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_4)  ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_5)  ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_6)  ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_7)  ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_8)  ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_9)  ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_10) ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_11) ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_12) ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_13) ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_14) ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_15) ||\
+                                    ((__CLKDIV__) == ADC_CLKDIV_16))
+
+//Channel
+#define ADC_CHANNEL0       0   
+#define ADC_CHANNEL1       1   
+#define ADC_CHANNEL2       2   
+#define ADC_CHANNEL3       3   
+#define ADC_CHANNEL4       4   
+#define ADC_CHANNEL5       5   
+#define ADC_CHANNEL6       6   
+#define ADC_CHANNEL7       7   
+#define ADC_CHANNEL8       8   
+#define ADC_CHANNEL9       9   
+#define ADC_CHANNEL10      10  
+#define ADC_CHANNEL11      11
+
+#define IS_ADC_CHANNEL(__CHANNEL__)  (((__CHANNEL__) == ADC_CHANNEL0)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL1)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL2)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL3)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL4)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL5)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL6)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL7)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL8)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL9)  ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL10) ||\
+                                      ((__CHANNEL__) == ADC_CHANNEL11))
+                                        
+//INTMask
+#define ADC_INT_AUTODONE    ANA_INTEN_INTEN1
+#define ADC_INT_MANUALDONE  ANA_INTEN_INTEN0
+#define ADC_INT_Msk        (ADC_INT_AUTODONE | ADC_INT_MANUALDONE)
+#define IS_ADC_INT(__INT__)  ((((__INT__) & ADC_INT_Msk) != 0U) &&\
+                              (((__INT__) & ~ADC_INT_Msk) == 0U))
+
+//ScaleDown
+#define ADC_SCA_NONE    0
+#define ADC_SCA_DIV2    ANA_ADCCTRL_CICSCA
+#define IS_ADC_SCA(__SCA__)  (((__SCA__) == ADC_SCA_NONE) || ((__SCA__) == ADC_SCA_DIV2))
+
+//Skip
+#define ADC_SKIP_4  ANA_ADCCTRL_CICSKIP_4
+#define ADC_SKIP_5  ANA_ADCCTRL_CICSKIP_5
+#define ADC_SKIP_6  ANA_ADCCTRL_CICSKIP_6
+#define ADC_SKIP_7  ANA_ADCCTRL_CICSKIP_7
+#define ADC_SKIP_0  ANA_ADCCTRL_CICSKIP_0
+#define ADC_SKIP_1  ANA_ADCCTRL_CICSKIP_1
+#define ADC_SKIP_2  ANA_ADCCTRL_CICSKIP_2
+#define ADC_SKIP_3  ANA_ADCCTRL_CICSKIP_3
+#define IS_ADC_SKIP(__SKIP__)  (((__SKIP__) == ADC_SKIP_4) ||\
+                                ((__SKIP__) == ADC_SKIP_5) ||\
+                                ((__SKIP__) == ADC_SKIP_6) ||\
+                                ((__SKIP__) == ADC_SKIP_7) ||\
+                                ((__SKIP__) == ADC_SKIP_0) ||\
+                                ((__SKIP__) == ADC_SKIP_1) ||\
+                                ((__SKIP__) == ADC_SKIP_2) ||\
+                                ((__SKIP__) == ADC_SKIP_3))
+
+//DSRSelection
+#define ADC_SDRSEL_DIV512  ANA_ADCCTRL_DSRSEL_512
+#define ADC_SDRSEL_DIV256  ANA_ADCCTRL_DSRSEL_256
+#define ADC_SDRSEL_DIV128  ANA_ADCCTRL_DSRSEL_128
+#define ADC_SDRSEL_DIV64   ANA_ADCCTRL_DSRSEL_64
+#define IS_ADC_SDR(__SDR__)  (((__SDR__) == ADC_SDRSEL_DIV512) ||\
+                              ((__SDR__) == ADC_SDRSEL_DIV256) ||\
+                              ((__SDR__) == ADC_SDRSEL_DIV128) ||\
+                              ((__SDR__) == ADC_SDRSEL_DIV64))
+
+typedef struct
+{
+  float VDDVoltage;
+  float BATRTCVoltage;
+  float Temperature;
+} ADC_CalResType;
+//Division
+#define ADC_BAT_CAPDIV  (ANA_REG1_GDE4)
+#define ADC_BAT_RESDIV  (ANA_REG1_RESDIV)
+                                  
+#define IS_ADC_BATDIV(__BATDIV__)  (((__BATDIV__) == ADC_BAT_CAPDIV) ||\
+                                    ((__BATDIV__) == ADC_BAT_RESDIV))
+
+/* ADC_GetVoltage */
+//Mode
+#define ADC_3V_EXTERNAL_NODIV    (0x000UL)    // Power supply: 3.3V;    Channel: External;    Divider modeL: None
+#define ADC_3V_EXTERNAL_RESDIV   (0x001UL)    // Power supply: 3.3V;    Channel: External;    Divider modeL: Resistive
+#define ADC_3V_EXTERNAL_CAPDIV   (0x002UL)    // Power supply: 3.3V;    Channel: External;    Divider modeL: Capacitive
+#define ADC_3V_VDD_RESDIV        (0x003UL)    // Power supply: 3.3V;    Channel: VDD;         Divider modeL: Resistive
+#define ADC_3V_VDD_CAPDIV        (0x004UL)    // Power supply: 3.3V;    Channel: VDD;         Divider modeL: Capacitive
+#define ADC_3V_BATRTC_RESDIV     (0x005UL)    // Power supply: 3.3V;    Channel: BATRTC;      Divider modeL: Resistive
+#define ADC_3V_BATRTC_CAPDIV     (0x006UL)    // Power supply: 3.3V;    Channel: BATRTC;      Divider modeL: Capacitive
+#define ADC_5V_EXTERNAL_NODIV    (0x100UL)    // Power supply: 5V;      Channel: External;    Divider modeL: None
+#define ADC_5V_EXTERNAL_RESDIV   (0x101UL)    // Power supply: 5V;      Channel: External;    Divider modeL: Resistive
+#define ADC_5V_EXTERNAL_CAPDIV   (0x102UL)    // Power supply: 5V;      Channel: External;    Divider modeL: Capacitive
+#define ADC_5V_VDD_RESDIV        (0x103UL)    // Power supply: 5V;      Channel: VDD;         Divider modeL: Resistive
+#define ADC_5V_VDD_CAPDIV        (0x104UL)    // Power supply: 5V;      Channel: VDD;         Divider modeL: Capacitive
+#define ADC_5V_BATRTC_RESDIV     (0x105UL)    // Power supply: 5V;      Channel: BATRTC;      Divider modeL: Resistive
+#define ADC_5V_BATRTC_CAPDIV     (0x106UL)    // Power supply: 5V;      Channel: BATRTC;      Divider modeL: Capacitive
+#define IS_ADCVOL_MODE(__MODE__)      (((__MODE__) == ADC_3V_EXTERNAL_NODIV)   ||\
+                                       ((__MODE__) == ADC_3V_EXTERNAL_RESDIV)  ||\
+                                       ((__MODE__) == ADC_3V_EXTERNAL_CAPDIV)  ||\
+                                       ((__MODE__) == ADC_3V_VDD_RESDIV)       ||\
+                                       ((__MODE__) == ADC_3V_VDD_CAPDIV)       ||\
+                                       ((__MODE__) == ADC_3V_BATRTC_RESDIV)    ||\
+                                       ((__MODE__) == ADC_3V_BATRTC_CAPDIV)    ||\
+                                       ((__MODE__) == ADC_5V_EXTERNAL_NODIV)   ||\
+                                       ((__MODE__) == ADC_5V_EXTERNAL_RESDIV)  ||\
+                                       ((__MODE__) == ADC_5V_EXTERNAL_CAPDIV)  ||\
+                                       ((__MODE__) == ADC_5V_VDD_RESDIV)       ||\
+                                       ((__MODE__) == ADC_5V_VDD_CAPDIV)       ||\
+                                       ((__MODE__) == ADC_5V_BATRTC_RESDIV)    ||\
+                                       ((__MODE__) == ADC_5V_BATRTC_CAPDIV))
+
+/* Exported Functions ------------------------------------------------------- */
+/* ADC Exported Functions Group1: 
+                                  (De)Initialization -------------------------*/
+void ADC_DeInit(void);
+void ADC_StructInit(ADCInitType* ADC_InitStruct);
+void ADC_Init(ADCInitType* ADC_InitStruct);
+/* ADC Exported Functions Group2: 
+                                  Get NVR Info, Calculate datas --------------*/
+uint32_t ADC_CalculateVoltage(uint32_t Mode, int16_t adc_data, float *Voltage);
+uint32_t ADC_GetVDDVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults);
+uint32_t ADC_GetVDDVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults);
+uint32_t ADC_GetBATRTCVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults);
+uint32_t ADC_GetBATRTCVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults);
+uint32_t ADC_GetTemperature(ADC_CalResType *CalResults);
+/* ADC Exported Functions Group3: 
+                                  Interrupt (flag) ---------------------------*/
+int16_t ADC_GetADCConversionValue(uint32_t Channel);
+void ADC_INTConfig(uint32_t INTMask, uint32_t NewState);
+uint8_t ADC_GetAutoDoneFlag(void);
+uint8_t ADC_GetManualDoneFlag(void);
+void ADC_ClearAutoDoneFlag(void);
+void ADC_ClearManualDoneFlag(void);
+/* ADC Exported Functions Group4: 
+                                  MISC Configuration -------------------------*/
+uint32_t ADC_Cmd(uint32_t NewState);
+void ADC_StartManual(void);
+void ADC_WaitForManual(void);
+void ADC_TrigSourceConfig(uint32_t TrigSource);
+void ADC_RESDivisionCmd(uint32_t NewState);
+void ADC_CAPDivisionCmd(uint32_t NewState);
+//CIC Control
+void ADC_CICAlwaysOnCmd(uint32_t NewState);
+void ADC_CICINVCmd(uint32_t NewState);
+void ADC_CICScaleDownConfig(uint32_t ScaleDown);
+void ADC_CICSkipConfig(uint32_t Skip);
+void ADC_CICDownSamRateConfig(uint32_t DSRSelection);
+
+#ifdef __cplusplus
+}
+#endif
+     
+#endif  /* __LIB_ADC_H */
+
+/*********************************** END OF FILE ******************************/

bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc_tiny.h

+/**
+  ******************************************************************************
+  * @file    lib_adc_tiny.h 
+  * @author  Application Team
+  * @version V4.4.0
+  * @date    2018-09-27
+  * @brief   ADC_TINY library.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+#ifndef __LIB_ADC_TINY_H
+#define __LIB_ADC_TINY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+
+typedef struct
+{
+  uint32_t SignalSel; 
+  uint32_t ADTREF1;
+  uint32_t ADTREF2;  
+  uint32_t ADTREF3;
+} TADCInitType;
+
+//SelADT
+#define ADCTINY_SIGNALSEL_IOE6   0
+#define ADCTINY_SIGNALSEL_IOE7   ANA_REGF_SELADT
+#define IS_ADCTINY_SELADT(__SELADT__)  (((__SELADT__) == ADCTINY_SIGNALSEL_IOE6) ||\
+                                        ((__SELADT__) == ADCTINY_SIGNALSEL_IOE7))
+
+//ADTREF1
+#define ADCTINY_REF1_0_9   0
+#define ADCTINY_REF1_0_7   ANA_REGF_ADTREF1SEL
+#define IS_ADCTINY_ADTREF1(__ADTREF1__)  (((__ADTREF1__) == ADCTINY_REF1_0_9) ||\
+                                          ((__ADTREF1__) == ADCTINY_REF1_0_7))
+
+//ADTREF2
+#define ADCTINY_REF2_1_8   0
+#define ADCTINY_REF2_1_6   ANA_REGF_ADTREF2SEL
+#define IS_ADCTINY_ADTREF2(__ADTREF2__)  (((__ADTREF2__) == ADCTINY_REF2_1_8) ||\
+                                          ((__ADTREF2__) == ADCTINY_REF2_1_6))
+
+//ADTREF3
+#define ADCTINY_REF3_2_7   0
+#define ADCTINY_REF3_2_5   ANA_REGF_ADTREF3SEL
+#define IS_ADCTINY_ADTREF3(__ADTREF3__)  (((__ADTREF3__) == ADCTINY_REF3_2_7) ||\
+                                          ((__ADTREF3__) == ADCTINY_REF3_2_5))
+
+//THSel
+#define ADCTINY_THSEL_0  ANA_MISC_TADCTH_0
+#define ADCTINY_THSEL_1  ANA_MISC_TADCTH_1
+#define ADCTINY_THSEL_2  ANA_MISC_TADCTH_2
+#define ADCTINY_THSEL_3  ANA_MISC_TADCTH_3
+#define IS_ADCTINY_THSEL(__THSEL__)  (((__THSEL__) == ADCTINY_THSEL_0) ||\
+                                      ((__THSEL__) == ADCTINY_THSEL_1) ||\
+                                      ((__THSEL__) == ADCTINY_THSEL_2) ||\
+                                      ((__THSEL__) == ADCTINY_THSEL_3))
+
+/* Exported Functions ------------------------------------------------------- */
+void TADC_DeInit(void);
+void TADC_StructInit(TADCInitType* TADC_InitStruct);
+void TADC_Init(TADCInitType* TADC_InitStruct);
+void TADC_Cmd(uint32_t NewState);
+uint8_t TADC_GetOutput(void);
+void TADC_IntTHConfig(uint32_t THSel);
+void TADC_INTConfig(uint32_t NewState);
+uint8_t TADC_GetINTStatus(void);
+void TADC_ClearINTStatus(void);
+
+#ifdef __cplusplus
+}
+#endif
+     
+#endif  /* __LIB_ADC_TINY_H */
+
+/*********************************** END OF FILE ******************************/

bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_tmr.h

+/**
+  ******************************************************************************
+  * @file    lib_tmr.h 
+  * @author  Application Team
+  * @version V4.4.0
+  * @date    2018-09-27
+  * @brief   Timer library.
+  ******************************************************************************
+  * @attention
+  *
+  ******************************************************************************
+  */
+#ifndef __LIB_TMR_H
+#define __LIB_TMR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "target.h"
+   
+typedef struct
+{
+  uint32_t Period;
+  uint32_t ClockSource;
+  uint32_t EXTGT;
+} TMR_InitType;
+//ClockSource
+#define TMR_CLKSRC_INTERNAL     0
+#define TMR_CLKSRC_EXTERNAL     TMR_CTRL_EXTCLK
+//ClockGate
+#define TMR_EXTGT_DISABLE       0
+#define TMR_EXTGT_ENABLE        TMR_CTRL_EXTEN
+                   
+/* Private macros ------------------------------------------------------------*/
+#define  IS_TMR_CLKSRC(__CLKSRC__)  (((__CLKSRC__) == TMR_CLKSRC_INTERNAL) || ((__CLKSRC__) == TMR_CLKSRC_EXTERNAL))
+
+#define  IS_TMR_EXTGT(__EXTGT__)  (((__EXTGT__) == TMR_EXTGT_DISABLE) || ((__EXTGT__) == TMR_EXTGT_ENABLE))
+
+
+/* Exported Functions ------------------------------------------------------- */
+/* Timer Exported Functions Group1: 
+                                    (De)Initialization  ----------------------*/
+void TMR_DeInit(TMR_TypeDef *TMRx);
+void TMR_Init(TMR_TypeDef *TMRx, TMR_InitType *InitStruct);
+void TMR_StructInit(TMR_InitType *InitStruct);
+/* Timer Exported Functions Group2: 
+                                    Interrupt (flag) -------------------------*/
+void TMR_INTConfig(TMR_TypeDef *TMRx, uint32_t NewState);
+uint8_t TMR_GetINTStatus(TMR_TypeDef *TMRx);
+void TMR_ClearINTStatus(TMR_TypeDef *TMRx);
+/* Timer Exported Functions Group3: 
+                                    MISC Configuration -----------------------*/
+void TMR_Cmd(TMR_TypeDef *TMRx, uint32_t NewState);
+uint32_t TMR_GetCurrentValue(TMR_TypeDef *TMRx);
+                           
+#ifdef __cplusplus
+}
+#endif
+     
+#endif  /* __LIB_TMR_H */
+
+/*********************************** END OF FILE ******************************/