From 8b250bc9ff78fd00028ad79fa354dcccedeb5fe0 Mon Sep 17 00:00:00 2001 From: FuChao Date: Tue, 7 Sep 2021 20:08:26 +0800 Subject: [PATCH] add Vango V85xx first version --- bsp/Vango_V85xx/Kconfig | 109 + .../CMSIS/Vango/V85xx/Include/gd32f10x_conf.h | 40 + .../CMSIS/Vango/V85xx/Include/lib_CodeRAM.h | 46 + .../CMSIS/Vango/V85xx/Include/lib_LoadNVR.h | 231 + .../CMSIS/Vango/V85xx/Include/lib_conf.h | 62 + .../CMSIS/Vango/V85xx/Include/lib_cortex.h | 48 + .../CMSIS/Vango/V85xx/Include/system_target.h | 41 + .../CMSIS/Vango/V85xx/Include/target.h | 4994 +++++++++++++++++ .../CMSIS/Vango/V85xx/Include/type_def.h | 104 + .../Vango/V85xx/Source/GCC/startup_target.S | 478 ++ .../CMSIS/Vango/V85xx/Source/system_target.c | 81 + .../Libraries/CMSIS/cmsis_compiler.h | 266 + bsp/Vango_V85xx/Libraries/CMSIS/cmsis_gcc.h | 2085 +++++++ .../Libraries/CMSIS/cmsis_version.h | 39 + bsp/Vango_V85xx/Libraries/CMSIS/core_cm0.h | 949 ++++ bsp/Vango_V85xx/Libraries/CMSIS/core_cmFunc.h | 616 ++ .../Libraries/CMSIS/core_cmInstr.h | 618 ++ bsp/Vango_V85xx/Libraries/SConscript | 25 + .../Include/lib_adc.h | 249 + .../Include/lib_adc_tiny.h | 81 + .../Include/lib_ana.h | 82 + .../Include/lib_clk.h | 307 + .../Include/lib_comp.h | 97 + .../Include/lib_crypt.h | 85 + .../Include/lib_dma.h | 253 + .../Include/lib_flash.h | 74 + .../Include/lib_gpio.h | 175 + .../Include/lib_i2c.h | 119 + .../Include/lib_iso7816.h | 104 + .../Include/lib_lcd.h | 162 + .../Include/lib_misc.h | 80 + .../Include/lib_pmu.h | 319 ++ .../Include/lib_pwm.h | 178 + .../Include/lib_rtc.h | 198 + .../Include/lib_spi.h | 180 + .../Include/lib_tmr.h | 63 + .../Include/lib_u32k.h | 142 + .../Include/lib_uart.h | 167 + .../Include/lib_version.h | 36 + .../Include/lib_wdt.h | 46 + .../Source/lib_adc.c | 977 ++++ .../Source/lib_adc_tiny.c | 175 + .../Source/lib_ana.c | 136 + .../Source/lib_clk.c | 635 +++ .../Source/lib_comp.c | 337 ++ .../Source/lib_crypt.c | 226 + .../Source/lib_dma.c | 442 ++ .../Source/lib_flash.c | 297 + .../Source/lib_gpio.c | 563 ++ .../Source/lib_i2c.c | 689 +++ .../Source/lib_iso7816.c | 396 ++ .../Source/lib_lcd.c | 601 ++ .../Source/lib_misc.c | 259 + .../Source/lib_pmu.c | 1158 ++++ .../Source/lib_pwm.c | 466 ++ .../Source/lib_rtc.c | 667 +++ .../Source/lib_spi.c | 430 ++ .../Source/lib_tmr.c | 178 + .../Source/lib_u32k.c | 317 ++ .../Source/lib_uart.c | 391 ++ .../Source/lib_version.c | 25 + .../Source/lib_wdt.c | 88 + bsp/Vango_V85xx/README.md | 72 + bsp/Vango_V85xx/SConscript | 14 + bsp/Vango_V85xx/SConstruct | 40 + bsp/Vango_V85xx/Target_FLASH.icf | 31 + bsp/Vango_V85xx/Target_FLASH.ld | 173 + bsp/Vango_V85xx/Target_FLASH.sct | 17 + bsp/Vango_V85xx/applications/SConscript | 11 + bsp/Vango_V85xx/applications/main.c | 53 + bsp/Vango_V85xx/drivers/SConscript | 35 + bsp/Vango_V85xx/drivers/board.c | 78 + bsp/Vango_V85xx/drivers/board.h | 26 + bsp/Vango_V85xx/drivers/drv_comm.h | 27 + bsp/Vango_V85xx/drivers/drv_gpio.c | 323 ++ bsp/Vango_V85xx/drivers/drv_gpio.h | 45 + bsp/Vango_V85xx/drivers/drv_usart.c | 324 ++ bsp/Vango_V85xx/drivers/drv_usart.h | 33 + bsp/Vango_V85xx/rtconfig.h | 182 + bsp/Vango_V85xx/rtconfig.py | 126 + 80 files changed, 25092 insertions(+) create mode 100644 bsp/Vango_V85xx/Kconfig create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/gd32f10x_conf.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/target.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/system_target.c create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/cmsis_compiler.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/cmsis_gcc.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/cmsis_version.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/core_cm0.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/core_cmFunc.h create mode 100644 bsp/Vango_V85xx/Libraries/CMSIS/core_cmInstr.h create mode 100644 bsp/Vango_V85xx/Libraries/SConscript create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc_tiny.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_ana.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_clk.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_comp.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_crypt.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_dma.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_flash.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_gpio.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_i2c.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_iso7816.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_lcd.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_misc.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pmu.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pwm.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_rtc.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_spi.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_tmr.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_u32k.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_uart.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_version.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_wdt.h create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc_tiny.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_ana.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_clk.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_comp.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_crypt.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_dma.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_flash.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_gpio.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_i2c.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_iso7816.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_lcd.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_misc.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pmu.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pwm.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_rtc.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_spi.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_tmr.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_u32k.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_uart.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_version.c create mode 100644 bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_wdt.c create mode 100644 bsp/Vango_V85xx/README.md create mode 100644 bsp/Vango_V85xx/SConscript create mode 100644 bsp/Vango_V85xx/SConstruct create mode 100644 bsp/Vango_V85xx/Target_FLASH.icf create mode 100644 bsp/Vango_V85xx/Target_FLASH.ld create mode 100644 bsp/Vango_V85xx/Target_FLASH.sct create mode 100644 bsp/Vango_V85xx/applications/SConscript create mode 100644 bsp/Vango_V85xx/applications/main.c create mode 100644 bsp/Vango_V85xx/drivers/SConscript create mode 100644 bsp/Vango_V85xx/drivers/board.c create mode 100644 bsp/Vango_V85xx/drivers/board.h create mode 100644 bsp/Vango_V85xx/drivers/drv_comm.h create mode 100644 bsp/Vango_V85xx/drivers/drv_gpio.c create mode 100644 bsp/Vango_V85xx/drivers/drv_gpio.h create mode 100644 bsp/Vango_V85xx/drivers/drv_usart.c create mode 100644 bsp/Vango_V85xx/drivers/drv_usart.h create mode 100644 bsp/Vango_V85xx/rtconfig.h create mode 100644 bsp/Vango_V85xx/rtconfig.py diff --git a/bsp/Vango_V85xx/Kconfig b/bsp/Vango_V85xx/Kconfig new file mode 100644 index 0000000000..97fb8f2b2c --- /dev/null +++ b/bsp/Vango_V85xx/Kconfig @@ -0,0 +1,109 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default: "rt-thread" +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_SERIES_GD32F1 + bool + default y + +config SOC_GD32103C + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select SOC_SERIES_GD32F1 + default y + +menu "On-chip Peripheral Drivers" + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "using uart0" + default n + config BSP_USING_UART1 + bool "using uart1" + default n + config BSP_USING_UART2 + bool "using uart2" + default y + config BSP_USING_UART3 + bool "using uart3" + default n + config BSP_USING_UART4 + bool "using uart4" + default n + endif + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "using adc0" + default n + config BSP_USING_ADC1 + bool "using adc1" + default n + endif + menuconfig BSP_USING_HWTIMER + bool "Enable hwtimer" + default n + select RT_USING_HWTIMER + if BSP_USING_HWTIMER + config BSP_USING_HWTIMER0 + bool "using hwtimer0" + default n + config BSP_USING_HWTIMER1 + bool "using hwtimer1" + default n + config BSP_USING_HWTIMER2 + bool "using hwtimer2" + default n + config BSP_USING_HWTIMER3 + bool "using hwtimer3" + default n + config BSP_USING_HWTIMER4 + bool "using hwtimer4" + default n + config BSP_USING_HWTIMER5 + bool "using hwtimer5" + default n + config BSP_USING_HWTIMER6 + bool "using hwtimer6" + default n + config BSP_USING_HWTIMER7 + bool "using hwtimer7" + default n + endif + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_RTC + bool "using internal rtc" + default n + select RT_USING_RTC + +endmenu diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/gd32f10x_conf.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/gd32f10x_conf.h new file mode 100644 index 0000000000..b9e3e3646c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/gd32f10x_conf.h @@ -0,0 +1,40 @@ +/** + ****************************************************************************** + * @brief Configuration file. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GD32F10X_CONF_H +#define __GD32F10X_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Comment the line below to disable peripheral header file inclusion */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_comp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +#endif /* __GD32F10X_CONF_H */ + diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h new file mode 100644 index 0000000000..1ee13c34ea --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h @@ -0,0 +1,46 @@ +/** + ****************************************************************************** + * @file lib_CodeRAM.h + * @author Application Team + * @version V4.4.0 + * @date 2019-01-18 + * @brief Codes executed in SRAM. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CODERAM_H +#define __LIB_CODERAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +#ifndef __GNUC__ + +#ifdef __ICCARM__ /* EWARM */ + #define __RAM_FUNC __ramfunc +#endif + +#ifdef __CC_ARM /* MDK-ARM */ + #define __RAM_FUNC __attribute__((used)) +#endif + +/* Exported Functions ------------------------------------------------------- */ + +__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void); + +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CODERAM_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h new file mode 100644 index 0000000000..e28cad6b66 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h @@ -0,0 +1,231 @@ +/** + ****************************************************************************** + * @file lib_LoadNVR.h + * @author Application Team + * @version V4.7.0 + * @date 2019-12-12 + * @brief Load information from NVR. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_LOADNVR_H +#define __LIB_LOADNVR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* BAT measure result */ +typedef struct +{ + float BATRESResult; // BAT Resistor division Measure Result + float BATCAPResult; // BATRTC Cap division Measure Result +} NVR_BATMEARES; + +/* Power Measure Result */ +typedef struct +{ + uint32_t AVCCMEAResult; // LDO33 Measure Result + uint32_t DVCCMEAResult; // LDO15 Measure Result + uint32_t BGPMEAResult; // BGP Measure Result + uint32_t RCLMEAResult; // RCL Measure Result + uint32_t RCHMEAResult; // RCH Measure Result +} NVR_MISCGain; + +/* Chip ID */ +typedef struct +{ + uint32_t ChipID0; // ID word 0 + uint32_t ChipID1; // ID word 1 +} NVR_CHIPID; + +/* Temperature information */ +typedef struct +{ + float TempOffset; +} NVR_TEMPINFO; + +/* LCD information */ +typedef struct +{ + uint32_t MEALCDLDO; // Measure LCD LDO pre trim value + uint32_t MEALCDVol; // VLCD setting +} NVR_LCDINFO; + +/* RTC(temp) information */ +typedef struct +{ + int16_t RTCTempP0; //P0 + int16_t RTCTempP1; //P1 + int32_t RTCTempP2; //P2 + int16_t RTCTempP4; //P4 + int16_t RTCTempP5; //P5 + int16_t RTCTempP6; //P6 + int16_t RTCTempP7; //P7 + int16_t RTCTempK1; //K1 + int16_t RTCTempK2; //K2 + int16_t RTCTempK3; //K3 + int16_t RTCTempK4; //K4 + int16_t RTCTempK5; //K5 + int16_t RTCACTI; //Center temperature + uint32_t RTCACKTemp; //section X temperature + int16_t RTCTempDelta; //Temperature delta + uint32_t RTCACF200; //RTC_ACF200 + uint32_t APBClock; //APB clock +} NVR_RTCINFO; + +/* ADC Voltage Parameters */ +typedef struct +{ + float aParameter; + float bParameter; +} NVR_ADCVOLPARA; +//Mode +#define NVR_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None +#define NVR_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive +#define NVR_3V_EXTERNAL_CAPDIV (0x002UL) // Power supply: 3.3V; Channel: External; Divider modeL: Capacitive +#define NVR_3V_VDD_RESDIV (0x003UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive +#define NVR_3V_VDD_CAPDIV (0x004UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Capacitive +#define NVR_3V_BATRTC_RESDIV (0x005UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive +#define NVR_3V_BATRTC_CAPDIV (0x006UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Capacitive +#define NVR_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None +#define NVR_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive +#define NVR_5V_EXTERNAL_CAPDIV (0x102UL) // Power supply: 5V; Channel: External; Divider modeL: Capacitive +#define NVR_5V_VDD_RESDIV (0x103UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive +#define NVR_5V_VDD_CAPDIV (0x104UL) // Power supply: 5V; Channel: VDD; Divider modeL: Capacitive +#define NVR_5V_BATRTC_RESDIV (0x105UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive +#define NVR_5V_BATRTC_CAPDIV (0x106UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Capacitive +#define IS_NVR_ADCVOL_MODE(__MODE__) (((__MODE__) == NVR_3V_EXTERNAL_NODIV) ||\ + ((__MODE__) == NVR_3V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == NVR_3V_EXTERNAL_CAPDIV) ||\ + ((__MODE__) == NVR_3V_VDD_RESDIV) ||\ + ((__MODE__) == NVR_3V_VDD_CAPDIV) ||\ + ((__MODE__) == NVR_3V_BATRTC_RESDIV) ||\ + ((__MODE__) == NVR_3V_BATRTC_CAPDIV) ||\ + ((__MODE__) == NVR_5V_EXTERNAL_NODIV) ||\ + ((__MODE__) == NVR_5V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == NVR_5V_EXTERNAL_CAPDIV) ||\ + ((__MODE__) == NVR_5V_VDD_RESDIV) ||\ + ((__MODE__) == NVR_5V_VDD_CAPDIV) ||\ + ((__MODE__) == NVR_5V_BATRTC_RESDIV) ||\ + ((__MODE__) == NVR_5V_BATRTC_CAPDIV)) + +/********** NVR Address **********/ +//ADC Voltage Parameters +#define NVR_3VPARA_BASEADDR1 (__IO uint32_t *)(0x40400) +#define NVR_3VPARA_BASEADDR2 (__IO uint32_t *)(0x40440) +#define NVR_5VPARA_BASEADDR1 (__IO uint32_t *)(0x40480) +#define NVR_5VPARA_BASEADDR2 (__IO uint32_t *)(0x404C0) +//RTC DATA +//P4 +#define NVR_RTC1_P4 (__IO uint32_t *)(0x40800) +#define NVR_RTC1_P4_CHKSUM (__IO uint32_t *)(0x40804) +#define NVR_RTC2_P4 (__IO uint32_t *)(0x40808) +#define NVR_RTC2_P4_CHKSUM (__IO uint32_t *)(0x4080C) +//ACK1~ACK5 +#define NVR_RTC1_ACK1 (__IO uint32_t *)(0x40810) +#define NVR_RTC1_ACK2 (__IO uint32_t *)(0x40814) +#define NVR_RTC1_ACK3 (__IO uint32_t *)(0x40818) +#define NVR_RTC1_ACK4 (__IO uint32_t *)(0x4081C) +#define NVR_RTC1_ACK5 (__IO uint32_t *)(0x40820) +#define NVR_RTC1_ACK_CHKSUM (__IO uint32_t *)(0x40824) +#define NVR_RTC2_ACK1 (__IO uint32_t *)(0x40828) +#define NVR_RTC2_ACK2 (__IO uint32_t *)(0x4082C) +#define NVR_RTC2_ACK3 (__IO uint32_t *)(0x40830) +#define NVR_RTC2_ACK4 (__IO uint32_t *)(0x40834) +#define NVR_RTC2_ACK5 (__IO uint32_t *)(0x40838) +#define NVR_RTC2_ACK_CHKSUM (__IO uint32_t *)(0x4083C) +//ACTI +#define NVR_RTC1_ACTI (__IO uint32_t *)(0x40840) +#define NVR_RTC1_ACTI_CHKSUM (__IO uint32_t *)(0x40844) +#define NVR_RTC2_ACTI (__IO uint32_t *)(0x40848) +#define NVR_RTC2_ACTI_CHKSUM (__IO uint32_t *)(0x4084C) +//ACKTEMP +#define NVR_RTC1_ACKTEMP (__IO uint32_t *)(0x40850) +#define NVR_RTC1_ACKTEMP_CHKSUM (__IO uint32_t *)(0x40854) +#define NVR_RTC2_ACKTEMP (__IO uint32_t *)(0x40858) +#define NVR_RTC2_ACKTEMP_CHKSUM (__IO uint32_t *)(0x4085C) +//Analog trim data +#define NVR_ANA_TRIMDATA1 (__IO uint32_t *)(0x40DC0) +#define NVR_ANA_OPREG1 (__IO uint32_t *)(0x40DC4) +#define NVR_ANA_KEYREG1 (__IO uint32_t *)(0x40DC8) +#define NVR_ANA_CHECKSUM1 (__IO uint32_t *)(0x40DCC) +#define NVR_ANA_TRIMDATA2 (__IO uint32_t *)(0x40DD0) +#define NVR_ANA_OPREG2 (__IO uint32_t *)(0x40DD4) +#define NVR_ANA_KEYREG2 (__IO uint32_t *)(0x40DD8) +#define NVR_ANA_CHECKSUM2 (__IO uint32_t *)(0x40DDC) +//BAT Measure Result +#define NVR_BAT_R1 (__IO uint32_t *)(0x40CE0) +#define NVR_BAT_C1 (__IO uint32_t *)(0x40CE4) +#define NVR_BATMEA_CHECHSUM1 (__IO uint32_t *)(0x40CE8) +#define NVR_BAT_R2 (__IO uint32_t *)(0x40CF0) +#define NVR_BAT_C2 (__IO uint32_t *)(0x40CF4) +#define NVR_BATMEA_CHECHSUM2 (__IO uint32_t *)(0x40CF8) +//RTC AutoCal Px pramameters +#define NVR_RTC1_P1_P0 (__IO uint32_t *)(0x40D00) +#define NVR_RTC1_P2 (__IO uint32_t *)(0x40D04) +#define NVR_RTC1_P5_P4 (__IO uint32_t *)(0x40D08) +#define NVR_RTC1_P7_P6 (__IO uint32_t *)(0x40D0C) +#define NVR_RTC1_PCHECHSUM (__IO uint32_t *)(0x40D10) +#define NVR_RTC2_P1_P0 (__IO uint32_t *)(0x40D14) +#define NVR_RTC2_P2 (__IO uint32_t *)(0x40D18) +#define NVR_RTC2_P5_P4 (__IO uint32_t *)(0x40D1C) +#define NVR_RTC2_P7_P6 (__IO uint32_t *)(0x40D20) +#define NVR_RTC2_PCHECHSUM (__IO uint32_t *)(0x40D24) +//Power Measure Result +#define NVR_DVCC_MEA1 (__IO uint32_t *)(0x40D28) +#define NVR_AVCC_MEA1 (__IO uint32_t *)(0x40D2C) +#define NVR_BGP_MEA1 (__IO uint32_t *)(0x40D30) +#define NVR_RCL_MEA1 (__IO uint32_t *)(0x40D34) +#define NVR_RCH_MEA1 (__IO uint32_t *)(0x40D38) +#define NVR_PWR_CHECKSUM1 (__IO uint32_t *)(0x40D3C) +#define NVR_DVCC_MEA2 (__IO uint32_t *)(0x40D40) +#define NVR_AVCC_MEA2 (__IO uint32_t *)(0x40D44) +#define NVR_BGP_MEA2 (__IO uint32_t *)(0x40D48) +#define NVR_RCL_MEA2 (__IO uint32_t *)(0x40D4C) +#define NVR_RCH_MEA2 (__IO uint32_t *)(0x40D50) +#define NVR_PWR_CHECKSUM2 (__IO uint32_t *)(0x40D54) +//Chip ID +#define NVR_CHIP1_ID0 (__IO uint32_t *)(0x40D58) +#define NVR_CHIP1_ID1 (__IO uint32_t *)(0x40D5C) +#define NVR_CHIP1_CHECKSUM (__IO uint32_t *)(0x40D60) +#define NVR_CHIP2_ID0 (__IO uint32_t *)(0x40D64) +#define NVR_CHIP2_ID1 (__IO uint32_t *)(0x40D68) +#define NVR_CHIP2_CHECKSUM (__IO uint32_t *)(0x40D6C) +//Temperature information +#define NVR_REALTEMP1 (__IO uint32_t *)(0x40D70) +#define NVR_MEATEMP1 (__IO uint32_t *)(0x40D74) +#define NVR_TEMP_CHECKSUM1 (__IO uint32_t *)(0x40D78) +#define NVR_REALTEMP2 (__IO uint32_t *)(0x40D7C) +#define NVR_MEATEMP2 (__IO uint32_t *)(0x40D80) +#define NVR_TEMP_CHECKSUM2 (__IO uint32_t *)(0x40D84) +//LCD Information +#define NVR_LCD_LDO1 (__IO uint32_t *)(0x40D90) +#define NVR_LCD_VOL1 (__IO uint32_t *)(0x40D94) +#define NVR_LCD_CHECKSUM1 (__IO uint32_t *)(0x40D98) +#define NVR_LCD_LDO2 (__IO uint32_t *)(0x40D9C) +#define NVR_LCD_VOL2 (__IO uint32_t *)(0x40DA0) +#define NVR_LCD_CHECKSUM2 (__IO uint32_t *)(0x40DA4) + + +uint32_t NVR_LoadANADataManual(void); +uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter); +uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult); +uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData); +uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult); +uint32_t NVR_GetChipID(NVR_CHIPID *ChipID); +uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_LOADNVR_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h new file mode 100644 index 0000000000..a536dfc6d9 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_comp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h new file mode 100644 index 0000000000..d7c1994cfc --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h @@ -0,0 +1,48 @@ +/** + ****************************************************************************** + * @file lib_Cortex.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Cortex module driver. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CORTEX_H +#define __LIB_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + + +#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) + +/* Exported Functions ------------------------------------------------------- */ +void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority); + +void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn); +void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn); +uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn); +void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority); +void CORTEX_NVIC_SystemReset(void); +uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CORTEX_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h new file mode 100644 index 0000000000..c897151964 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h @@ -0,0 +1,41 @@ +/** + ****************************************************************************** + * @file system_target.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief system source file. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __SYSTEM_TARGET_H +#define __SYSTEM_TARGET_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "type_def.h" + +#define NVR_REGINFOCOUNT1 (0x80400) +#define NVR_REGINFOBAKOFFSET (0x100) + +/* ########################### System Configuration ######################### */ + +extern void SystemInit(void); +extern void SystemUpdate(void); + + +#ifdef USE_TARGET_DRIVER + #include "lib_conf.h" +#endif /* USE_TARGET_DRIVER */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_TARGET_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/target.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/target.h new file mode 100644 index 0000000000..7199c552fb --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/target.h @@ -0,0 +1,4994 @@ +/** +******************************************************************************** +* @file target.h +* @author Application Team +* @version V4.4.0 +* @date 2018-09-27 +* @brief Register define +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, XXXXX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +******************************************************************************** +*/ +#ifndef __TARGET_H +#define __TARGET_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define __Vendor_SysTickConfig 0 /*!< target uses systick config */ +#define __NVIC_PRIO_BITS 2 /*!< target uses 2 Bits for the Priority Levels */ + +typedef enum {ERROR = 0, SUCCESS = !ERROR, RESET = 0, SET = !RESET, DISABLE = 0, ENABLE = !DISABLE} TypeState, EventStatus, ControlStatus, FlagStatus, ErrStatus; + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + NMI_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** target specific Interrupt Numbers ********************************************************************/ + PMU_IRQn = 0, /*!< Power Management Unit Interrupt */ + RTC_IRQn = 1, /*!< RTC global Interrupt */ + U32K0_IRQn = 2, /*!< U32K0 global Interrupt */ + U32K1_IRQn = 3, /*!< U32K1 global Interrupt */ + I2C_IRQn = 4, /*!< I2C global Interrupt */ + SPI1_IRQn = 5, /*!< SPI1 global Interrupt */ + UART0_IRQn = 6, /*!< UART0 global Interrupt */ + UART1_IRQn = 7, /*!< UART1 global Interrupt */ + UART2_IRQn = 8, /*!< UART2 global Interrupt */ + UART3_IRQn = 9, /*!< UART3 global Interrupt */ + UART4_IRQn = 10, /*!< UART4 global Interrupt */ + UART5_IRQn = 11, /*!< UART5 global Interrupt */ + ISO78160_IRQn = 12, /*!< ISO78160 global Interrupt */ + ISO78161_IRQn = 13, /*!< ISO78161 global Interrupt */ + TMR0_IRQn = 14, /*!< Timer0 global Interrupt */ + TMR1_IRQn = 15, /*!< Timer1 global Interrupt */ + TMR2_IRQn = 16, /*!< Timer2 global Interrupt */ + TMR3_IRQn = 17, /*!< Timer3 global Interrupt */ + PWM0_IRQn = 18, /*!< PWM0 global Interrupt */ + PWM1_IRQn = 19, /*!< PWM1 global Interrupt */ + PWM2_IRQn = 20, /*!< PWM2 global Interrupt */ + PWM3_IRQn = 21, /*!< PWM3 global Interrupt */ + DMA_IRQn = 22, /*!< DMA global Interrupt */ + FLASH_IRQn = 23, /*!< FLASH global Interrupt */ + ANA_IRQn = 24, /*!< ANA global Interrupt */ + SPI2_IRQn = 27, /*!< SPI2 global Interrupt */ +} IRQn_Type; + +#include "core_cm0.h" +#include "type_def.h" + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Power Management Unit Controller + */ + +typedef struct +{ + __IO uint32_t DSLEEPEN; /*!< PMU deep sleep enable register, Address offset: 0x00 */ + __IO uint32_t DSLEEPPASS; /*!< PMU deep sleep password register, Address offset: 0x04 */ + __IO uint32_t CONTROL; /*!< PMU control register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< PMU Status register, Address offset: 0x0C */ + __IO uint32_t IOAOEN; /*!< IOA output enable register, Address offset: 0x10 */ + __IO uint32_t IOAIE; /*!< IOA input enable register, Address offset: 0x14 */ + __IO uint32_t IOADAT; /*!< IOA data register, Address offset: 0x18 */ + __IO uint32_t IOAATT; /*!< IOA attribute register, Address offset: 0x1C */ + __IO uint32_t IOAWKUEN; /*!< IOA input status register, Address offset: 0x20 */ + __IO uint32_t IOASTS; /*!< IOA input status register, Address offset: 0x24 */ + __IO uint32_t IOAINTSTS; /*!< IOA input status register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< Reserved, 0x2C */ + uint32_t RESERVED2; /*!< Reserved, 0x30 */ + uint32_t RESERVED3; /*!< Reserved, 0x34 */ + __IO uint32_t IOASEL; /*!< IOA special function select register, Address offset: 0x38 */ + __IO uint32_t VERSIONID_; /*!< Version ID of chip, Address offset: 0x3C */ + __IO uint32_t WDTPASS; /*!< Watch dog timing unlock register, Address offset: 0x40 */ + __IO uint32_t WDTEN; /*!< Watch dog timer enable register, Address offset: 0x44 */ + __IO uint32_t WDTCLR; /*!< Watch dog timer clear register, Address offset: 0x48 */ +// __IO uint32_t WDTSTS; /*!< Watch dog timer status register, Address offset: 0x4C */ + uint32_t RESERVED4; /*!< Reserved, 0x4C */ + __IO uint32_t IOANODEG; /*!< IOA de-glitch circuit control, Address offset: 0x50 */ +}PMU_TypeDef; + +/** + * @brief Power Management Unit Retention RAM + */ + +typedef struct +{ + __IO uint32_t RAM[64]; /*!< PMU 32 bits Retention RAM 0-63, Address offset: 0x00-0xFC */ +}PMU_RETRAM_TypeDef; + +/** + * @brief Analog control register + */ + +typedef struct +{ + __IO uint32_t REG0; /*!< Analog control register 0, Address offset:0x00 */ + __IO uint32_t REG1; /*!< Analog control register 1, Address offset:0x04 */ + __IO uint32_t REG2; /*!< Analog control register 2, Address offset:0x08 */ + __IO uint32_t REG3; /*!< Analog control register 3, Address offset:0x0C */ + __IO uint32_t REG4; /*!< Analog control register 4, Address offset:0x10 */ + __IO uint32_t REG5; /*!< Analog control register 5, Address offset:0x14 */ + __IO uint32_t REG6; /*!< Analog control register 6, Address offset:0x18 */ + __IO uint32_t REG7; /*!< Analog control register 7, Address offset:0x1C */ + __IO uint32_t REG8; /*!< Analog control register 8, Address offset:0x20 */ + __IO uint32_t REG9; /*!< Analog control register 9, Address offset:0x24 */ + __IO uint32_t REGA; /*!< Analog control register 10, Address offset:0x28 */ + __IO uint32_t REGB; /*!< Analog control register 11, Address offset:0x2C */ + __IO uint32_t REGC; /*!< Analog control register 12, Address offset:0x30 */ + __IO uint32_t REGD; /*!< Analog control register 13, Address offset:0x34 */ + __IO uint32_t REGE; /*!< Analog control register 14, Address offset:0x38 */ + __IO uint32_t REGF; /*!< Analog control register 15, Address offset:0x3C */ +// __IO uint32_t REG10; /*!< Analog control register 16, Address offset:0x40 */ +// __IO uint32_t REG11; /*!< Analog control register 17, Address offset:0x44 */ +// __IO uint32_t REG12; /*!< Analog control register 18, Address offset:0x48 */ + uint32_t RESERVED1; /*!< Reserved, 0x40 */ + uint32_t RESERVED2; /*!< Reserved, 0x44 */ + uint32_t RESERVED3; /*!< Reserved, 0x48 */ + uint32_t RESERVED4; /*!< Reserved, 0x4C */ + __IO uint32_t CTRL; /*!< Analog misc. control register, Address offset:0x50 */ + __IO uint32_t COMPOUT; /*!< Comparator result register, Address offset:0x54 */ + //__IO uint32_t VERSION; /*!< Analog IP version register, Address offset:0x58 */ + //__IO uint32_t ADCSTATE; /*!< ADC State register, Address offset:0x5C */ + uint32_t RESERVED5; /*!< Reserved, */ + uint32_t RESERVED6; /*!< Reserved, */ + __IO uint32_t INTSTS; /*!< Analog interrupt status register, Address offset:0x60 */ + __IO uint32_t INTEN; /*!< Analog interrupt enable register, Address offset:0x64 */ + __IO uint32_t ADCCTRL; /*!< ADC control register, Address offset:0x68 */ + uint32_t RESERVED7; /*!< Reserved, 0x6C */ + __IO uint32_t ADCDATA0; /*!< ADC channel 0 data register, Address offset:0x70 */ + __IO uint32_t ADCDATA1; /*!< ADC channel 1 data register, Address offset:0x74 */ + __IO uint32_t ADCDATA2; /*!< ADC channel 2 data register, Address offset:0x78 */ + __IO uint32_t ADCDATA3; /*!< ADC channel 3 data register, Address offset:0x7C */ + __IO uint32_t ADCDATA4; /*!< ADC channel 4 data register, Address offset:0x80 */ + __IO uint32_t ADCDATA5; /*!< ADC channel 5 data register, Address offset:0x84 */ + __IO uint32_t ADCDATA6; /*!< ADC channel 6 data register, Address offset:0x88 */ + __IO uint32_t ADCDATA7; /*!< ADC channel 7 data register, Address offset:0x8C */ + __IO uint32_t ADCDATA8; /*!< ADC channel 8 data register, Address offset:0x90 */ + __IO uint32_t ADCDATA9; /*!< ADC channel 9 data register, Address offset:0x94 */ + __IO uint32_t ADCDATAA; /*!< ADC channel 10 data register, Address offset:0x98 */ + __IO uint32_t ADCDATAB; /*!< ADC channel 11 data register, Address offset:0x9C */ +// __IO uint32_t ADCDATAC; /*!< ADC channel 12 data register, Address offset:0xA0 */ +// __IO uint32_t ADCDATAD; /*!< ADC channel 13 data register, Address offset:0xA4 */ +// __IO uint32_t ADCDATAE; /*!< ADC channel 14 data register, Address offset:0xA8 */ +// __IO uint32_t ADCDATAF; /*!< ADC channel 15 data register, Address offset:0xAC */ + uint32_t RESERVED8; /*!< Reserved, 0xA0 */ + uint32_t RESERVED9; /*!< Reserved, 0xA4 */ + uint32_t RESERVED10; /*!< Reserved, 0xA8 */ + uint32_t RESERVED11; /*!< Reserved, 0xAC */ + __IO uint32_t CMPCNT1; /*!< Comparator 1 counter, Address offset:0xB0 */ + __IO uint32_t CMPCNT2; /*!< Comparator 2 counter, Address offset:0xB4 */ + __IO uint32_t MISC_A; /*!< MISC, Address offset:0xB8 */ +} ANA_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t SEC; /*!< RTC second register, Address offset: 0x00 */ + __IO uint32_t MIN; /*!< RTC minute register, Address offset: 0x04 */ + __IO uint32_t HOUR; /*!< RTC hour register, Address offset: 0x08 */ + __IO uint32_t DAY; /*!< RTC day register, Address offset: 0x0C */ + __IO uint32_t WEEK; /*!< RTC week-day register, Address offset: 0x10 */ + __IO uint32_t MON; /*!< RTC month register, Address offset: 0x14 */ + __IO uint32_t YEAR; /*!< RTC year register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUSEC; /*!< RTC wake-up second register, Address offset: 0x20 */ + __IO uint32_t WKUMIN; /*!< RTC wake-up minute register, Address offset: 0x24 */ + __IO uint32_t WKUHOUR; /*!< RTC wake-up hour register, Address offset: 0x28 */ + __IO uint32_t WKUCNT; /*!< RTC wake-up counter register, Address offset: 0x2C */ + __IO uint32_t CAL; /*!< RTC calibration register, Address offset: 0x30 */ + __IO uint32_t DIV; /*!< RTC PLL divider register, Address offset: 0x34 */ + __IO uint32_t CTL; /*!< RTC PLL divider control register, Address offset: 0x38 */ + uint32_t RESERVED2; + uint32_t RESERVED3; + //__IO uint32_t ITV; /*!< RTC wake-up interval control, Address offset: 0x3C */ + //__IO uint32_t SITV; /*!< RTC wake-up second interval control, Address offset: 0x40 */ + __IO uint32_t PWD; /*!< RTC password control register, Address offset: 0x44 */ + __IO uint32_t CE; /*!< RTC write enable control register, Address offset: 0x48 */ + __IO uint32_t LOAD; /*!< RTC read enable control register, Address offset: 0x4C */ + __IO uint32_t INTSTS; /*!< RTC interrupt status control register, Address offset: 0x50 */ + __IO uint32_t INTEN; /*!< RTC interrupt enable control register, Address offset: 0x54 */ + __IO uint32_t PSCA; /*!< RTC clock pre-scaler control register, Address offset: 0x58 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x5C-0x7C */ + __IO uint32_t ACCTRL; /*!< RTC auto-calibration control register, Address offset: 0x80 */ + __IO uint32_t ACTI; /*!< RTC auto-calibration center temperature control register, Address offset: 0x84 */ + __IO uint32_t ACF200; /*!< RTC auto-calibration 200*frequency control register, Address offset: 0x88 */ + __IO uint32_t ACADCW; /*!< RTC auto-calibration manual ADC value control register, Address offset: 0x8C */ + __IO uint32_t ACP0; /*!< RTC auto-calibration parameter 0 control register, Address offset: 0x90 */ + __IO uint32_t ACP1; /*!< RTC auto-calibration parameter 1 control register, Address offset: 0x94 */ + __IO uint32_t ACP2; /*!< RTC auto-calibration parameter 2 control register, Address offset: 0x98 */ + __IO uint32_t ACP3; /*!< RTC auto-calibration parameter 3 control register, Address offset: 0x9C */ + __IO uint32_t ACP4; /*!< RTC auto-calibration parameter 4 control register, Address offset: 0xA0 */ + __IO uint32_t ACP5; /*!< RTC auto-calibration parameter 5 control register, Address offset: 0xA4 */ + __IO uint32_t ACP6; /*!< RTC auto-calibration parameter 6 control register, Address offset: 0xA8 */ + __IO uint32_t ACP7; /*!< RTC auto-calibration parameter 7 control register, Address offset: 0xAC */ + __IO uint32_t ACK1; /*!< RTC auto-calibration parameter k1 control register, Address offset: 0xB0 */ + __IO uint32_t ACK2; /*!< RTC auto-calibration parameter k2 control register, Address offset: 0xB4 */ + __IO uint32_t ACK3; /*!< RTC auto-calibration parameter k3 control register, Address offset: 0xB8 */ + __IO uint32_t ACK4; /*!< RTC auto-calibration parameter k4 control register, Address offset: 0xBC */ + __IO uint32_t ACK5; /*!< RTC auto-calibration parameter k5 control register, Address offset: 0xC0 */ + __IO uint32_t ACTEMP; /*!< RTC auto-calibration calculated temperature register, Address offset: 0xC4 */ + __IO uint32_t ACPPM; /*!< RTC auto-calibration calculated PPM register, Address offset: 0xC8 */ + __IO uint32_t WKUCNTR; /*!< RTC current WKUCNT counter value read-out register., Address offset: 0xCC */ + __IO uint32_t ACKTEMP; /*!< RTC auto-calibration k temperature section control register,Address offset: 0xD0 */ + //uint32_t RESERVED37[128+15];/*!< Reserved, Address offset: 0xD4-0x3FC */ + //__IO uint32_t RTC_ACOP0_63[64]; /*!< RTC auto-calibration OP0-OP63 register (only for FPGA), Address offset: 0x400-0x4FC */ +} RTC_TypeDef; + +/** + * @brief FLASH + */ +typedef struct +{ + __IO uint32_t STS; /*!< , Address offset: 0x00 */ + __IO uint32_t NVRPASS; /*!< FLASH NVR sector password register, Address offset: 0x04 */ + __IO uint32_t BDPASS; /*!< FLASH Back door register, Address offset: 0x08 */ + __IO uint32_t KEY; /*!< FLASH key register, Address offset: 0x0C */ + __IO uint32_t INT; /*!< FLASH Checksum interrupt status, Address offset: 0x10 */ + __IO uint32_t CSSADDR; /*!< FLASH Checksum start address, Address offset: 0x14 */ + __IO uint32_t CSEADDR; /*!< FLASH Checksum end address, Address offset: 0x18 */ + __IO uint32_t CSVALUE; /*!< FLASH Checksum value register, Address offset: 0x1C */ + __IO uint32_t CSCVALUE; /*!< FLASH Checksum compare value register, Address offset: 0x20 */ + __IO uint32_t PASS; /*!< FLASH password register, Address offset: 0x24 */ + __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x28 */ + __IO uint32_t PGADDR; /*!< FLASH program address register, Address offset: 0x2C */ + __IO uint32_t PGDATA; /*!< FLASH program word data register, Address offset: 0x30 */ + __IO uint32_t CONF; /*!< FLASH configuration read/write register, Address offset: 0x34 */ + __IO uint32_t SERASE; /*!< FLASH sector erase control register, Address offset: 0x38 */ + __IO uint32_t CERASE; /*!< FLASH chip erase control register, Address offset: 0x3C */ + __IO uint32_t DSTB; /*!< FLASH deep standby control register, Address offset: 0x40 */ +} FLASH_TypeDef; + + +/** + * @brief General Purpose IO (GPIOB~GPIOF) + */ + +typedef struct +{ + __IO uint32_t OEN; /*!< IOx output enable register, Address offset: 0x00 */ + __IO uint32_t IE; /*!< IOx input enable register, Address offset: 0x04 */ + __IO uint32_t DAT; /*!< IOx data register, Address offset: 0x08 */ + __IO uint32_t ATT; /*!< IOx attribute register, Address offset: 0x0C */ + __IO uint32_t STS; /*!< IOx input status register, Address offset: 0x10 */ +}GPIO_TypeDef; + +/** + * @brief General Purpose IO (GPIOA) + */ +typedef struct +{ + __IO uint32_t OEN; + __IO uint32_t IE; + __IO uint32_t DAT; + __IO uint32_t ATT; + __IO uint32_t WKUEN; + __IO uint32_t STS; + __IO uint32_t INT; + uint32_t RESERVED1; + uint32_t RESERVED2; + uint32_t RESERVED3; + __IO uint32_t SEL; + uint32_t RESERVED[5]; + __IO uint32_t IOANODEG; +} GPIOA_TypeDef; + +/** + * @brief General Purpose IO special function + */ + +typedef struct +{ + __IO uint32_t SELB; /*!< IOB special function select register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, 0x04 */ + uint32_t RESERVED2; /*!< Reserved, 0x08 */ + __IO uint32_t SELE; /*!< IOE special function select register, Address offset: 0x0C */ + uint32_t RESERVED3; /*!< Reserved, 0x10 */ + uint32_t RESERVED4; /*!< Reserved, 0x14 */ + uint32_t RESERVED5; /*!< Reserved, 0x18 */ + uint32_t RESERVED6; /*!< Reserved, 0x1C */ + __IO uint32_t _MISC; /*!< IO misc control register, Address offset: 0x20 */ +}GPIO_AF_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t IE; /*!< DMA interrupt enable register, Address offset:0x00 */ + __IO uint32_t STS; /*!< DMA status register, Address offset:0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t C0CTL; /*!< DMA channel 0 control register, Address offset:0x10 */ + __IO uint32_t C0SRC; /*!< DMA channel 0 source register, Address offset:0x14 */ + __IO uint32_t C0DST; /*!< DMA channel 0 destination register, Address offset:0x18 */ + __IO uint32_t C0LEN; /*!< DMA channel 0 transfer length register, Address offset:0x1C */ + __IO uint32_t C1CTL; /*!< DMA channel 1 control register, Address offset:0x20 */ + __IO uint32_t C1SRC; /*!< DMA channel 1 source register, Address offset:0x24 */ + __IO uint32_t C1DST; /*!< DMA channel 1 destination register, Address offset:0x28 */ + __IO uint32_t C1LEN; /*!< DMA channel 1 transfer length register, Address offset:0x2C */ + __IO uint32_t C2CTL; /*!< DMA channel 2 control register, Address offset:0x30 */ + __IO uint32_t C2SRC; /*!< DMA channel 2 source register, Address offset:0x34 */ + __IO uint32_t C2DST; /*!< DMA channel 2 destination register, Address offset:0x38 */ + __IO uint32_t C2LEN; /*!< DMA channel 2 transfer length register, Address offset:0x3C */ + __IO uint32_t C3CTL; /*!< DMA channel 3 control register, Address offset:0x40 */ + __IO uint32_t C3SRC; /*!< DMA channel 3 source register, Address offset:0x44 */ + __IO uint32_t C3DST; /*!< DMA channel 3 destination register, Address offset:0x48 */ + __IO uint32_t C3LEN; /*!< DMA channel 3 transfer length register, Address offset:0x4C */ + __IO uint32_t AESCTL; /*!< DMA AES control register, Address offset:0x50 */ + uint32_t RESERVED3[3]; /*!< Reserved, 0x54-0x5C */ + __IO uint32_t AESKEY0; /*!< DMA AES key 0 register, Address offset:0x60 */ + __IO uint32_t AESKEY1; /*!< DMA AES key 1 register, Address offset:0x64 */ + __IO uint32_t AESKEY2; /*!< DMA AES key 2 register, Address offset:0x68 */ + __IO uint32_t AESKEY3; /*!< DMA AES key 3 register, Address offset:0x6C */ + __IO uint32_t AESKEY4; /*!< DMA AES key 4 register, Address offset:0x70 */ + __IO uint32_t AESKEY5; /*!< DMA AES key 5 register, Address offset:0x74 */ + __IO uint32_t AESKEY6; /*!< DMA AES key 6 register, Address offset:0x78 */ + __IO uint32_t AESKEY7; /*!< DMA AES key 7 register, Address offset:0x7C */ +} DMA_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t DATA; /*!< UARTx data register, Address offset: 0x00 */ + __IO uint32_t STATE; /*!< UARTx status register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< UARTx control register, Address offset: 0x08 */ + __IO uint32_t INTSTS; /*!< UARTx interrupt status register, Address offset: 0x0C */ + __IO uint32_t BAUDDIV; /*!< UARTx baud rate divide register, Address offset: 0x10 */ + __IO uint32_t CTRL2; /*!< UARTx control register 2, Address offset: 0x14 */ +} UART_TypeDef; + +/** + * @brief UART 32K Controller + */ +typedef struct +{ + __IO uint32_t CTRL0; /*!< UART 32K x control register 0, Address offset: 0x00 */ + __IO uint32_t CTRL1; /*!< UART 32K x control register 1, Address offset: 0x04 */ + __IO uint32_t PHASE; /*!< UART 32K x baud rate control register, Address offset: 0x08 */ + __IO uint32_t DATA; /*!< UART 32K x receive data buffer, Address offset: 0x0C */ + __IO uint32_t STS; /*!< UART 32K x interrupt status register, Address offset: 0x10 */ +} U32K_TypeDef; + +/** + * @brief ISO7816 Controller + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, 0x00 */ + __IO uint32_t BAUDDIVL; /*!< ISO7816 x baud-rate low byte register, Address offset: 0x04 */ + __IO uint32_t BAUDDIVH; /*!< ISO7816 x baud-rate high byte register, Address offset: 0x08 */ + __IO uint32_t DATA; /*!< ISO7816 x data register, Address offset: 0x0C */ + __IO uint32_t INFO; /*!< ISO7816 x information register, Address offset: 0x10 */ + __IO uint32_t CFG; /*!< ISO7816 x control register, Address offset: 0x14 */ + __IO uint32_t CLK; /*!< ISO7816 x clock divider register, Address offset: 0x1C */ +} ISO7816_TypeDef; + +/** + * @brief Timer Controller + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Timer x��s control register, Address offset: 0x00 */ + __IO uint32_t VALUE; /*!< Timer x��s current count register, Address offset: 0x04 */ + __IO uint32_t RELOAD; /*!< Timer x��s reload register, Address offset: 0x08 */ + __IO uint32_t INT; /*!< Timer x��s interrupt status register, Address offset: 0x0C */ +} TMR_TypeDef; + +/** + * @brief PWM Controller + */ +typedef struct +{ + __IO uint32_t CTL; /*!< PWM Timer x��s control register, Address offset: 0x00 */ + __IO uint32_t TAR; /*!< PWM Timer x��s current count register, Address offset: 0x04 */ + __IO uint32_t CCTL0; /*!< PWM Timer x��s compare/capture control register 0, Address offset: 0x08 */ + __IO uint32_t CCTL1; /*!< PWM Timer x��s compare/capture control register 1, Address offset: 0x0C */ + __IO uint32_t CCTL2; /*!< PWM Timer x��s compare/capture control register 2, Address offset: 0x10 */ + __IO uint32_t CCR0; /*!< PWM Timer x��s compare/capture data register 0, Address offset: 0x14 */ + __IO uint32_t CCR1; /*!< PWM Timer x��s compare/capture data register 1, Address offset: 0x18 */ + __IO uint32_t CCR2; /*!< PWM Timer x��s compare/capture data register 2, Address offset: 0x1C */ +} PWM_TypeDef; + +/** + * @brief PWMx selection register + */ +typedef struct +{ + __IO uint32_t OSEL; /*!< PWM output selection register, Address offset: 0x00 */ +// __IO uint32_t ISEL01; /*!< PWM0 and PWM1��s input selection register, Address offset: 0x04 */ +// __IO uint32_t ISEL23; /*!< PWM2 and PWM3��s input selection register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< RESERVED0, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x08 */ +} PWM_MUX_TypeDef; + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t FB[40]; /*!< LCD Frame buffer 0~39 register, Address offset: 0x00-0x9C */ + uint32_t RESERVED1[24]; /*!< Reserved, 0xA0-0xFC */ + __IO uint32_t CTRL; /*!< LCD control register, Address offset: 0x100 */ + __IO uint32_t CTRL2; /*!< LCD control register 2, Address offset: 0x104 */ + __IO uint32_t SEGCTRL0; /*!< LCD segment enable control register 0, Address offset: 0x108 */ + __IO uint32_t SEGCTRL1; /*!< LCD segment enable control register 1, Address offset: 0x10C */ + __IO uint32_t SEGCTRL2; /*!< LCD segment enable control register 2, Address offset: 0x110 */ +}LCD_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< SPI x Control Register, Address offset: 0x00 */ + __IO uint32_t TXSTS; /*!< SPI x Transmit Status Register, Address offset: 0x04 */ + __IO uint32_t TXDAT; /*!< SPI x Transmit FIFO register, Address offset: 0x08 */ + __IO uint32_t RXSTS; /*!< SPI x Receive Status Register, Address offset: 0x0C */ + __IO uint32_t RXDAT; /*!< SPI x Receive FIFO Register, Address offset: 0x10 */ + __IO uint32_t MISC_; /*!< SPI x Misc Control Register, Address offset: 0x14 */ +} SPI_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t DATA; /*!< I2C data register, Address offset: 0x00 */ + __IO uint32_t ADDR; /*!< I2C address register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< I2C control/status register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< I2C status register, Address offset: 0x0C */ + uint32_t RESERVED1; /*!< Reserved, 0x10 */ + uint32_t RESERVED2; /*!< Reserved, 0x14 */ + __IO uint32_t CTRL2; /*!< I2C interrupt enable register, Address offset: 0x18 */ +}I2C_TypeDef; + +/** + * @brief MISC Controller + */ +typedef struct +{ + __IO uint32_t SRAMINT; /*!< SRAM Parity Error Interrupt, Address offset: 0x00 */ + __IO uint32_t SRAMINIT; /*!< SRAM initialize register, Address offset: 0x04 */ + __IO uint32_t PARERR; /*!< SRAM Parity Error address register, Address offset: 0x08 */ + __IO uint32_t IREN; /*!< IR enable control register, Address offset: 0x0C */ + __IO uint32_t DUTYL; /*!< IR Duty low pulse control register, Address offset: 0x10 */ + __IO uint32_t DUTYH; /*!< IR Duty high pulse control register, Address offset: 0x14 */ + __IO uint32_t IRQLAT; /*!< Cortex M0 IRQ latency control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t HIADDR; /*!< AHB invalid access address, Address offset: 0x20 */ + __IO uint32_t PIADDR; /*!< APB invalid access address, Address offset: 0x24 */ +} MISC_TypeDef; + +/** + * @brief MISC2 Controller + */ +typedef struct +{ + __IO uint32_t FLASHWC; /*!< Flash wait cycle register, Address offset: 0x00 */ + __IO uint32_t CLKSEL; /*!< Clock selection register, Address offset: 0x04 */ + __IO uint32_t CLKDIVH; /*!< AHB clock divider control register, Address offset: 0x08 */ + __IO uint32_t CLKDIVP; /*!< APB clock divider control register, Address offset: 0x0C */ + __IO uint32_t HCLKEN; /*!< AHB clock enanle control register, Address offset: 0x10 */ + __IO uint32_t PCLKEN; /*!< APB clock enanle control register, Address offset: 0x14 */ +} MISC2_TypeDef; + +/** + * @brief CRYPT Controller + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< CRYPT control register, Address offset: 0x00 */ + __IO uint32_t PTRA; /*!< CRYPT pointer A, Address offset: 0x04 */ + __IO uint32_t PTRB; /*!< CRYPT pointer B, Address offset: 0x08 */ + __IO uint32_t PTRO; /*!< CRYPT pointer O, Address offset: 0x0C */ + __IO uint32_t CARRY; /*!< CRYPT carry/borrow bit register, Address offset: 0x10 */ +} CRYPT_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x00000000U) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0003FFFFU) /*!< FLASH END address of bank1 */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ + +/*!< Peripheral memory map */ +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00000000U) +#define APBPERIPH_BASE (PERIPH_BASE + 0x00010000U) + +/*!< FLASH */ +#define FLASHSFR_BASE (FLASH_BASE + 0x000FFFBC) + +/*!< AHB peripherals */ +#define GPIO_BASE (AHBPERIPH_BASE + 0x00000000) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000020) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000040) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000060) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x00000080) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x000000A0) +#define GPIOAF_BASE (AHBPERIPH_BASE + 0x000000C0) +#define LCD_BASE (AHBPERIPH_BASE + 0x00002000) +#define CRYPT_BASE (AHBPERIPH_BASE + 0x00006000) + +/*!< APB peripherals */ +#define DMA_BASE (APBPERIPH_BASE + 0x00000000) +#define I2C_BASE (APBPERIPH_BASE + 0x00000800) +#define SPI1_BASE (APBPERIPH_BASE + 0x00001000) +#define UART0_BASE (APBPERIPH_BASE + 0x00001800) +#define UART1_BASE (APBPERIPH_BASE + 0x00001820) +#define UART2_BASE (APBPERIPH_BASE + 0x00001840) +#define UART3_BASE (APBPERIPH_BASE + 0x00001860) +#define UART4_BASE (APBPERIPH_BASE + 0x00001880) +#define UART5_BASE (APBPERIPH_BASE + 0x000018A0) +#define ISO78160_BASE (APBPERIPH_BASE + 0x00002000) +#define ISO78161_BASE (APBPERIPH_BASE + 0x00002040) +#define TMR0_BASE (APBPERIPH_BASE + 0x00002800) +#define TMR1_BASE (APBPERIPH_BASE + 0x00002820) +#define TMR2_BASE (APBPERIPH_BASE + 0x00002840) +#define TMR3_BASE (APBPERIPH_BASE + 0x00002860) +#define PWM0_BASE (APBPERIPH_BASE + 0x00002900) +#define PWM1_BASE (APBPERIPH_BASE + 0x00002920) +#define PWM2_BASE (APBPERIPH_BASE + 0x00002940) +#define PWM3_BASE (APBPERIPH_BASE + 0x00002960) +#define PWMMUX_BASE (APBPERIPH_BASE + 0x000029F0) +#define MISC_BASE (APBPERIPH_BASE + 0x00003000) +#define MISC2_BASE (APBPERIPH_BASE + 0x00003E00) +#define PMU_BASE (APBPERIPH_BASE + 0x00004000) +#define GPIOA_BASE (APBPERIPH_BASE + 0x00004010) +#define PMU_RETRAM_BASE (APBPERIPH_BASE + 0x00004400) +#define U32K0_BASE (APBPERIPH_BASE + 0x00004100) +#define U32K1_BASE (APBPERIPH_BASE + 0x00004180) +#define ANA_BASE (APBPERIPH_BASE + 0x00004200) +#define RETRAM_BASE (APBPERIPH_BASE + 0x00004400) +#define RTC_BASE (APBPERIPH_BASE + 0x00004800) +#define SPI2_BASE (APBPERIPH_BASE + 0x00005800) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define PMU ((PMU_TypeDef *) PMU_BASE) +#define PMU_RETRAM ((PMU_RETRAM_TypeDef *) PMU_RETRAM_BASE) +#define ANA ((ANA_TypeDef *) ANA_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASHSFR_BASE) +#define GPIOA ((GPIOA_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOAF ((GPIO_AF_TypeDef *) GPIOAF_BASE) +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define UART3 ((UART_TypeDef *) UART3_BASE) +#define UART4 ((UART_TypeDef *) UART4_BASE) +#define UART5 ((UART_TypeDef *) UART5_BASE) +#define U32K0 ((U32K_TypeDef *) U32K0_BASE) +#define U32K1 ((U32K_TypeDef *) U32K1_BASE) +#define ISO78160 ((ISO7816_TypeDef *) ISO78160_BASE) +#define ISO78161 ((ISO7816_TypeDef *) ISO78161_BASE) +#define TMR0 ((TMR_TypeDef *) TMR0_BASE) +#define TMR1 ((TMR_TypeDef *) TMR1_BASE) +#define TMR2 ((TMR_TypeDef *) TMR2_BASE) +#define TMR3 ((TMR_TypeDef *) TMR3_BASE) +#define PWM0 ((PWM_TypeDef *) PWM0_BASE) +#define PWM1 ((PWM_TypeDef *) PWM1_BASE) +#define PWM2 ((PWM_TypeDef *) PWM2_BASE) +#define PWM3 ((PWM_TypeDef *) PWM3_BASE) +#define PWMMUX ((PWM_MUX_TypeDef *) PWMMUX_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define I2C ((I2C_TypeDef *) I2C_BASE) +#define MISC ((MISC_TypeDef *) MISC_BASE) +#define MISC2 ((MISC2_TypeDef *) MISC2_BASE) +#define CRYPT ((CRYPT_TypeDef *) CRYPT_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Power Management Unit (PMU) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for PMU_DSLEEPEN register ******************/ +#define PMU_DSLEEPEN_DSLEEP_Pos (0U) +#define PMU_DSLEEPEN_DSLEEP_Msk (0x1U << PMU_DSLEEPEN_DSLEEP_Pos) /*!< 0x00000001 */ +#define PMU_DSLEEPEN_DSLEEP PMU_DSLEEPEN_DSLEEP_Msk /*!< This bit indicates the deep-sleep mode has been entry */ +#define PMU_DSLEEPEN_WKU_Pos (31U) +#define PMU_DSLEEPEN_WKU_Msk (0x1U << PMU_DSLEEPEN_WKU_Pos) /*!< 0x80000000 */ +#define PMU_DSLEEPEN_WKU PMU_DSLEEPEN_WKU_Msk /*!< Current wake-up signal status, this bit reflect the wake-up status receive by PMU controller */ + +/************** Bits definition for PMU_DSLEEPPASS register ******************/ +#define PMU_DSLEEPPASS_UNLOCK_Pos (0U) +#define PMU_DSLEEPPASS_UNLOCK_Msk (0x1U << PMU_DSLEEPPASS_UNLOCK_Pos) /*!< 0x00000001 */ +#define PMU_DSLEEPPASS_UNLOCK PMU_DSLEEPPASS_UNLOCK_Msk /*!< This bit indicates the entry of deep-sleep mode has been unlocked and is ready to entry deep-sleep mode */ + +/************** Bits definition for PMU_CONTROL register ******************/ +#define PMU_CONTROL_INT_IOA_EN_Pos (0U) +#define PMU_CONTROL_INT_IOA_EN_Msk (0x1U << PMU_CONTROL_INT_IOA_EN_Pos) /*!< 0x00000001 */ +#define PMU_CONTROL_INT_IOA_EN PMU_CONTROL_INT_IOA_EN_Msk /*!< PMU��s interrupt enable register. This bit is used to control the interrupt signal output to CPU */ +#define PMU_CONTROL_RTCLK_SEL_Pos (1U) +#define PMU_CONTROL_RTCLK_SEL_Msk (0x1U << PMU_CONTROL_RTCLK_SEL_Pos) /*!< 0x00000002 */ +#define PMU_CONTROL_RTCLK_SEL PMU_CONTROL_RTCLK_SEL_Msk /*!< RTC Clock selection */ +#define PMU_CONTROL_INT_32K_EN_Pos (2U) +#define PMU_CONTROL_INT_32K_EN_Msk (0x1U << PMU_CONTROL_INT_32K_EN_Pos) /*!< 0x00000004 */ +#define PMU_CONTROL_INT_32K_EN PMU_CONTROL_INT_32K_EN_Msk /*!< 32K XTAL absent interrupt enable register. This bit is used to control the interrupt signal output to CPU */ +#define PMU_CONTROL_INT_6M_EN_Pos (3U) +#define PMU_CONTROL_INT_6M_EN_Msk (0x1U << PMU_CONTROL_INT_6M_EN_Pos) /*!< 0x00000008 */ +#define PMU_CONTROL_INT_6M_EN PMU_CONTROL_INT_6M_EN_Msk /*!< 6.5536M XTAL absent interrupt enable register */ +#define PMU_CONTROL_PLLH_SEL_Pos (4U) +#define PMU_CONTROL_PLLH_SEL_Msk (0x1U << PMU_CONTROL_PLLH_SEL_Pos) /*!< 0x00000010 */ +#define PMU_CONTROL_PLLH_SEL PMU_CONTROL_PLLH_SEL_Msk /*!< High speed PLL input clock selection */ +#define PMU_CONTROL_PLLL_SEL_Pos (5U) +#define PMU_CONTROL_PLLL_SEL_Msk (0x1U << PMU_CONTROL_PLLL_SEL_Pos) /*!< 0x00000020 */ +#define PMU_CONTROL_PLLL_SEL PMU_CONTROL_PLLL_SEL_Msk /*!< Low speed PLL input clock selection */ +//#define PMU_CONTROL_PD_WKUEN_Pos (6U) +//#define PMU_CONTROL_PD_WKUEN_Msk (0x1U << PMU_CONTROL_PD_WKUEN_Pos) /*!< 0x00000040 */ +//#define PMU_CONTROL_PD_WKUEN PMU_CONTROL_PD_WKUEN_Msk /*!< Wake-up enable/disable when main power is off */ +//#define PMU_CONTROL_PWUPCYC_Pos (8U) +//#define PMU_CONTROL_PWUPCYC_Msk (0xFFU << PMU_CONTROL_PWUPCYC_Pos) /*!< 0x0000FF00 */ +//#define PMU_CONTROL_PWUPCYC PMU_CONTROL_PWUPCYC_Msk /*!< Power-up cycle count, this register control the power-up wait time when a wake-up even is received. The unit is 32K clock period */ +//#define PMU_CONTROL_NOWAITLOCK_Pos (17U) +//#define PMU_CONTROL_NOWAITLOCK_Msk (0x1U << PMU_CONTROL_NOWAITLOCK_Pos) /*!< 0x00020000 */ +//#define PMU_CONTROL_NOWAITLOCK PMU_CONTROL_NOWAITLOCK_Msk /*!< if the hardware will wait for PLLL��s lock signal when switch clock source to PLLL/PLLH */ + +/************** Bits definition for PMU_STS register ******************/ +#define PMU_STS_INT_32K_Pos (0U) +#define PMU_STS_INT_32K_Msk (0x1U << PMU_STS_INT_32K_Pos) /*!< 0x00000001 */ +#define PMU_STS_INT_32K PMU_STS_INT_32K_Msk /*!< This bit represents the 32K crystal absent interrupt status. When this bit is set to 1, it means the 32K crystal is removed or broken. Write 1 to this bit can clear this flag to 0 */ +#define PMU_STS_INT_6M_Pos (1U) +#define PMU_STS_INT_6M_Msk (0x1U << PMU_STS_INT_6M_Pos) /*!< 0x00000002 */ +#define PMU_STS_INT_6M PMU_STS_INT_6M_Msk /*!< This bit represents the 6.55364M crystal absent interrupt status. When this bit is set to 1, it means the 6.55364M crystal is removed or broken. Write 1 to this bit can clear this flag to 0 */ +#define PMU_STS_EXIST_32K_Pos (2U) +#define PMU_STS_EXIST_32K_Msk (0x1U << PMU_STS_EXIST_32K_Pos) /*!< 0x00000004 */ +#define PMU_STS_EXIST_32K PMU_STS_EXIST_32K_Msk /*!< 32K XTAL exist status register. This bit is represent 32K XTAL is existed or absent */ +#define PMU_STS_EXIST_6M_Pos (3U) +#define PMU_STS_EXIST_6M_Msk (0x1U << PMU_STS_EXIST_6M_Pos) /*!< 0x00000008 */ +#define PMU_STS_EXIST_6M PMU_STS_EXIST_6M_Msk /*!< 6.5536M XTAL exist status register. This bit is represent 6.5536M XTAL is existed or absent */ +#define PMU_STS_EXTRST_Pos (4U) +#define PMU_STS_EXTRST_Msk (0x1U << PMU_STS_EXTRST_Pos) /*!< 0x00000010 */ +#define PMU_STS_EXTRST PMU_STS_EXTRST_Msk /*!< This bit indicated if the last interrupt is cause by external reset signal. Write 1 to clear this bit */ +#define PMU_STS_PORST_Pos (5U) +#define PMU_STS_PORST_Msk (0x1U << PMU_STS_PORST_Pos) /*!< 0x00000020 */ +#define PMU_STS_PORST PMU_STS_PORST_Msk /*!< This bit indicated if the last reset is cause by internal power-on reset signal. Write 1 to clear this bit */ +#define PMU_STS_DPORST_Pos (6U) +#define PMU_STS_DPORST_Msk (0x1U << PMU_STS_DPORST_Pos) /*!< 0x00000040 */ +#define PMU_STS_DPORST PMU_STS_DPORST_Msk /*!< This bit indicated if the last reset is cause by internal digital power-on reset signal. Write 1 to clear this bit */ +#define PMU_STS_MODE_Pos (24U) +#define PMU_STS_MODE_Msk (0x1U << PMU_STS_MODE_Pos) /*!< 0x01000000 */ +#define PMU_STS_MODE PMU_STS_MODE_Msk /*!< This register shows the current status of MODE pin */ + +/************** Bits definition for PMU_IOAOEN register ******************/ +#define PMU_IOAOEN_Pos (0U) +#define PMU_IOAOEN_Msk (0xFFFFU << PMU_IOAOEN_Pos) /*!< 0x0000FFFF */ +#define PMU_IOAOEN_IOAOEN PMU_IOAOEN_Msk /*!< Each bit control the IOA��s output enable signal */ + +/************** Bits definition for PMU_IOAIE register ******************/ +#define PMU_IOAIE_Pos (0U) +#define PMU_IOAIE_Msk (0xFFFFU << PMU_IOAIE_Pos) /*!< 0x0000FFFF */ +#define PMU_IOAIE_IOAIE PMU_IOAIE_Msk /*!< Each bit control the IOA��s input enable signal */ + +/************** Bits definition for PMU_IOADAT register ******************/ +#define PMU_IOADAT_Pos (0U) +#define PMU_IOADAT_Msk (0xFFFFU << PMU_IOADAT_Pos) /*!< 0x0000FFFF */ +#define PMU_IOADAT_IOADAT PMU_IOADAT_Msk /*!< Each bit control the IOA��s output data and pull low/high function */ + +/************** Bits definition for PMU_IOAATT register ******************/ +#define PMU_IOAATT_Pos (0U) +#define PMU_IOAATT_Msk (0xFFFFU << PMU_IOAATT_Pos) /*!< 0x0000FFFF */ +#define PMU_IOAATT_IOAATT PMU_IOAATT_Msk /*!< Each bit control the IOA��s attribute and pull low/high function */ + +/************** Bits definition for PMU_IOAWKUEN register ******************/ +#define PMU_IOAWKUEN_Pos (0U) +#define PMU_IOAWKUEN_Msk (0xFFFFFFFFU << PMU_IOAWKUEN_Pos) /*!< 0xFFFFFFFF */ +#define PMU_IOAWKUEN_IOAWKUEN PMU_IOAWKUEN_Msk /*!< Every 2 bits control the IOA��s wake up function */ + +/************** Bits definition for PMU_IOASTS register ******************/ +#define PMU_IOASTS_Pos (0U) +#define PMU_IOASTS_Msk (0xFFFFU << PMU_IOASTS_Pos) /*!< 0x0000FFFF */ +#define PMU_IOASTS_IOASTS PMU_IOASTS_Msk /*!< Each bit represents the current IOA��s input data value */ + +/************** Bits definition for PMU_IOAINT register ******************/ +#define PMU_IOAINT_Pos (0U) +#define PMU_IOAINT_Msk (0xFFFFU << PMU_IOAINT_Pos) /*!< 0x0000FFFF */ +#define PMU_IOAINT_IOAINT PMU_IOAINT_Msk /*!< Each bit represents the IOA��s interrupt status. The corresponded bit will be set to 1 when corresponded wake-up event is detected. This register can be clear to 0 by writing corresponded bit to 1 */ + +/************** Bits definition for PMU_IOADR register ******************/ +#define PMU_IOADR_IOA0DR_Pos (0U) +#define PMU_IOADR_IOA0DR_Msk (0x1U << PMU_IOADR_IOA0DR_Pos) /*!< 0x00000001 */ +#define PMU_IOADR_IOA0DR PMU_IOADR_IOA0DR_Msk /*!< IOA0��s driving strength setting, change to this register will change all setting of IOA0~IOA15 */ +#define PMU_IOADR_IOAXDR_Pos (1U) +#define PMU_IOADR_IOAXDR_Msk (0x7FFFU << PMU_IOADR_IOAXDR_Pos) /*!< 0x0000FFFE */ +#define PMU_IOADR_IOAXDR PMU_IOADR_IOAXDR_Msk /*!< Each bit represent the current driving strength setting of IOA1~IOA15 */ + +/************** Bits definition for PMU_IOASEL register ******************/ +#define PMU_IOASEL_SEL3_Pos (3U) +#define PMU_IOASEL_SEL3_Msk (0x1U << PMU_IOASEL_SEL3_Pos) /*!< 0x00000008 */ +#define PMU_IOASEL_SEL3 PMU_IOASEL_SEL3_Msk /*!< IOA3 special function select register */ +#define PMU_IOASEL_SEL6_Pos (6U) +#define PMU_IOASEL_SEL6_Msk (0x1U << PMU_IOASEL_SEL6_Pos) /*!< 0x00000040 */ +#define PMU_IOASEL_SEL6 PMU_IOASEL_SEL6_Msk /*!< IOA6 special function select register */ +#define PMU_IOASEL_SEL7_Pos (7U) +#define PMU_IOASEL_SEL7_Msk (0x1U << PMU_IOASEL_SEL7_Pos) /*!< 0x00000080 */ +#define PMU_IOASEL_SEL7 PMU_IOASEL_SEL7_Msk /*!< IOA7 special function select register */ + +/************** Bits definition for PMU_WDTPASS register ******************/ +#define PMU_WDTPASS_UNLOCK_Pos (0U) +#define PMU_WDTPASS_UNLOCK_Msk (0x1U << PMU_WDTPASS_UNLOCK_Pos) /*!< 0x00000001 */ +#define PMU_WDTPASS_UNLOCK PMU_WDTPASS_UNLOCK_Msk /*!< This bit indicates the watch dog timer enable register has been unlocked and is ready to change the watch dog enable control register */ + +/************** Bits definition for PMU_WDTEN register ******************/ +#define PMU_WDTEN_WDTEN_Pos (0U) +#define PMU_WDTEN_WDTEN_Msk (0x1U << PMU_WDTEN_WDTEN_Pos) /*!< 0x00000001 */ +#define PMU_WDTEN_WDTEN PMU_WDTEN_WDTEN_Msk /*!< This bit indicates the watch dog timer is enable. To change the value of this register, UNLOCK bit of MISC_WDTPASS should be set to 1 first */ +#define PMU_WDTEN_WDTSEL_Pos (2U) +#define PMU_WDTEN_WDTSEL_Msk (0x3U << PMU_WDTEN_WDTSEL_Pos) /*!< 0x0000000C */ +#define PMU_WDTEN_WDTSEL PMU_WDTEN_WDTSEL_Msk /*!< This register is used to control the WDT counting period */ +#define PMU_WDTEN_WDTSEL_0 (0x0U << PMU_WDTEN_WDTSEL_Pos) +#define PMU_WDTEN_WDTSEL_1 (0x1U << PMU_WDTEN_WDTSEL_Pos) +#define PMU_WDTEN_WDTSEL_2 (0x2U << PMU_WDTEN_WDTSEL_Pos) +#define PMU_WDTEN_WDTSEL_3 (0x3U << PMU_WDTEN_WDTSEL_Pos) + + +/************** Bits definition for PMU_WDTCLR register ******************/ +#define PMU_WDTCLR_WDTCNT_Pos (0U) +#define PMU_WDTCLR_WDTCNT_Msk (0xFFFFU << PMU_WDTCLR_WDTCNT_Pos) /*!< 0x0000FFFF */ +#define PMU_WDTCLR_WDTCNT PMU_WDTCLR_WDTCNT_Msk /*!< This register shows the current counter value of wat dog timer. When this timer count to limit value set by WDTSEL, the WDT will issue a system reset */ + +/************** Bits definition for PMU_WDTSTS register ******************/ +//#define PMU_WDTSTS_WDTSTS_Pos (0U) +//#define PMU_WDTSTS_WDTSTS_Msk (0x1U << PMU_WDTSTS_WDTSTS_Pos) /*!< 0x00000001 */ +//#define PMU_WDTSTS_WDTSTS PMU_WDTSTS_WDTSTS_Msk /*!< This register indicates that a WDT reset has happened. Programmer can read this bit to know if this time is the WDT reset. Write 1 to this bit can clear this flag */ + +/******************************************************************************/ +/* */ +/* Embedded 256 Bytes Retention SRAM (PMU_RAM) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for PMU_RAMx register ******************/ +#define PMU_RAM_RAM_Pos (0U) +#define PMU_RAM_RAM_Msk (0xFFFFFFFFU << PMU_RAM_RAM_Pos) /*!< 0xFFFFFFFF */ +#define PMU_RAM_RAM PMU_RAM_RAM_Msk /*!< There is a 256 bytes (64x32) SRAM embedded in the PMU controller. This RAM can keep data during deep-sleep mode. Only word access is allowed to these ports */ + +/******************************************************************************/ +/* */ +/* Analog controller (ANA) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for ANA_REG0 register ******************/ +//#define ANA_REG0_CURRIT_Pos (0U) +//#define ANA_REG0_CURRIT_Msk (0x3U << ANA_REG0_CURRIT_Pos) /*!< 0x00000003 */ +//#define ANA_REG0_CURRIT ANA_REG0_CURRIT_Msk /*!< ADC overall bias current trim */ +//#define ANA_REG0_CURRIT_0 (0x0U << ANA_REG0_CURRIT_Pos) +//#define ANA_REG0_CURRIT_1 (0x1U << ANA_REG0_CURRIT_Pos) +//#define ANA_REG0_CURRIT_2 (0x2U << ANA_REG0_CURRIT_Pos) +//#define ANA_REG0_CURRIT_3 (0x3U << ANA_REG0_CURRIT_Pos) +//#define ANA_REG0_ADIT1_Pos (2U) +//#define ANA_REG0_ADIT1_Msk (0x3U << ANA_REG0_ADIT1_Pos) /*!< 0x0000000C */ +//#define ANA_REG0_ADIT1 ANA_REG0_ADIT1_Msk /*!< Current trim for 1st stage of ADC */ +//#define ANA_REG0_ADIT1_0 (0x0U << ANA_REG0_ADIT1_Pos) +//#define ANA_REG0_ADIT1_1 (0x1U << ANA_REG0_ADIT1_Pos) +//#define ANA_REG0_ADIT1_2 (0x2U << ANA_REG0_ADIT1_Pos) +//#define ANA_REG0_ADIT1_3 (0x3U << ANA_REG0_ADIT1_Pos) +//#define ANA_REG0_ADIT2_Pos (4U) +//#define ANA_REG0_ADIT2_Msk (0x3U << ANA_REG0_ADIT2_Pos) /*!< 0x00000030 */ +//#define ANA_REG0_ADIT2 ANA_REG0_ADIT2_Msk /*!< Current trim for 2st stage of ADC */ +//#define ANA_REG0_ADIT2_0 (0x0U << ANA_REG0_ADIT2_Pos) +//#define ANA_REG0_ADIT2_1 (0x1U << ANA_REG0_ADIT2_Pos) +//#define ANA_REG0_ADIT2_2 (0x2U << ANA_REG0_ADIT2_Pos) +//#define ANA_REG0_ADIT2_3 (0x3U << ANA_REG0_ADIT2_Pos) +//#define ANA_REG0_REFBIT_Pos (6U) +//#define ANA_REG0_REFBIT_Msk (0x1U << ANA_REG0_REFBIT_Pos) /*!< 0x00000040 */ +//#define ANA_REG0_REFBIT ANA_REG0_REFBIT_Msk /*!< Current trim for ADC ref buffer */ +//#define ANA_REG0_ADQIT_Pos (7U) +//#define ANA_REG0_ADQIT_Msk (0x1U << ANA_REG0_ADQIT_Pos) /*!< 0x00000080 */ +//#define ANA_REG0_ADQIT ANA_REG0_ADQIT_Msk /*!< Current trim for ADC CMP */ + +/************** Bits definition for ANA_REG1 register ******************/ +//#define ANA_REG1_ADC_SEL_Pos (0U) +//#define ANA_REG1_ADC_SEL_Msk (0xFU << ANA_REG1_ADC_SEL_Pos) /*!< 0x0000000F */ +//#define ANA_REG1_ADC_SEL ANA_REG1_ADC_SEL_Msk /*!< This register represents current ADC sampling channels. The ADC sampling channels are controlled by ADC controller */ +//#define ANA_REG1_ADC_SEL_0 (0x0U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_1 (0x1U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_2 (0x2U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_3 (0x3U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_4 (0x4U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_5 (0x5U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_6 (0x6U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_7 (0x7U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_8 (0x8U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_9 (0x9U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_10 (0xAU << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_11 (0xBU << ANA_REG1_ADC_SEL_Pos) +#define ANA_REG1_RESDIV_Pos (4U) +#define ANA_REG1_RESDIV_Msk (0x1U << ANA_REG1_RESDIV_Pos) /*!< 0x00000010 */ +#define ANA_REG1_RESDIV ANA_REG1_RESDIV_Msk /*!< Enable resistor division for M ADC��s input signal */ +#define ANA_REG1_GDE4_Pos (5U) +#define ANA_REG1_GDE4_Msk (0x1U << ANA_REG1_GDE4_Pos) /*!< 0x00000020 */ +#define ANA_REG1_GDE4 ANA_REG1_GDE4_Msk /*!< Enable cap division for M ADC��s input signal */ +//#define ANA_REG1_PRES_EN_Pos (6U) +//#define ANA_REG1_PRES_EN_Msk (0x1U << ANA_REG1_PRES_EN_Pos) /*!< 0x00000040 */ +//#define ANA_REG1_PRES_EN ANA_REG1_PRES_EN_Msk /*!< Enable pull down resistor for M ADC��s input signal */ +//#define ANA_REG1_ADCRSTM_Pos (7U) +//#define ANA_REG1_ADCRSTM_Msk (0x1U << ANA_REG1_ADCRSTM_Pos) /*!< 0x00000080 */ +//#define ANA_REG1_ADCRSTM ANA_REG1_ADCRSTM_Msk /*!< */ + +/************** Bits definition for ANA_REG2 register ******************/ +#define ANA_REG2_CMP1_SEL_Pos (0U) +#define ANA_REG2_CMP1_SEL_Msk (0x3U << ANA_REG2_CMP1_SEL_Pos) /*!< 0x00000003 */ +#define ANA_REG2_CMP1_SEL ANA_REG2_CMP1_SEL_Msk /*!< Signal source selection of comparator A */ +#define ANA_REG2_CMP1_SEL_0 (0x0U << ANA_REG2_CMP1_SEL_Pos) +#define ANA_REG2_CMP1_SEL_1 (0x1U << ANA_REG2_CMP1_SEL_Pos) +#define ANA_REG2_CMP1_SEL_2 (0x2U << ANA_REG2_CMP1_SEL_Pos) +#define ANA_REG2_CMP1_SEL_3 (0x3U << ANA_REG2_CMP1_SEL_Pos) +#define ANA_REG2_CMP2_SEL_Pos (2U) +#define ANA_REG2_CMP2_SEL_Msk (0x3U << ANA_REG2_CMP2_SEL_Pos) /*!< 0x0000000C */ +#define ANA_REG2_CMP2_SEL ANA_REG2_CMP2_SEL_Msk /*!< Signal source selection of comparator B */ +#define ANA_REG2_REFSEL_CMP1_Pos (4U) +#define ANA_REG2_REFSEL_CMP1_Msk (0x1U << ANA_REG2_REFSEL_CMP1_Pos) /*!< 0x00000010 */ +#define ANA_REG2_REFSEL_CMP1 ANA_REG2_REFSEL_CMP1_Msk /*!< REF selection of CMP1 */ +#define ANA_REG2_REFSEL_CMP2_Pos (5U) +#define ANA_REG2_REFSEL_CMP2_Msk (0x1U << ANA_REG2_REFSEL_CMP2_Pos) /*!< 0x00000020 */ +#define ANA_REG2_REFSEL_CMP2 ANA_REG2_REFSEL_CMP2_Msk /*!< REF selection of CMP2 */ +//#define ANA_REG2_TEMPPDN_Pos (6U) +//#define ANA_REG2_TEMPPDN_Msk (0x1U << ANA_REG2_TEMPPDN_Pos) /*!< 0x00000040 */ +//#define ANA_REG2_TEMPPDN ANA_REG2_TEMPPDN_Msk /*!< Temperature sensor power down control */ +//#define ANA_REG2_XOLPD_Pos (7U) +//#define ANA_REG2_XOLPD_Msk (0x1U << ANA_REG2_XOLPD_Pos) /*!< 0x00000080 */ +//#define ANA_REG2_XOLPD ANA_REG2_XOLPD_Msk /*!< 32K crystal pad (XOL) power down control */ + +/************** Bits definition for ANA_REG3 register ******************/ +#define ANA_REG3_ADCPDN_Pos (0U) +#define ANA_REG3_ADCPDN_Msk (0x1U << ANA_REG3_ADCPDN_Pos) /*!< 0x00000001 */ +#define ANA_REG3_ADCPDN ANA_REG3_ADCPDN_Msk /*!< ADC power down control signal */ +#define ANA_REG3_CMP1PDN_Pos (1U) +#define ANA_REG3_CMP1PDN_Msk (0x1U << ANA_REG3_CMP1PDN_Pos) /*!< 0x00000002 */ +#define ANA_REG3_CMP1PDN ANA_REG3_CMP1PDN_Msk /*!< CMP1 power down control signal */ +#define ANA_REG3_CMP2PDN_Pos (2U) +#define ANA_REG3_CMP2PDN_Msk (0x1U << ANA_REG3_CMP2PDN_Pos) /*!< 0x00000004 */ +#define ANA_REG3_CMP2PDN ANA_REG3_CMP2PDN_Msk /*!< CMP2 power down control signal */ +#define ANA_REG3_BGPPD_Pos (3U) +#define ANA_REG3_BGPPD_Msk (0x1U << ANA_REG3_BGPPD_Pos) /*!< 0x00000008 */ +#define ANA_REG3_BGPPD ANA_REG3_BGPPD_Msk /*!< BGP power down control signal */ +#define ANA_REG3_RCHPD_Pos (4U) +#define ANA_REG3_RCHPD_Msk (0x1U << ANA_REG3_RCHPD_Pos) /*!< 0x00000010 */ +#define ANA_REG3_RCHPD ANA_REG3_RCHPD_Msk /*!< RCH (6.5536M ROSC) power down control signal */ +#define ANA_REG3_PLLLPDN_Pos (5U) +#define ANA_REG3_PLLLPDN_Msk (0x1U << ANA_REG3_PLLLPDN_Pos) /*!< 0x00000020 */ +#define ANA_REG3_PLLLPDN ANA_REG3_PLLLPDN_Msk /*!< PLLL (32768Hz input PLL) power down control signal */ +#define ANA_REG3_PLLHPDN_Pos (6U) +#define ANA_REG3_PLLHPDN_Msk (0x1U << ANA_REG3_PLLHPDN_Pos) /*!< 0x00000040 */ +#define ANA_REG3_PLLHPDN ANA_REG3_PLLHPDN_Msk /*!< PLLL (6.55364MHz input PLL) power down control signal */ +#define ANA_REG3_XOHPDN_Pos (7U) +#define ANA_REG3_XOHPDN_Msk (0x1U << ANA_REG3_XOHPDN_Pos) /*!< 0x00000080 */ +#define ANA_REG3_XOHPDN ANA_REG3_XOHPDN_Msk /*!< Turn on signal of 6.5536M crystal */ + +/************** Bits definition for ANA_REG4 register ******************/ +//#define ANA_REG4_XRSEL_Pos (0U) +//#define ANA_REG4_XRSEL_Msk (0x3U << ANA_REG4_XRSEL_Pos) /*!< 0x00000003 */ +//#define ANA_REG4_XRSEL ANA_REG4_XRSEL_Msk /*!< After power up, set this register to 0x3 for low power operation */ +//#define ANA_REG4_XOLLP_Pos (2U) +//#define ANA_REG4_XOLLP_Msk (0x1U << ANA_REG4_XOLLP_Pos) /*!< 0x00000004 */ +//#define ANA_REG4_XOLLP ANA_REG4_XOLLP_Msk /*!< 32K crystal pad low power mode, set this bit to 1 after power-up for low power operation */ +//#define ANA_REG4_XCSEL_Pos (3U) +//#define ANA_REG4_XCSEL_Msk (0x1U << ANA_REG4_XCSEL_Pos) /*!< 0x00000008 */ +//#define ANA_REG4_XCSEL ANA_REG4_XCSEL_Msk /*!< 32K crystal capacitance trimming */ +//#define ANA_REG4_XRSEL_H_Pos (4U) +//#define ANA_REG4_XRSEL_H_Msk (0x3U << ANA_REG4_XRSEL_H_Pos) /*!< 0x00000030 */ +//#define ANA_REG4_XRSEL_H ANA_REG4_XRSEL_H_Msk /*!< */ +//#define ANA_REG4_XCSEL_H_Pos (6U) +//#define ANA_REG4_XCSEL_H_Msk (0x3U << ANA_REG4_XCSEL_H_Pos) /*!< 0x000000C0 */ +//#define ANA_REG4_XCSEL_H ANA_REG4_XCSEL_H_Msk /*!< */ + +/************** Bits definition for ANA_REG5 register ******************/ +#define ANA_REG5_IT_CMP1_Pos (0U) +#define ANA_REG5_IT_CMP1_Msk (0x3U << ANA_REG5_IT_CMP1_Pos) /*!< 0x00000003 */ +#define ANA_REG5_IT_CMP1 ANA_REG5_IT_CMP1_Msk /*!< Bias current selection of CMP1 */ +#define ANA_REG5_IT_CMP1_0 (0x0U << ANA_REG5_IT_CMP1_Pos) +#define ANA_REG5_IT_CMP1_1 (0x1U << ANA_REG5_IT_CMP1_Pos) +#define ANA_REG5_IT_CMP1_2 (0x2U << ANA_REG5_IT_CMP1_Pos) +#define ANA_REG5_IT_CMP1_3 (0x3U << ANA_REG5_IT_CMP1_Pos) +#define ANA_REG5_IT_CMP2_Pos (2U) +#define ANA_REG5_IT_CMP2_Msk (0x3U << ANA_REG5_IT_CMP2_Pos) /*!< 0x0000000C */ +#define ANA_REG5_IT_CMP2 ANA_REG5_IT_CMP2_Msk /*!< Bias current selection of CMP2 */ +//#define ANA_REG5_CMP_HYS_Pos (4U) +//#define ANA_REG5_CMP_HYS_Msk (0x1U << ANA_REG5_CMP_HYS_Pos) /*!< 0x00000010 */ +//#define ANA_REG5_CMP_HYS ANA_REG5_CMP_HYS_Msk /*!< HYS voltage selection */ +//#define ANA_REG5_PW2M_EN_Pos (5U) +//#define ANA_REG5_PW2M_EN_Msk (0x1U << ANA_REG5_PW2M_EN_Pos) /*!< 0x00000020 */ +//#define ANA_REG5_PW2M_EN ANA_REG5_PW2M_EN_Msk /*!< Enable power supply to RTC */ +#define ANA_REG5_PD_AVCCDET_Pos (6U) +#define ANA_REG5_PD_AVCCDET_Msk (0x1U << ANA_REG5_PD_AVCCDET_Pos) /*!< 0x00000040 */ +#define ANA_REG5_PD_AVCCDET ANA_REG5_PD_AVCCDET_Msk /*!< Power down low voltage detector */ +//#define ANA_REG5_RTCLDOPD_EN_Pos (7U) +//#define ANA_REG5_RTCLDOPD_EN_Msk (0x1U << ANA_REG5_RTCLDOPD_EN_Pos) /*!< 0x00000080 */ +//#define ANA_REG5_RTCLDOPD_EN ANA_REG5_RTCLDOPD_EN_Msk /*!< Enable PD RTCLDO when main power is on */ + +/************** Bits definition for ANA_REG6 register ******************/ +#define ANA_REG6_LCD_BMODE_Pos (0U) +#define ANA_REG6_LCD_BMODE_Msk (0x1U << ANA_REG6_LCD_BMODE_Pos) /*!< 0x00000001 */ +#define ANA_REG6_LCD_BMODE ANA_REG6_LCD_BMODE_Msk /*!< LCD BIAS mode selection */ +#define ANA_REG6_VLCD_Pos (1U) +#define ANA_REG6_VLCD_Msk (0xFU << ANA_REG6_VLCD_Pos) /*!< 0x0000001E */ +#define ANA_REG6_VLCD ANA_REG6_VLCD_Msk /*!< LCD driving voltage */ +#define ANA_REG6_VLCD_0 (0x0U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_1 (0x1U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_2 (0x2U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_3 (0x3U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_4 (0x4U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_5 (0x5U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_6 (0x6U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_7 (0x7U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_8 (0x8U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_9 (0x9U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_A (0xAU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_B (0xBU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_C (0xCU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_D (0xDU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_E (0xEU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_F (0xFU << ANA_REG6_VLCD_Pos) +//#define ANA_REG6_LCDVOUT_Pos (5U) +//#define ANA_REG6_LCDVOUT_Msk (0x1U << ANA_REG6_LCDVOUT_Pos) /*!< 0x00000020 */ +//#define ANA_REG6_LCDVOUT ANA_REG6_LCDVOUT_Msk /*!< LCD voltage output enable */ +//#define ANA_REG6_BAT1DISC_Pos (6U) +//#define ANA_REG6_BAT1DISC_Msk (0x1U << ANA_REG6_BAT1DISC_Pos) /*!< 0x00000040 */ +//#define ANA_REG6_BAT1DISC ANA_REG6_BAT1DISC_Msk /*!< Discharge the BAT1 battery */ +#define ANA_REG6_BATRTCDISC_Pos (7U) +#define ANA_REG6_BATRTCDISC_Msk (0x1U << ANA_REG6_BATRTCDISC_Pos) /*!< 0x00000080 */ +#define ANA_REG6_BATRTCDISC ANA_REG6_BATRTCDISC_Msk /*!< Discharge the RTCBAT battery */ + +/************** Bits definition for ANA_REG7 register ******************/ +//#define ANA_REG7_ANAOUT_EN_Pos (0U) +//#define ANA_REG7_ANAOUT_EN_Msk (0x1U << ANA_REG7_ANAOUT_EN_Pos) /*!< 0x00000001 */ +//#define ANA_REG7_ANAOUT_EN ANA_REG7_ANAOUT_EN_Msk /*!< Enable analog signal out */ +//#define ANA_REG7_P10ENN_Pos (1U) +//#define ANA_REG7_P10ENN_Msk (0x1U << ANA_REG7_P10ENN_Pos) /*!< 0x00000002 */ +//#define ANA_REG7_P10ENN ANA_REG7_P10ENN_Msk /*!< */ +//#define ANA_REG7_MADCHOPN_Pos (2U) +//#define ANA_REG7_MADCHOPN_Msk (0x1U << ANA_REG7_MADCHOPN_Pos) /*!< 0x00000004 */ +//#define ANA_REG7_MADCHOPN ANA_REG7_MADCHOPN_Msk /*!< */ +//#define ANA_REG7_TMPCKOFF_Pos (3U) +//#define ANA_REG7_TMPCKOFF_Msk (0x1U << ANA_REG7_TMPCKOFF_Pos) /*!< 0x00000008 */ +//#define ANA_REG7_TMPCKOFF ANA_REG7_TMPCKOFF_Msk /*!< */ +//#define ANA_REG7_LDOISEL_Pos (4U) +//#define ANA_REG7_LDOISEL_Msk (0x1U << ANA_REG7_LDOISEL_Pos) /*!< 0x00000010 */ +//#define ANA_REG7_LDOISEL ANA_REG7_LDOISEL_Msk /*!< */ +//#define ANA_REG7_SWT2VDD_Pos (5U) +//#define ANA_REG7_SWT2VDD_Msk (0x1U << ANA_REG7_SWT2VDD_Pos) /*!< 0x00000020 */ +//#define ANA_REG7_SWT2VDD ANA_REG7_SWT2VDD_Msk /*!< */ +//#define ANA_REG7_X32KIN_EN_Pos (6U) +//#define ANA_REG7_X32KIN_EN_Msk (0x1U << ANA_REG7_X32KIN_EN_Pos) /*!< 0x00000040 */ +//#define ANA_REG7_X32KIN_EN ANA_REG7_X32KIN_EN_Msk /*!< Additional X32K pad input enable */ +//#define ANA_REG7_CLKOSEL_Pos (7U) +//#define ANA_REG7_CLKOSEL_Msk (0x1U << ANA_REG7_CLKOSEL_Pos) /*!< 0x00000080 */ +//#define ANA_REG7_CLKOSEL ANA_REG7_CLKOSEL_Msk /*!< */ + +/************** Bits definition for ANA_REG8 register ******************/ +//#define ANA_REG8_DVCCSEL_Pos (0U) +//#define ANA_REG8_DVCCSEL_Msk (0x3U << ANA_REG8_DVCCSEL_Pos) /*!< 0x00000003 */ +//#define ANA_REG8_DVCCSEL ANA_REG8_DVCCSEL_Msk /*!< Trimming of DVCC */ +//#define ANA_REG8_DVCCSEL_0 (0x0U << ANA_REG8_DVCCSEL_Pos) +//#define ANA_REG8_DVCCSEL_1 (0x1U << ANA_REG8_DVCCSEL_Pos) +//#define ANA_REG8_DVCCSEL_2 (0x2U << ANA_REG8_DVCCSEL_Pos) +//#define ANA_REG8_DVCCSEL_3 (0x3U << ANA_REG8_DVCCSEL_Pos) +//#define ANA_REG8_AVCCSEL_Pos (2U) +//#define ANA_REG8_AVCCSEL_Msk (0x3U << ANA_REG8_AVCCSEL_Pos) /*!< 0x0000000C */ +//#define ANA_REG8_AVCCSEL ANA_REG8_AVCCSEL_Msk /*!< Trimming of AVCC */ +#define ANA_REG8_VDDPVDSEL_Pos (4U) +#define ANA_REG8_VDDPVDSEL_Msk (0x7U << ANA_REG8_VDDPVDSEL_Pos) /*!< 0x00000070 */ +#define ANA_REG8_VDDPVDSEL ANA_REG8_VDDPVDSEL_Msk /*!< Voltage selection of power detector, the setting in this register will affect the status of QPWRDN */ +#define ANA_REG8_VDDPVDSEL_0 (0x0U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_1 (0x1U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_2 (0x2U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_3 (0x3U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_4 (0x4U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_5 (0x5U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_6 (0x6U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_7 (0x7U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_PD_AVCCLDO_Pos (7U) +#define ANA_REG8_PD_AVCCLDO_Msk (0x1U << ANA_REG8_PD_AVCCLDO_Pos) /*!< 0x00000080 */ +#define ANA_REG8_PD_AVCCLDO ANA_REG8_PD_AVCCLDO_Msk /*!< AVCCLDO Power-down control signal */ + +/************** Bits definition for ANA_REG9 register ******************/ +#define ANA_REG9_PLLLSEL_Pos (0U) +#define ANA_REG9_PLLLSEL_Msk (0x7U << ANA_REG9_PLLLSEL_Pos) /*!< 0x00000007 */ +#define ANA_REG9_PLLLSEL ANA_REG9_PLLLSEL_Msk /*!< Clk frequency selection of PLLL */ +#define ANA_REG9_PLLLSEL_26M (0x0U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_13M (0x1U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_6_5M (0x2U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_3_2M (0x3U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_800K (0x5U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_400K (0x6U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_200K (0x7U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLHSEL_Pos (3U) +#define ANA_REG9_PLLHSEL_Msk (0xFU << ANA_REG9_PLLHSEL_Pos) /*!< 0x00000078 */ +#define ANA_REG9_PLLHSEL ANA_REG9_PLLHSEL_Msk /*!< Clk frequency selection of PLLH */ +#define ANA_REG9_PLLHSEL_X2 (0xCU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X2_5 (0xDU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X3 (0xEU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X3_5 (0xFU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X4 (0x0U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X4_5 (0x1U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X5 (0x2U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X6 (0x4U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X6_5 (0x5U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X7 (0x6U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X7_5 (0x7U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PDDET_Pos (7U) +#define ANA_REG9_PDDET_Msk (0x1U << ANA_REG9_PDDET_Pos) /*!< 0x00000080 */ +#define ANA_REG9_PDDET ANA_REG9_PDDET_Msk /*!< */ + +/************** Bits definition for ANA_REGA register ******************/ +//#define ANA_REGA_VDD2_OFF_Pos (0U) +//#define ANA_REGA_VDD2_OFF_Msk (0x1U << ANA_REGA_VDD2_OFF_Pos) /*!< 0x00000001 */ +//#define ANA_REGA_VDD2_OFF ANA_REGA_VDD2_OFF_Msk /*!< This register is controlled by hardware and should be set to 0 for all the time */ +//#define ANA_REGA_VDD3_OFF_Pos (1U) +//#define ANA_REGA_VDD3_OFF_Msk (0x1U << ANA_REGA_VDD3_OFF_Pos) /*!< 0x00000002 */ +//#define ANA_REGA_VDD3_OFF ANA_REGA_VDD3_OFF_Msk /*!< This register is controlled by hardware and should be set to 0 for all the time */ +////#define ANA_REGA_RTCVSEL_Pos (2U) +//#define ANA_REGA_RTCVSEL_Msk (0x1U << ANA_REGA_RTCVSEL_Pos) /*!< 0x00000004 */ +//#define ANA_REGA_RTCVSEL ANA_REGA_RTCVSEL_Msk /*!< RTC LDO voltage selection */ +//#define ANA_REGA_SWT2BAT1_Pos (3U) +//#define ANA_REGA_SWT2BAT1_Msk (0x1U << ANA_REGA_SWT2BAT1_Pos) /*!< 0x00000008 */ +//#define ANA_REGA_SWT2BAT1 ANA_REGA_SWT2BAT1_Msk /*!< Switching from VDCIN to BAT1 manually */ +//#define ANA_REGA_PSLSEL_Pos (4U) +//#define ANA_REGA_PSLSEL_Msk (0x1U << ANA_REGA_PSLSEL_Pos) /*!< 0x00000010 */ +//#define ANA_REGA_PSLSEL ANA_REGA_PSLSEL_Msk /*!< power switch level selection */ +//#define ANA_REGA_PD_PORH_Pos (5U) +//#define ANA_REGA_PD_PORH_Msk (0x1U << ANA_REGA_PD_PORH_Pos) /*!< 0x00000020 */ +//#define ANA_REGA_PD_PORH ANA_REGA_PD_PORH_Msk /*!< PD POR_H module, output ��1�� when PD */ +//#define ANA_REGA_PD_RCL_Pos (6U) +//#define ANA_REGA_PD_RCL_Msk (0x1U << ANA_REGA_PD_RCL_Pos) /*!< 0x00000040 */ +//#define ANA_REGA_PD_RCL ANA_REGA_PD_RCL_Msk /*!< PD 32K RC module */ +#define ANA_REGA_PD_VDCINDET_Pos (7U) +#define ANA_REGA_PD_VDCINDET_Msk (0x1U << ANA_REGA_PD_VDCINDET_Pos) /*!< 0x00000080 */ +#define ANA_REGA_PD_VDCINDET ANA_REGA_PD_VDCINDET_Msk /*!< PD VDCIN detector */ + +/************** Bits definition for ANA_REGB register ******************/ +#define ANA_REGB_RCLTRIM_Pos (0U) +#define ANA_REGB_RCLTRIM_Msk (0x1FU << ANA_REGB_RCLTRIM_Pos) /*!< 0x0000001F */ +#define ANA_REGB_RCLTRIM ANA_REGB_RCLTRIM_Msk /*!< Trimming of 32kHz RC */ +#define ANA_REGB_RCLTRIM_0 (0x00U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_1 (0x01U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_2 (0x02U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_3 (0x03U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_4 (0x04U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_5 (0x05U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_6 (0x06U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_7 (0x07U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_8 (0x08U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_9 (0x09U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_10 (0x0AU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_11 (0x0BU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_12 (0x0CU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_13 (0x0DU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_14 (0x0EU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_15 (0x0FU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_16 (0x10U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_17 (0x11U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_18 (0x12U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_19 (0x13U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_20 (0x14U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_21 (0x15U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_22 (0x16U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_23 (0x17U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_24 (0x18U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_25 (0x19U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_26 (0x1AU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_27 (0x1BU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_28 (0x1CU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_29 (0x1DU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_30 (0x1EU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_31 (0x1FU << ANA_REGB_RCLTRIM_Pos) + +/************** Bits definition for ANA_REGC register ******************/ +#define ANA_REGC_RCHTRIM_Pos (0U) +#define ANA_REGC_RCHTRIM_Msk (0x3FU << ANA_REGC_RCHTRIM_Pos) /*!< 0x0000003F */ +#define ANA_REGC_RCHTRIM ANA_REGC_RCHTRIM_Msk /*!< Trimming of 6.55364MHz RC */ +#define ANA_REGC_RCHTRIM_0 (0x00U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_1 (0x01U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_2 (0x02U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_3 (0x03U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_4 (0x04U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_5 (0x05U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_6 (0x06U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_7 (0x07U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_8 (0x08U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_9 (0x09U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_10 (0x0AU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_11 (0x0BU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_12 (0x0CU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_13 (0x0DU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_14 (0x0EU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_15 (0x0FU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_16 (0x10U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_17 (0x11U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_18 (0x12U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_19 (0x13U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_20 (0x14U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_21 (0x15U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_22 (0x16U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_23 (0x17U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_24 (0x18U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_25 (0x19U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_26 (0x1AU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_27 (0x1BU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_28 (0x1CU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_29 (0x1DU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_30 (0x1EU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_31 (0x1FU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_32 (0x20U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_33 (0x21U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_34 (0x22U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_35 (0x23U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_36 (0x24U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_37 (0x25U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_38 (0x26U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_39 (0x27U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_40 (0x28U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_41 (0x29U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_42 (0x2AU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_43 (0x2BU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_44 (0x2CU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_45 (0x2DU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_46 (0x2EU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_47 (0x2FU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_48 (0x30U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_49 (0x31U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_50 (0x32U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_51 (0x33U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_52 (0x34U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_53 (0x35U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_54 (0x36U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_55 (0x37U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_56 (0x38U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_57 (0x39U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_58 (0x3AU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_59 (0x3BU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_60 (0x3CU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_61 (0x3DU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_62 (0x3EU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_63 (0x3FU << ANA_REGC_RCHTRIM_Pos) + +/************** Bits definition for ANA_REGD register ******************/ +#define ANA_REGD_DVCCTRIM_Pos (0U) +#define ANA_REGD_DVCCTRIM_Msk (0x7U << ANA_REGD_DVCCTRIM_Pos) /*!< 0x00000007 */ +#define ANA_REGD_DVCCTRIM ANA_REGD_DVCCTRIM_Msk /*!< Trimming of DVCC */ +#define ANA_REGD_DVCCTRIM_0 (0x0U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_1 (0x1U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_2 (0x2U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_3 (0x3U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_4 (0x4U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_5 (0x5U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_6 (0x6U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_7 (0x7U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_Pos (3U) +#define ANA_REGD_AVCCTRIM_Msk (0x7U << ANA_REGD_AVCCTRIM_Pos) /*!< 0x00000038 */ +#define ANA_REGD_AVCCTRIM ANA_REGD_AVCCTRIM_Msk /*!< Trimming of AVCC */ +#define ANA_REGD_AVCCTRIM_0 (0x0U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_1 (0x1U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_2 (0x2U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_3 (0x3U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_4 (0x4U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_5 (0x5U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_6 (0x6U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_7 (0x7U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_VREFTRIM_Pos (6U) +#define ANA_REGD_VREFTRIM_Msk (0x3U << ANA_REGD_VREFTRIM_Pos) /*!< 0x000000C0 */ +#define ANA_REGD_VREFTRIM ANA_REGD_VREFTRIM_Msk /*!< Trimming of VREF, which will affect DVCC/33��s output by same ratio */ +#define ANA_REGD_VREFTRIM_0 (0x0U << ANA_REGD_VREFTRIM_Pos) +#define ANA_REGD_VREFTRIM_1 (0x1U << ANA_REGD_VREFTRIM_Pos) +#define ANA_REGD_VREFTRIM_2 (0x2U << ANA_REGD_VREFTRIM_Pos) +#define ANA_REGD_VREFTRIM_3 (0x3U << ANA_REGD_VREFTRIM_Pos) + +/************** Bits definition for ANA_REGE register ******************/ +#define ANA_REGE_REST_Pos (0U) +#define ANA_REGE_REST_Msk (0x7U << ANA_REGE_REST_Pos) /*!< 0x00000007 */ +#define ANA_REGE_REST ANA_REGE_REST_Msk /*!< Fine trimming of bandgap */ +#define ANA_REGE_REST_0 (0x0U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_1 (0x1U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_2 (0x2U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_3 (0x3U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_4 (0x4U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_5 (0x5U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_6 (0x6U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_7 (0x7U << ANA_REGE_REST_Pos) +#define ANA_REGE_RESTL_Pos (4U) +#define ANA_REGE_RESTL_Msk (0x3U << ANA_REGE_RESTL_Pos) /*!< 0x00000018 */ +#define ANA_REGE_RESTL ANA_REGE_RESTL_Msk /*!< Coarse trimming of bandgap */ +#define ANA_REGE_RESTL_0 (0x0U << ANA_REGE_RESTL_Pos) +#define ANA_REGE_RESTL_1 (0x1U << ANA_REGE_RESTL_Pos) +#define ANA_REGE_RESTL_2 (0x2U << ANA_REGE_RESTL_Pos) +#define ANA_REGE_RESTL_3 (0x3U << ANA_REGE_RESTL_Pos) +#define ANA_REGE_RESTD_Pos (6U) +#define ANA_REGE_RESTD_Msk (0x1U << ANA_REGE_RESTD_Pos) +#define ANA_REGE_RESTD ANA_REGE_RESTD_Msk +/************** Bits definition for ANA_REGF register ******************/ +//#define ANA_REGF_TRB_Pos (0U) +//#define ANA_REGF_TRB_Msk (0x3U << ANA_REGF_TRB_Pos) /*!< 0x00000003 */ +//#define ANA_REGF_TRB ANA_REGF_TRB_Msk /*!< Bias voltage trim for ADCs */ +#define ANA_REGF_AVCCO_EN_Pos (2U) +#define ANA_REGF_AVCCO_EN_Msk (0x1U << ANA_REGF_AVCCO_EN_Pos) +#define ANA_REGF_AVCCO_EN ANA_REGF_AVCCO_EN_Msk +#define ANA_REGF_PDNADT_Pos (3U) +#define ANA_REGF_PDNADT_Msk (0x1U << ANA_REGF_PDNADT_Pos) +#define ANA_REGF_PDNADT ANA_REGF_PDNADT_Msk +#define ANA_REGF_SELADT_Pos (4U) +#define ANA_REGF_SELADT_Msk (0x1U << ANA_REGF_SELADT_Pos) +#define ANA_REGF_SELADT ANA_REGF_SELADT_Msk +#define ANA_REGF_ADTREF1SEL_Pos (5U) +#define ANA_REGF_ADTREF1SEL_Msk (0x1U << ANA_REGF_ADTREF1SEL_Pos) +#define ANA_REGF_ADTREF1SEL ANA_REGF_ADTREF1SEL_Msk +#define ANA_REGF_ADTREF2SEL_Pos (6U) +#define ANA_REGF_ADTREF2SEL_Msk (0x1U << ANA_REGF_ADTREF2SEL_Pos) +#define ANA_REGF_ADTREF2SEL ANA_REGF_ADTREF2SEL_Msk +#define ANA_REGF_ADTREF3SEL_Pos (7U) +#define ANA_REGF_ADTREF3SEL_Msk (0x1U << ANA_REGF_ADTREF3SEL_Pos) +#define ANA_REGF_ADTREF3SEL ANA_REGF_ADTREF3SEL_Msk +///************** Bits definition for ANA_REG10 register ******************/ +//#define ANA_REG10_Pos (0U) +//#define ANA_REG10_Msk (0xFFU << ANA_REG10_Pos) /*!< 0x000000FF */ +//#define ANA_REG10 ANA_REG10_Msk /*!< Analog control register 16 */ +// +///************** Bits definition for ANA_REG11 register ******************/ +//#define ANA_REG11_Pos (0U) +//#define ANA_REG11_Msk (0xFFU << ANA_REG11_Pos) /*!< 0x000000FF */ +//#define ANA_REG11 ANA_REG11_Msk /*!< Analog control register 17 */ +// +///************** Bits definition for ANA_REG12 register ******************/ +//#define ANA_REG12_Pos (0U) +//#define ANA_REG12_Msk (0xFFU << ANA_REG12_Pos) /*!< 0x000000FF */ +//#define ANA_REG12 ANA_REG12_Msk /*!< Analog control register 18 */ + +/************** Bits definition for ANA_CTRL register ******************/ +#define ANA_CTRL_COMP1_SEL_Pos (0U) +#define ANA_CTRL_COMP1_SEL_Msk (0x3U << ANA_CTRL_COMP1_SEL_Pos) /*!< 0x00000003 */ +#define ANA_CTRL_COMP1_SEL ANA_CTRL_COMP1_SEL_Msk /*!< This register is used to control the interrupt and wake-up signal generation of COMP1 */ +#define ANA_CTRL_COMP1_SEL_0 (0x0U << ANA_CTRL_COMP1_SEL_Pos) +#define ANA_CTRL_COMP1_SEL_1 (0x1U << ANA_CTRL_COMP1_SEL_Pos) +#define ANA_CTRL_COMP1_SEL_2 (0x2U << ANA_CTRL_COMP1_SEL_Pos) +#define ANA_CTRL_COMP1_SEL_3 (0x3U << ANA_CTRL_COMP1_SEL_Pos) +#define ANA_CTRL_COMP2_SEL_Pos (2U) +#define ANA_CTRL_COMP2_SEL_Msk (0x3U << ANA_CTRL_COMP2_SEL_Pos) /*!< 0x0000000C */ +#define ANA_CTRL_COMP2_SEL ANA_CTRL_COMP2_SEL_Msk /*!< This register is used to control the interrupt and wake-up signal generation of COMP2 */ +//#define ANA_CTRL_PORLOFF_Pos (4U) +//#define ANA_CTRL_PORLOFF_Msk (0x1U << ANA_CTRL_PORLOFF_Pos) /*!< 0x00000010 */ +//#define ANA_CTRL_PORLOFF ANA_CTRL_PORLOFF_Msk /*!< This register can disable the PORL reset */ +//#define ANA_CTRL_PORHOFF_Pos (5U) +//#define ANA_CTRL_PORHOFF_Msk (0x1U << ANA_CTRL_PORHOFF_Pos) /*!< 0x00000020 */ +//#define ANA_CTRL_PORHOFF ANA_CTRL_PORHOFF_Msk /*!< This register can disable the PORH reset */ +#define ANA_CTRL_PDNS_Pos (6U) +#define ANA_CTRL_PDNS_Msk (0x1U << ANA_CTRL_PDNS_Pos) /*!< 0x00000040 */ +#define ANA_CTRL_PDNS ANA_CTRL_PDNS_Msk /*!< This register is used to set the deep sleep behavior when VDCIN is not drop */ +//#define ANA_CTRL_DVCCSW_Pos (7U) +//#define ANA_CTRL_DVCCSW_Msk (0x1U << ANA_CTRL_DVCCSW_Pos) /*!< 0x00000080 */ +//#define ANA_CTRL_DVCCSW ANA_CTRL_DVCCSW_Msk /*!< DVCC auto switch enable at sleep or deep-sleep mode */ +#define ANA_CTRL_RCHTGT_Pos (8U) +#define ANA_CTRL_RCHTGT_Msk (0xFFU << ANA_CTRL_RCHTGT_Pos) /*!< 0x0000FF00 */ +#define ANA_CTRL_RCHTGT ANA_CTRL_RCHTGT_Msk /*!< RCH auto0calibration target register. This register is used to store the target value of RCH */ +//#define ANA_CTRL_DVCCSWSEL_Pos (16U) +//#define ANA_CTRL_DVCCSWSEL_Msk (0x3U << ANA_CTRL_DVCCSWSEL_Pos) /*!< 0x00030000 */ +//#define ANA_CTRL_DVCCSWSEL ANA_CTRL_DVCCSWSEL_Msk /*!< DVCC auto-switching setting at sleep mode or deep-sleep mode */ +//#define ANA_CTRL_DVCCSWSEL_0 (0x0U << ANA_CTRL_DVCCSWSEL_Pos) +//#define ANA_CTRL_DVCCSWSEL_1 (0x1U << ANA_CTRL_DVCCSWSEL_Pos) +//#define ANA_CTRL_DVCCSWSEL_2 (0x2U << ANA_CTRL_DVCCSWSEL_Pos) +//#define ANA_CTRL_DVCCSWSEL_3 (0x3U << ANA_CTRL_DVCCSWSEL_Pos) +#define ANA_CTRL_CMP1DEB_Pos (20U) +#define ANA_CTRL_CMP1DEB_Msk (0x3U << ANA_CTRL_CMP1DEB_Pos) /*!< 0x00300000 */ +#define ANA_CTRL_CMP1DEB ANA_CTRL_CMP1DEB_Msk /*!< Comparator 1 de-bounce control register */ +#define ANA_CTRL_CMP1DEB_0 (0x0U << ANA_CTRL_CMP1DEB_Pos) +#define ANA_CTRL_CMP1DEB_1 (0x1U << ANA_CTRL_CMP1DEB_Pos) +#define ANA_CTRL_CMP1DEB_2 (0x2U << ANA_CTRL_CMP1DEB_Pos) +#define ANA_CTRL_CMP1DEB_3 (0x3U << ANA_CTRL_CMP1DEB_Pos) +#define ANA_CTRL_CMP2DEB_Pos (22U) +#define ANA_CTRL_CMP2DEB_Msk (0x3U << ANA_CTRL_CMP2DEB_Pos) /*!< 0x00C00000 */ +#define ANA_CTRL_CMP2DEB ANA_CTRL_CMP2DEB_Msk /*!< Comparator 2 de-bounce control register */ +#define ANA_CTRL_PWRDROPDEB_Pos (24U) +#define ANA_CTRL_PWRDROPDEB_Msk (0x3U << ANA_CTRL_PWRDROPDEB_Pos) /*!< 0x03000000 */ +#define ANA_CTRL_PWRDROPDEB ANA_CTRL_PWRDROPDEB_Msk /*!< Power drop de-bounce control register */ +#define ANA_CTRL_PWRDROPDEB_0 (0x0U << ANA_CTRL_PWRDROPDEB_Pos) +#define ANA_CTRL_PWRDROPDEB_1 (0x1U << ANA_CTRL_PWRDROPDEB_Pos) +#define ANA_CTRL_PWRDROPDEB_2 (0x2U << ANA_CTRL_PWRDROPDEB_Pos) +#define ANA_CTRL_PWRDROPDEB_3 (0x3U << ANA_CTRL_PWRDROPDEB_Pos) +#define ANA_CTRL_PDNS2_Pos (26U) +#define ANA_CTRL_PDNS2_Msk (0x1U << ANA_CTRL_PDNS2_Pos) /*!< 0x04000000 */ +#define ANA_CTRL_PDNS2 ANA_CTRL_PDNS2_Msk /*!< This register is used to set the deep sleep behavior when VDD is not drop */ +//#define ANA_CTRL_ANATEST_Pos (28U) +//#define ANA_CTRL_ANATEST_Msk (0xFU << ANA_CTRL_ANATEST_Pos) /*!< 0xF0000000 */ +//#define ANA_CTRL_ANATEST ANA_CTRL_ANATEST_Msk /*!< This register is used to control the internal analog test signal. When one of the internal signal is selected, the hardware will use IOA[15] as input to simulation the behavior of the internal signal */ + +/************** Bits definition for ANA_COMPOUT register ******************/ +#define ANA_COMPOUT_LOCKH_Pos (0U) +#define ANA_COMPOUT_LOCKH_Msk (0x1U << ANA_COMPOUT_LOCKH_Pos) /*!< 0x00000001 */ +#define ANA_COMPOUT_LOCKH ANA_COMPOUT_LOCKH_Msk /*!< PLLH lock status */ +#define ANA_COMPOUT_LOCKL_Pos (1U) +#define ANA_COMPOUT_LOCKL_Msk (0x1U << ANA_COMPOUT_LOCKL_Pos) /*!< 0x00000002 */ +#define ANA_COMPOUT_LOCKL ANA_COMPOUT_LOCKL_Msk /*!< PLLL lock status */ +#define ANA_COMPOUT_COMP1_Pos (2U) +#define ANA_COMPOUT_COMP1_Msk (0x1U << ANA_COMPOUT_COMP1_Pos) /*!< 0x00000004 */ +#define ANA_COMPOUT_COMP1 ANA_COMPOUT_COMP1_Msk /*!< This bit shows the output of comparator 1 */ +#define ANA_COMPOUT_COMP2_Pos (3U) +#define ANA_COMPOUT_COMP2_Msk (0x1U << ANA_COMPOUT_COMP2_Pos) /*!< 0x00000008 */ +#define ANA_COMPOUT_COMP2 ANA_COMPOUT_COMP2_Msk /*!< This bit shows the output of comparator 2 */ +//#define ANA_COMPOUT_MAINPDN_Pos (4U) +//#define ANA_COMPOUT_MAINPDN_Msk (0x1U << ANA_COMPOUT_MAINPDN_Pos) /*!< 0x00000010 */ +//#define ANA_COMPOUT_MAINPDN ANA_COMPOUT_MAINPDN_Msk /*!< Main power power-down status */ +//#define ANA_COMPOUT_BATRTCPDN_Pos (5U) +//#define ANA_COMPOUT_BATRTCPDN_Msk (0x1U << ANA_COMPOUT_BATRTCPDN_Pos) /*!< 0x00000020 */ +//#define ANA_COMPOUT_BATRTCPDN ANA_COMPOUT_BATRTCPDN_Msk /*!< RTC power power-down status */ +//#define ANA_COMPOUT_MAINPRSTS_Pos (6U) +//#define ANA_COMPOUT_MAINPRSTS_Msk (0x1U << ANA_COMPOUT_MAINPRSTS_Pos) /*!< 0x00000040 */ +//#define ANA_COMPOUT_MAINPRSTS ANA_COMPOUT_MAINPRSTS_Msk /*!< This bit show the status of MAINPRSTS */ +#define ANA_COMPOUT_VDDALARM_Pos (7U) +#define ANA_COMPOUT_VDDALARM_Msk (0x1U << ANA_COMPOUT_VDDALARM_Pos) /*!< 0x00000080 */ +#define ANA_COMPOUT_VDDALARM ANA_COMPOUT_VDDALARM_Msk /*!< This bit shows the output of POWALARM */ +#define ANA_COMPOUT_VDCINDROP_Pos (8U) +#define ANA_COMPOUT_VDCINDROP_Msk (0x1U << ANA_COMPOUT_VDCINDROP_Pos) /*!< 0x00000100 */ +#define ANA_COMPOUT_VDCINDROP ANA_COMPOUT_VDCINDROP_Msk /*!< VDCIN drop status */ +#define ANA_COMPOUT_AVCCLV_Pos (10U) +#define ANA_COMPOUT_AVCCLV_Msk (0x1U << ANA_COMPOUT_AVCCLV_Pos) /*!< 0x00000400 */ +#define ANA_COMPOUT_AVCCLV ANA_COMPOUT_AVCCLV_Msk /*!< AVCC low power status */ +#define ANA_COMPOUT_TADCO_Pos (14UL) +#define ANA_COMPOUT_TADCO_Msk (0x03UL << ANA_COMPOUT_TADCO_Pos) +#define ANA_COMPOUT_TADCO ANA_COMPOUT_TADCO_Msk + +///************** Bits definition for ANA_VERSION register ******************/ +//#define ANA_VERSION_VERSION_Pos (0U) +//#define ANA_VERSION_VERSION_Msk (0x3U << ANA_VERSION_VERSION_Pos) /*!< 0x00000003 */ +//#define ANA_VERSION_VERSION ANA_VERSION_VERSION_Msk /*!< This bit shows the version information of analog module */ + +///************** Bits definition for ANA_ADCSTATE register ******************/ +//#define ANA_ADCSTATE_ADCSTATE_Pos (0U) +//#define ANA_ADCSTATE_ADCSTATE_Msk (0x7U << ANA_ADCSTATE_ADCSTATE_Pos) /*!< 0x00000007 */ +//#define ANA_ADCSTATE_ADCSTATE ANA_ADCSTATE_ADCSTATE_Msk /*!< This bit shows the ADC state of ADC CIC filter */ + +/************** Bits definition for ANA_INTSTS register ******************/ +#define ANA_INTSTS_Msk (0x1DFFUL) +#define ANA_INTSTS_INTSTS0_Pos (0U) +#define ANA_INTSTS_INTSTS0_Msk (0x1U << ANA_INTSTS_INTSTS0_Pos) /*!< 0x00000001 */ +#define ANA_INTSTS_INTSTS0 ANA_INTSTS_INTSTS0_Msk /*!< Interrupt flag of manual ADC conversion done */ +#define ANA_INTSTS_INTSTS1_Pos (1U) +#define ANA_INTSTS_INTSTS1_Msk (0x1U << ANA_INTSTS_INTSTS1_Pos) /*!< 0x00000002 */ +#define ANA_INTSTS_INTSTS1 ANA_INTSTS_INTSTS1_Msk /*!< Interrupt flag of auto ADC conversion done */ +#define ANA_INTSTS_INTSTS2_Pos (2U) +#define ANA_INTSTS_INTSTS2_Msk (0x1U << ANA_INTSTS_INTSTS2_Pos) /*!< 0x00000004 */ +#define ANA_INTSTS_INTSTS2 ANA_INTSTS_INTSTS2_Msk /*!< Interrupt flag of COMP1, the interrupt generate condition is controlled by COMP1_SEL */ +#define ANA_INTSTS_INTSTS3_Pos (3U) +#define ANA_INTSTS_INTSTS3_Msk (0x1U << ANA_INTSTS_INTSTS3_Pos) /*!< 0x00000008 */ +#define ANA_INTSTS_INTSTS3 ANA_INTSTS_INTSTS3_Msk /*!< Interrupt flag of COMP2, the interrupt generate condition is controlled by COMP2_SEL */ +//#define ANA_INTSTS_INTSTS4_Pos (4U) +//#define ANA_INTSTS_INTSTS4_Msk (0x1U << ANA_INTSTS_INTSTS4_Pos) /*!< 0x00000010 */ +//#define ANA_INTSTS_INTSTS4 ANA_INTSTS_INTSTS4_Msk /*!< Interrupt flag of MAINPDN, this interrupt will be generated when MAINPDN rising or falling */ +//#define ANA_INTSTS_INTSTS5_Pos (5U) +//#define ANA_INTSTS_INTSTS5_Msk (0x1U << ANA_INTSTS_INTSTS5_Pos) /*!< 0x00000020 */ +//#define ANA_INTSTS_INTSTS5 ANA_INTSTS_INTSTS5_Msk /*!< Interrupt flag of RTCPDN, this interrupt will be generated when RTCPDN rising or falling */ +//#define ANA_INTSTS_INTSTS6_Pos (6U) +//#define ANA_INTSTS_INTSTS6_Msk (0x1U << ANA_INTSTS_INTSTS6_Pos) /*!< 0x00000040 */ +//#define ANA_INTSTS_INTSTS6 ANA_INTSTS_INTSTS6_Msk /*!< Interrupt flag of SWT2BAT, this interrupt will be generated when SWT2BAT rising or falling */ +#define ANA_INTSTS_INTSTS7_Pos (7U) +#define ANA_INTSTS_INTSTS7_Msk (0x1U << ANA_INTSTS_INTSTS7_Pos) /*!< 0x00000080 */ +#define ANA_INTSTS_INTSTS7 ANA_INTSTS_INTSTS7_Msk /*!< Interrupt flag of POWALARMQPWRDN, this interrupt will be generated when POWALARM QPWRDN rising or falling */ +#define ANA_INTSTS_INTSTS8_Pos (8U) +#define ANA_INTSTS_INTSTS8_Msk (0x1U << ANA_INTSTS_INTSTS8_Pos) /*!< 0x00000100 */ +#define ANA_INTSTS_INTSTS8 ANA_INTSTS_INTSTS8_Msk /*!< Interrupt flag of PWRDROP, this interrupt will be generated when PWRDOP rising or falling */ +#define ANA_INTSTS_INTSTS10_Pos (10U) +#define ANA_INTSTS_INTSTS10_Msk (0x1U << ANA_INTSTS_INTSTS10_Pos) /*!< 0x00000400 */ +#define ANA_INTSTS_INTSTS10 ANA_INTSTS_INTSTS10_Msk /*!< Interrupt flag of POWLV, this interrupt will be generated when POWLV rising or falling */ +#define ANA_INTSTS_INTSTS11_Pos (11U) +#define ANA_INTSTS_INTSTS11_Msk (0x1U << ANA_INTSTS_INTSTS11_Pos) /*!< 0x00000800 */ +#define ANA_INTSTS_INTSTS11 ANA_INTSTS_INTSTS11_Msk /*!< Interrupt flag of sleep mode entry under PWRDROP is 0(i.e. VDCIN higher than threshold), this interrupt will be generated when PWRDROP is 0 and the entry of sleep or deep-sleep modes are detected. Programmer can enable this interrupt to force CPU wake-up from sleep or deep-sleep mode when PWRDROP is 0 */ +#define ANA_INTSTS_INTSTS12_Pos (12U) +#define ANA_INTSTS_INTSTS12_Msk (0x1U << ANA_INTSTS_INTSTS12_Pos) /*!< 0x00001000 */ +#define ANA_INTSTS_INTSTS12 ANA_INTSTS_INTSTS12_Msk /*!< ANA_REGx error flag. This interrupt is used to detect the error status of ANA_REGx, an automatically check0sum and parity check is applied to ANA_REGx, when external noise cause by ESD or other problem affect the setting of ANA_REGx, this interrupt will be asserted and programmer can use this flag to determine if it is necessary to recover the setting in the ANA_REGx */ +#define ANA_INTSTS_INTSTS13_Pos (13U) +#define ANA_INTSTS_INTSTS13_Msk (0x1U << ANA_INTSTS_INTSTS13_Pos) +#define ANA_INTSTS_INTSTS13 ANA_INTSTS_INTSTS13_Msk + +/************** Bits definition for ANA_INTEN register ******************/ +#define ANA_INTEN_INTEN0_Pos (0U) +#define ANA_INTEN_INTEN0_Msk (0x1U << ANA_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +#define ANA_INTEN_INTEN0 ANA_INTEN_INTEN0_Msk /*!< Interrupt enable control of manual ADC conversion done */ +#define ANA_INTEN_INTEN1_Pos (1U) +#define ANA_INTEN_INTEN1_Msk (0x1U << ANA_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define ANA_INTEN_INTEN1 ANA_INTEN_INTEN1_Msk /*!< Interrupt enable control of auto ADC conversion done */ +#define ANA_INTEN_INTEN2_Pos (2U) +#define ANA_INTEN_INTEN2_Msk (0x1U << ANA_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define ANA_INTEN_INTEN2 ANA_INTEN_INTEN2_Msk /*!< Interrupt and wake-up enable control of COMP1 */ +#define ANA_INTEN_INTEN3_Pos (3U) +#define ANA_INTEN_INTEN3_Msk (0x1U << ANA_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define ANA_INTEN_INTEN3 ANA_INTEN_INTEN3_Msk /*!< Interrupt and wake-up enable control of COMP2 */ +//#define ANA_INTEN_INTEN4_Pos (4U) +//#define ANA_INTEN_INTEN4_Msk (0x1U << ANA_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +//#define ANA_INTEN_INTEN4 ANA_INTEN_INTEN4_Msk /*!< Interrupt and wake-up enable control of MAINPDN falling */ +//#define ANA_INTEN_INTEN5_Pos (5U) +//#define ANA_INTEN_INTEN5_Msk (0x1U << ANA_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +//#define ANA_INTEN_INTEN5 ANA_INTEN_INTEN5_Msk /*!< Interrupt and wake-up enable control of RTCPDN falling */ +//#define ANA_INTEN_INTEN6_Pos (6U) +//#define ANA_INTEN_INTEN6_Msk (0x1U << ANA_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +//#define ANA_INTEN_INTEN6 ANA_INTEN_INTEN6_Msk /*!< Interrupt and wake-up enable control of SWT2BAT */ +#define ANA_INTEN_INTEN7_Pos (7U) +#define ANA_INTEN_INTEN7_Msk (0x1U << ANA_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define ANA_INTEN_INTEN7 ANA_INTEN_INTEN7_Msk /*!< Interrupt and wake-up enable control of POWALARM */ +#define ANA_INTEN_INTEN8_Pos (8U) +#define ANA_INTEN_INTEN8_Msk (0x1U << ANA_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define ANA_INTEN_INTEN8 ANA_INTEN_INTEN8_Msk /*!< Interrupt and wake-up enable control of PWRDROP */ +#define ANA_INTEN_INTEN10_Pos (10U) +#define ANA_INTEN_INTEN10_Msk (0x1U << ANA_INTEN_INTEN10_Pos) /*!< 0x00000400 */ +#define ANA_INTEN_INTEN10 ANA_INTEN_INTEN10_Msk /*!< Interrupt and wake-up enable control of POWLV */ +#define ANA_INTEN_INTEN11_Pos (11U) +#define ANA_INTEN_INTEN11_Msk (0x1U << ANA_INTEN_INTEN11_Pos) /*!< 0x00000800 */ +#define ANA_INTEN_INTEN11 ANA_INTEN_INTEN11_Msk /*!< Interrupt and wake-up enable control of sleep mode entry */ +#define ANA_INTEN_INTEN12_Pos (12U) +#define ANA_INTEN_INTEN12_Msk (0x1U << ANA_INTEN_INTEN12_Pos) /*!< 0x00001000 */ +#define ANA_INTEN_INTEN12 ANA_INTEN_INTEN12_Msk /*!< Interrupt and wake-up enable control of ANA_REGx error */ +#define ANA_INTEN_INTEN13_Pos (13U) +#define ANA_INTEN_INTEN13_Msk (0x1U << ANA_INTEN_INTEN13_Pos) /*!< 0x00001000 */ +#define ANA_INTEN_INTEN13 ANA_INTEN_INTEN13_Msk + +/************** Bits definition for ANA_ADCCTRL register ******************/ +#define ANA_ADCCTRL_MCH_Pos (0U) +#define ANA_ADCCTRL_MCH_Msk (0xFU << ANA_ADCCTRL_MCH_Pos) /*!< 0x0000000F */ +#define ANA_ADCCTRL_MCH ANA_ADCCTRL_MCH_Msk /*!< Manual ADC channel control */ +#define ANA_ADCCTRL_ACH_Pos (4U) +#define ANA_ADCCTRL_ACH_Msk (0xFU << ANA_ADCCTRL_ACH_Pos) /*!< 0x000000F0 */ +#define ANA_ADCCTRL_ACH ANA_ADCCTRL_ACH_Msk /*!< Auto ADC channel control */ +#define ANA_ADCCTRL_CLKDIV_Pos (8U) +#define ANA_ADCCTRL_CLKDIV_Msk (0xFU << ANA_ADCCTRL_CLKDIV_Pos) /*!< 0x00000700 */ +#define ANA_ADCCTRL_CLKDIV ANA_ADCCTRL_CLKDIV_Msk /*!< ADC clock divider, the ADC main clock is necessary to be 3.2768MHz, so when different clock source is selected, it is necessary to set correct clock division rate to generate ADC clock */ +#define ANA_ADCCTRL_CLKDIV_1 (0x0U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_2 (0x1U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_3 (0x2U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_4 (0x3U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_5 (0x4U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_6 (0x5U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_7 (0x6U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_8 (0x7U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_9 (0x8U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_10 (0x9U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_11 (0xAU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_12 (0xBU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_13 (0xCU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_14 (0xDU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_15 (0xEU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_16 (0xFU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKSEL_Pos (12U) +#define ANA_ADCCTRL_CLKSEL_Msk (0x1U << ANA_ADCCTRL_CLKSEL_Pos) /*!< 0x00001000 */ +#define ANA_ADCCTRL_CLKSEL ANA_ADCCTRL_CLKSEL_Msk /*!< ADC clock source selection */ +#define ANA_ADCCTRL_AEN_Pos (16U) +#define ANA_ADCCTRL_AEN_Msk (0x7U << ANA_ADCCTRL_AEN_Pos) /*!< 0x00070000 */ +#define ANA_ADCCTRL_AEN ANA_ADCCTRL_AEN_Msk /*!< Auto ADC conversion enable control register */ +#define ANA_ADCCTRL_AEN_OFF (0x0U << ANA_ADCCTRL_AEN_Pos) +#define ANA_ADCCTRL_AEN_TMR0 (0x4U << ANA_ADCCTRL_AEN_Pos) +#define ANA_ADCCTRL_AEN_TMR1 (0x5U << ANA_ADCCTRL_AEN_Pos) +#define ANA_ADCCTRL_AEN_TMR2 (0x6U << ANA_ADCCTRL_AEN_Pos) +#define ANA_ADCCTRL_AEN_TMR3 (0x7U << ANA_ADCCTRL_AEN_Pos) +//#define ANA_ADCCTRL_STOP_Pos (19U) +//#define ANA_ADCCTRL_STOP_Msk (0x1U << ANA_ADCCTRL_STOP_Pos) /*!< 0x00080000 */ +//#define ANA_ADCCTRL_STOP ANA_ADCCTRL_STOP_Msk /*!< Force stop current ADC conversion process */ +#define ANA_ADCCTRL_MMODE_Pos (20U) +#define ANA_ADCCTRL_MMODE_Msk (0x1U << ANA_ADCCTRL_MMODE_Pos) /*!< 0x00100000 */ +#define ANA_ADCCTRL_MMODE ANA_ADCCTRL_MMODE_Msk /*!< Manual ADC mode control */ +#define ANA_ADCCTRL_AMODE_Pos (21U) +#define ANA_ADCCTRL_AMODE_Msk (0x1U << ANA_ADCCTRL_AMODE_Pos) /*!< 0x00200000 */ +#define ANA_ADCCTRL_AMODE ANA_ADCCTRL_AMODE_Msk /*!< Auto ADC mode control */ +#define ANA_ADCCTRL_DSRSEL_Pos (22U) +#define ANA_ADCCTRL_DSRSEL_Msk (0x3U << ANA_ADCCTRL_DSRSEL_Pos) /*!< 0x00C00000 */ +#define ANA_ADCCTRL_DSRSEL ANA_ADCCTRL_DSRSEL_Msk /*!< CIC down sampling rate control register. The higher down-sampling rate, the higher output data stability, and also lower sampling rate */ +#define ANA_ADCCTRL_DSRSEL_512 (0x0U << ANA_ADCCTRL_DSRSEL_Pos) +#define ANA_ADCCTRL_DSRSEL_256 (0x1U << ANA_ADCCTRL_DSRSEL_Pos) +#define ANA_ADCCTRL_DSRSEL_128 (0x2U << ANA_ADCCTRL_DSRSEL_Pos) +#define ANA_ADCCTRL_DSRSEL_64 (0x3U << ANA_ADCCTRL_DSRSEL_Pos) +#define ANA_ADCCTRL_CICSKIP_Pos (24U) +#define ANA_ADCCTRL_CICSKIP_Msk (0x7U << ANA_ADCCTRL_CICSKIP_Pos) /*!< 0x07000000 */ +#define ANA_ADCCTRL_CICSKIP ANA_ADCCTRL_CICSKIP_Msk /*!< CIC output skip control register. This register is used to control how many samples will be skipped at the beginning of ADC sample. If CICAON is 1 and the ADC channel is not changed, the CIC output will not be skipped by the ADC controller, this can be used for high speed capture to single channel */ +#define ANA_ADCCTRL_CICSKIP_4 (0x0U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_5 (0x1U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_6 (0x2U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_7 (0x3U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_0 (0x4U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_1 (0x5U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_2 (0x6U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_3 (0x7U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSCA_Pos (27U) +#define ANA_ADCCTRL_CICSCA_Msk (0x1U << ANA_ADCCTRL_CICSCA_Pos) /*!< 0x08000000 */ +#define ANA_ADCCTRL_CICSCA ANA_ADCCTRL_CICSCA_Msk /*!< CIC output scale-down selection */ +#define ANA_ADCCTRL_CICINV_Pos (28U) +#define ANA_ADCCTRL_CICINV_Msk (0x1U << ANA_ADCCTRL_CICINV_Pos) /*!< 0x10000000 */ +#define ANA_ADCCTRL_CICINV ANA_ADCCTRL_CICINV_Msk /*!< CIC filter input inversion */ +#define ANA_ADCCTRL_CICAON_Pos (29U) +#define ANA_ADCCTRL_CICAON_Msk (0x1U << ANA_ADCCTRL_CICAON_Pos) /*!< 0x20000000 */ +#define ANA_ADCCTRL_CICAON ANA_ADCCTRL_CICAON_Msk /*!< CIC filter always on control register */ +//#define ANA_ADCCTRL_16CH_Pos (30U) +//#define ANA_ADCCTRL_16CH_Msk (0x1U << ANA_ADCCTRL_16CH_Pos) /*!< 0x40000000 */ +//#define ANA_ADCCTRL_16CH ANA_ADCCTRL_16CH_Msk /*!< ADC multi channels scan control register */ +#define ANA_ADCCTRL_MTRIG_Pos (31U) +#define ANA_ADCCTRL_MTRIG_Msk (0x1U << ANA_ADCCTRL_MTRIG_Pos) /*!< 0x80000000 */ +#define ANA_ADCCTRL_MTRIG ANA_ADCCTRL_MTRIG_Msk /*!< Manual ADC trigger */ + +/************** Bits definition for ANA_ADCDATAx register ******************/ +#define ANA_ADCDATA_Pos (0U) +#define ANA_ADCDATA_Msk (0xFFFFU << ANA_ADCDATA_Pos) /*!< 0x0000FFFF */ +#define ANA_ADCDATA ANA_ADCDATA_Msk /*!< The result of ADC conversion will be stored in these registers */ + +/************** Bits definition for ANA_CMPCNTx register ******************/ +#define ANA_CMPCNT_CNT_Pos (0U) +#define ANA_CMPCNT_CNT_Msk (0xFFFFFFFFU << ANA_CMPCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define ANA_CMPCNT_CNT ANA_CMPCNT_CNT_Msk /*!< This register store the happen times of comparator x according to the setting in COMPx_SEL */ + +/************** Bits definition for ANA_MISC register ******************/ +//#define ANA_MISC_FORCEPWR2MP_Pos (1U) +//#define ANA_MISC_FORCEPWR2MP_Msk (0x1U << ANA_MISC_FORCEPWR2MP_Pos) /*!< 0x00000002 */ +//#define ANA_MISC_FORCEPWR2MP ANA_MISC_FORCEPWR2MP_Msk /*!< Force BATRTC feed into VDDIO function when doing RTC auto-calibration control */ +#define ANA_MISC_TADCTH_Pos (4U) +#define ANA_MISC_TADCTH_Msk (0x03UL << ANA_MISC_TADCTH_Pos) +#define ANA_MISC_TADCTH ANA_MISC_TADCTH_Msk +#define ANA_MISC_TADCTH_0 (0x00UL << ANA_MISC_TADCTH_Pos) +#define ANA_MISC_TADCTH_1 (0x01UL << ANA_MISC_TADCTH_Pos) +#define ANA_MISC_TADCTH_2 (0x02UL << ANA_MISC_TADCTH_Pos) +#define ANA_MISC_TADCTH_3 (0x03UL << ANA_MISC_TADCTH_Pos) + +/******************************************************************************/ +/* */ +/* RTC controller (RTC) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for RTC_SEC register ******************/ +#define RTC_SEC_Pos (0U) +#define RTC_SEC_Msk (0x7FU << RTC_SEC_Pos) /*!< 0x0000007F */ +#define RTC_SEC_SEC RTC_SEC_Msk /*!< RTC second register */ + +/************** Bits definition for RTC_MIN register ******************/ +#define RTC_MIN_Pos (0U) +#define RTC_MIN_Msk (0x7FU << RTC_MIN_Pos) /*!< 0x0000007F */ +#define RTC_MIN_MIN RTC_MIN_Msk /*!< RTC minute register */ + +/************** Bits definition for RTC_HOUR register ******************/ +#define RTC_HOUR_Pos (0U) +#define RTC_HOUR_Msk (0x3FU << RTC_HOUR_Pos) /*!< 0x0000003F */ +#define RTC_HOUR_HOUR RTC_HOUR_Msk /*!< RTC hour register */ + +/************** Bits definition for RTC_DAY register ******************/ +#define RTC_DAY_Pos (0U) +#define RTC_DAY_Msk (0x3FU << RTC_DAY_Pos) /*!< 0x0000003F */ +#define RTC_DAY_DAY RTC_DAY_Msk /*!< RTC day register */ + +/************** Bits definition for RTC_WEEK register ******************/ +#define RTC_WEEK_Pos (0U) +#define RTC_WEEK_Msk (0x7U << RTC_WEEK_Pos) /*!< 0x00000007 */ +#define RTC_WEEK_WEEK RTC_WEEK_Msk /*!< RTC week-day register */ + +/************** Bits definition for RTC_MON register ******************/ +#define RTC_MON_Pos (0U) +#define RTC_MON_Msk (0x1FU << RTC_MON_Pos) /*!< 0x0000001F */ +#define RTC_MON_MON RTC_MON_Msk /*!< RTC month register */ + +/************** Bits definition for RTC_YEAR register ******************/ +#define RTC_YEAR_Pos (0U) +#define RTC_YEAR_Msk (0xFFU << RTC_YEAR_Pos) /*!< 0x000000FF */ +#define RTC_YEAR_YEAR RTC_YEAR_Msk /*!< RTC year register */ + +/************** Bits definition for RTC_WKUSEC register ******************/ +#define RTC_WKUSEC_Pos (0U) +#define RTC_WKUSEC_Msk (0x3FU << RTC_WKUSEC_Pos) /*!< 0x0000003F */ +#define RTC_WKUSEC_WKUSEC RTC_WKUSEC_Msk /*!< This register is used to control the multi-second wake-up function. The wake-up period is (WKUSEC + 1)*1 second */ + +/************** Bits definition for RTC_WKUMIN register ******************/ +#define RTC_WKUMIN_Pos (0U) +#define RTC_WKUMIN_Msk (0x3FU << RTC_WKUMIN_Pos) /*!< 0x0000003F */ +#define RTC_WKUMIN_WKUMIN RTC_WKUMIN_Msk /*!< This register is used to control the multi-minute wake-up function. The wake-up period is (WKUMIN + 1)*1 minute */ + +/************** Bits definition for RTC_WKUHOUR register ******************/ +#define RTC_WKUHOUR_Pos (0U) +#define RTC_WKUHOUR_Msk (0x1FU << RTC_WKUHOUR_Pos) /*!< 0x0000001F */ +#define RTC_WKUHOUR_WKUHOUR RTC_WKUHOUR_Msk /*!< This register is used to control the multi-hour wake-up function. The wake-up period is (WKUHOUR + 1)*1 hour */ + +/************** Bits definition for RTC_WKUCNT register ******************/ +#define RTC_WKUCNT_WKUCNT_Pos (0U) +#define RTC_WKUCNT_WKUCNT_Msk (0xFFFFFFU << RTC_WKUCNT_WKUCNT_Pos) /*!< 0x00FFFFFF */ +#define RTC_WKUCNT_WKUCNT RTC_WKUCNT_WKUCNT_Msk /*!< This register is used to control the 32K counter wake-up function. The wake-up period is (WKUCNT + 1)*Counter Clock */ +#define RTC_WKUCNT_CNTSEL_Pos (24U) +#define RTC_WKUCNT_CNTSEL_Msk (0x3U << RTC_WKUCNT_CNTSEL_Pos) /*!< 0x03000000 */ +#define RTC_WKUCNT_CNTSEL RTC_WKUCNT_CNTSEL_Msk /*!< This is register is used to set the counter clock of WKUCNT */ +#define RTC_WKUCNT_CNTSEL_0 (0x0U << RTC_WKUCNT_CNTSEL_Pos) +#define RTC_WKUCNT_CNTSEL_1 (0x1U << RTC_WKUCNT_CNTSEL_Pos) +#define RTC_WKUCNT_CNTSEL_2 (0x2U << RTC_WKUCNT_CNTSEL_Pos) +#define RTC_WKUCNT_CNTSEL_3 (0x3U << RTC_WKUCNT_CNTSEL_Pos) + +/************** Bits definition for RTC_CAL register ******************/ +#define RTC_CAL_Pos (0U) +#define RTC_CAL_Msk (0x3FFFU << RTC_CAL_Pos) /*!< 0x00003FFF */ +#define RTC_CAL_CAL RTC_CAL_Msk /*!< RTC 32768 calibration register, the RTC engine will do calibration for every 30 seconds, the internal counter will count 32768 times during 1~29 second. At the 30 second, it will count [32768-(CAL-1)] for a second, so it can let the average 1 second pulse in 30 seconds become an accurate 1 second pulse */ + +/************** Bits definition for RTC_DIV register ******************/ +#define RTC_DIV_RTCDIV_Pos (0U) +#define RTC_DIV_RTCDIV_Msk (0x3FFFFFFU << RTC_DIV_RTCDIV_Pos) /*!< 0x03FFFFFF */ +#define RTC_DIV_RTCDIV RTC_DIV_RTCDIV_Msk /*!< This register is used to store capture value during capture mode of used to generate divider output during generation mode. The output frequency is PCLK/(2*(RTCDIV+1)) */ + +/************** Bits definition for RTC_CTL register ******************/ +//#define RTC_CTL_MODE_Pos (0U) +//#define RTC_CTL_MODE_Msk (0x3U << RTC_CTL_MODE_Pos) /*!< 0x00000003 */ +//#define RTC_CTL_MODE RTC_CTL_MODE_Msk /*!< This register is used to control the capture/divider mode of high frequency divider */ +//#define RTC_CTL_MODE_0 (0x0U << RTC_CTL_MODE_Pos) +//#define RTC_CTL_MODE_1 (0x1U << RTC_CTL_MODE_Pos) +//#define RTC_CTL_MODE_2 (0x2U << RTC_CTL_MODE_Pos) +//#define RTC_CTL_MODE_3 (0x3U << RTC_CTL_MODE_Pos) +#define RTC_CTL_RTCPLLOE_Pos (2U) +#define RTC_CTL_RTCPLLOE_Msk (0x1U << RTC_CTL_RTCPLLOE_Pos) /*!< 0x00000004 */ +#define RTC_CTL_RTCPLLOE RTC_CTL_RTCPLLOE_Msk /*!< RTCPLL Divider output enable, this register is used to control the RTCPLL divider output */ +//#define RTC_CTL_SPOE_Pos (3U) +//#define RTC_CTL_SPOE_Msk (0x1U << RTC_CTL_SPOE_Pos) /*!< 0x00000008 */ +//#define RTC_CTL_SPOE RTC_CTL_SPOE_Msk /*!< RTC second pulse output enable, this register is used to control the RTC second pulse output */ + +///************** Bits definition for RTC_ITV register ******************/ +//#define RTC_ITV_ITV_Pos (0U) +//#define RTC_ITV_ITV_Msk (0x7U << RTC_ITV_ITV_Pos) /*!< 0x00000007 */ +//#define RTC_ITV_ITV RTC_ITV_ITV_Msk /*!< This register is used to control wake-up and interrupt interval of RTC. This register operates independently with RTC_WKUSEC and RTC_WKUMIN and RTC_WKUHOUR */ +//#define RTC_ITV_ITV_0 (0x0U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_1 (0x1U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_2 (0x2U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_3 (0x3U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_4 (0x4U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_5 (0x5U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_6 (0x6U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_7 (0x7U << RTC_ITV_ITV_Pos) +// +///************** Bits definition for RTC_SITV register ******************/ +//#define RTC_SITV_SITV_Pos (0U) +//#define RTC_SITV_SITV_Msk (0x3FU << RTC_SITV_SITV_Pos) /*!< 0x0000003F */ +//#define RTC_SITV_SITV RTC_SITV_SITV_Msk /*!< Multi second wake-up interval control register. This register is valid only when ITV is 7 and SITVEN is 1 */ +//#define RTC_SITV_SITVEN_Pos (6U) +//#define RTC_SITV_SITVEN_Msk (0x1U << RTC_SITV_SITVEN_Pos) /*!< 0x00000040 */ +//#define RTC_SITV_SITVEN RTC_SITV_SITVEN_Msk /*!< Multi Second interval enable register, this register is valid only when ITV is set to 7 */ + +/************** Bits definition for RTC_PWD register ******************/ +#define RTC_PWD_PWDEN_Pos (0U) +#define RTC_PWD_PWDEN_Msk (0x1U << RTC_PWD_PWDEN_Pos) /*!< 0x00000001 */ +#define RTC_PWD_PWDEN RTC_PWD_PWDEN_Msk /*!< This register is used to protect the RTC_CE port��s access. Before access the RTC_CE, programmer should write 0x5AA55AA5 to this port, and the PWDEN will be set to 1. This bit will be cleared automatically after any write to RTC_CE port. Which means programmer should write to this port again before next access to RTC_CE port */ + +/************** Bits definition for RTC_CE register ******************/ +#define RTC_CE_CE_Pos (0U) +#define RTC_CE_CE_Msk (0x1U << RTC_CE_CE_Pos) /*!< 0x00000001 */ +#define RTC_CE_CE RTC_CE_CE_Msk /*!< This register is used to unlock the access to RTC register. This register can be only when PWDEN is set to 1 and 0xA55AA55B is written to this register. After this bit is set to 1, the RTC register can be programmed, but the actual update to RTC core will be start after this bit is cleared to 0. To clear this bit, the PWDEN should be set to 1 and 0xA55AA55A should be written to this register */ +#define RTC_CE_BSY_Pos (1U) +#define RTC_CE_BSY_Msk (0x1U << RTC_CE_BSY_Pos) /*!< 0x00000002 */ +#define RTC_CE_BSY RTC_CE_BSY_Msk /*!< This flag is used to indicated the RTC update procedure or RTC read procedure is ongoing. This bit will be set immediately after the CE is cleared from 1 to 0 or when RTC_LOAD port is read by CPU. This bit will cleared automatically after the read or write procedure is done. Programmer can polling this bit to know if the RTC update is done or not. The update or read procedure take around 3 32K period, which is around 100 us */ + +/************** Bits definition for RTC_LOAD register ******************/ +#define RTC_LOAD_LOAD_Pos (0U) +#define RTC_LOAD_LOAD_Msk (0xFFFFFFFFU << RTC_LOAD_LOAD_Pos) /*!< 0xFFFFFFFF */ +#define RTC_LOAD_LOAD RTC_LOAD_LOAD_Msk /*!< This register is used to let RTC engine read data from RTC core. When programmer read from this port, the current time will be latched and programmer can read data from RTC_SEC ~ RTC_YEAR register. The read procedure will takes 3 32K cycles, programmer can check the BSY bit to know if the procedure is done. The read data from this port is invalid */ + +/************** Bits definition for RTC_INTSTS register ******************/ +//#define RTC_INTSTS_INTSTS0_Pos (0U) +//#define RTC_INTSTS_INTSTS0_Msk (0x1U << RTC_INTSTS_INTSTS0_Pos) /*!< 0x00000001 */ +//#define RTC_INTSTS_INTSTS0 RTC_INTSTS_INTSTS0_Msk /*!< Interrupt status 0, this interrupt is controlled by ITV and SITV. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS1_Pos (1U) +#define RTC_INTSTS_INTSTS1_Msk (0x1U << RTC_INTSTS_INTSTS1_Pos) /*!< 0x00000002 */ +#define RTC_INTSTS_INTSTS1 RTC_INTSTS_INTSTS1_Msk /*!< Interrupt status 1, this interrupt will be set when illegal time format is written into RTC core. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS2_Pos (2U) +#define RTC_INTSTS_INTSTS2_Msk (0x1U << RTC_INTSTS_INTSTS2_Pos) /*!< 0x00000004 */ +#define RTC_INTSTS_INTSTS2 RTC_INTSTS_INTSTS2_Msk /*!< Interrupt status 2, this interrupt will be set when multi-second interrupt period set by WKUSEC is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS3_Pos (3U) +#define RTC_INTSTS_INTSTS3_Msk (0x1U << RTC_INTSTS_INTSTS3_Pos) /*!< 0x00000008 */ +#define RTC_INTSTS_INTSTS3 RTC_INTSTS_INTSTS3_Msk /*!< Interrupt status 3, this interrupt will be set when multi-minute interrupt period set by WKUMIN is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS4_Pos (4U) +#define RTC_INTSTS_INTSTS4_Msk (0x1U << RTC_INTSTS_INTSTS4_Pos) /*!< 0x00000010 */ +#define RTC_INTSTS_INTSTS4 RTC_INTSTS_INTSTS4_Msk /*!< Interrupt status 4, this interrupt will be set when multi-hour interrupt period set by WKUHOUR is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS5_Pos (5U) +#define RTC_INTSTS_INTSTS5_Msk (0x1U << RTC_INTSTS_INTSTS5_Pos) /*!< 0x00000020 */ +#define RTC_INTSTS_INTSTS5 RTC_INTSTS_INTSTS5_Msk /*!< Interrupt status 5, this interrupt will be set when mid-night (00:00) is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS6_Pos (6U) +#define RTC_INTSTS_INTSTS6_Msk (0x1U << RTC_INTSTS_INTSTS6_Pos) /*!< 0x00000040 */ +#define RTC_INTSTS_INTSTS6 RTC_INTSTS_INTSTS6_Msk /*!< Interrupt status 6, this interrupt will be set when 32K counter interrupt period set by WKUCNT is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS7_Pos (7U) +#define RTC_INTSTS_INTSTS7_Msk (0x1U << RTC_INTSTS_INTSTS7_Pos) /*!< 0x00000080 */ +#define RTC_INTSTS_INTSTS7 RTC_INTSTS_INTSTS7_Msk /*!< Interrupt status 7, this interrupt will be set when an auto calibration is done. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS8_Pos (8U) +#define RTC_INTSTS_INTSTS8_Msk (0x1U << RTC_INTSTS_INTSTS8_Pos) /*!< 0x00000100 */ +#define RTC_INTSTS_INTSTS8 RTC_INTSTS_INTSTS8_Msk /*!< Interrupt status 8, this interrupt will be set when an illegal write to CE register is happened. The illegal write means the BSY bit is still 1 but CE is set to 1 again or RTC_LOAD port is read again. Write 1 to clear this bit */ +#define RTC_INTSTS_ACBSY_Pos (9U) +#define RTC_INTSTS_ACBSY_Msk (0x1U << RTC_INTSTS_ACBSY_Pos) /*!< 0x00000200 */ +#define RTC_INTSTS_ACBSY RTC_INTSTS_ACBSY_Msk /*!< Auto-calibration busy flag */ + +/************** Bits definition for RTC_INTEN register ******************/ +//#define RTC_INTEN_INTEN0_Pos (0U) +//#define RTC_INTEN_INTEN0_Msk (0x1U << RTC_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +//#define RTC_INTEN_INTEN0 RTC_INTEN_INTEN0_Msk /*!< Interrupt enable 0, when this bit is 1, the INTSTS0 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN1_Pos (1U) +#define RTC_INTEN_INTEN1_Msk (0x1U << RTC_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define RTC_INTEN_INTEN1 RTC_INTEN_INTEN1_Msk /*!< Interrupt enable 1, when this bit is 1, the INTSTS1 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN2_Pos (2U) +#define RTC_INTEN_INTEN2_Msk (0x1U << RTC_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define RTC_INTEN_INTEN2 RTC_INTEN_INTEN2_Msk /*!< Interrupt enable 2, when this bit is 1, the INTSTS2 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN3_Pos (3U) +#define RTC_INTEN_INTEN3_Msk (0x1U << RTC_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define RTC_INTEN_INTEN3 RTC_INTEN_INTEN3_Msk /*!< Interrupt enable 3, when this bit is 1, the INTSTS3 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN4_Pos (4U) +#define RTC_INTEN_INTEN4_Msk (0x1U << RTC_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +#define RTC_INTEN_INTEN4 RTC_INTEN_INTEN4_Msk /*!< Interrupt enable 4, when this bit is 1, the INTSTS3 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN5_Pos (5U) +#define RTC_INTEN_INTEN5_Msk (0x1U << RTC_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +#define RTC_INTEN_INTEN5 RTC_INTEN_INTEN5_Msk /*!< Interrupt enable 5, when this bit is 1, the INTSTS5 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN6_Pos (6U) +#define RTC_INTEN_INTEN6_Msk (0x1U << RTC_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +#define RTC_INTEN_INTEN6 RTC_INTEN_INTEN6_Msk /*!< Interrupt enable 6, when this bit is 1, the INTSTS6 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN7_Pos (7U) +#define RTC_INTEN_INTEN7_Msk (0x1U << RTC_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define RTC_INTEN_INTEN7 RTC_INTEN_INTEN7_Msk /*!< Interrupt enable 7, when this bit is 1, the INTSTS7 can be set, and interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN8_Pos (8U) +#define RTC_INTEN_INTEN8_Msk (0x1U << RTC_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define RTC_INTEN_INTEN8 RTC_INTEN_INTEN8_Msk /*!< Interrupt enable 8, when this bit is 1 and INTSTS86 is set, and interrupt will be asserted to CPU */ + +/************** Bits definition for RTC_PSCA register ******************/ +#define RTC_PSCA_PSCA_Pos (0U) +#define RTC_PSCA_PSCA_Msk (0x3U << RTC_PSCA_PSCA_Pos) /*!< 0x00000003 */ +#define RTC_PSCA_PSCA RTC_PSCA_PSCA_Msk /*!< This register is used to control the RTC clock pre-scaler. When slow down the RTC clock, it can significantly reduce the power under sleep or deep-sleep mode */ +#define RTC_PSCA_PSCA_0 (0x0U << RTC_PSCA_PSCA_Pos) +#define RTC_PSCA_PSCA_1 (0x1U << RTC_PSCA_PSCA_Pos) +//#define RTC_PSCA_PSCA_2 (0x2U << RTC_PSCA_PSCA_Pos) +//#define RTC_PSCA_PSCA_3 (0x3U << RTC_PSCA_PSCA_Pos) + +/************** Bits definition for RTC_ACCTRL register ******************/ +#define RTC_ACCTRL_ACEN_Pos (0U) +#define RTC_ACCTRL_ACEN_Msk (0x1U << RTC_ACCTRL_ACEN_Pos) /*!< 0x00000001 */ +#define RTC_ACCTRL_ACEN RTC_ACCTRL_ACEN_Msk /*!< Auto-calibration enable control register */ +#define RTC_ACCTRL_MANU_Pos (1U) +#define RTC_ACCTRL_MANU_Msk (0x1U << RTC_ACCTRL_MANU_Pos) /*!< 0x00000002 */ +#define RTC_ACCTRL_MANU RTC_ACCTRL_MANU_Msk /*!< Auto-calibration manual trigger function. Write 1 to this register will trigger an auto-calibration procedure. This bit will be cleared to 0 when the procedure is done */ +#define RTC_ACCTRL_ADCSEL_Pos (3U) +#define RTC_ACCTRL_ADCSEL_Msk (0x1U << RTC_ACCTRL_ADCSEL_Pos) /*!< 0x00000008 */ +#define RTC_ACCTRL_ADCSEL RTC_ACCTRL_ADCSEL_Msk /*!< ADC source select register */ +#define RTC_ACCTRL_ACCLK_Pos (4U) +#define RTC_ACCTRL_ACCLK_Msk (0x3U << RTC_ACCTRL_ACCLK_Pos) /*!< 0x00000030 */ +#define RTC_ACCTRL_ACCLK RTC_ACCTRL_ACCLK_Msk /*!< Auto-trigger clock source selection */ +#define RTC_ACCTRL_ACCLK_0 (0x0U << RTC_ACCTRL_ACCLK_Pos) +#define RTC_ACCTRL_ACCLK_1 (0x1U << RTC_ACCTRL_ACCLK_Pos) +#define RTC_ACCTRL_ACCLK_2 (0x2U << RTC_ACCTRL_ACCLK_Pos) +#define RTC_ACCTRL_ACCLK_3 (0x3U << RTC_ACCTRL_ACCLK_Pos) +#define RTC_ACCTRL_ACDEL_Pos (6U) +#define RTC_ACCTRL_ACDEL_Msk (0x3U << RTC_ACCTRL_ACDEL_Pos) /*!< 0x000000C0 */ +#define RTC_ACCTRL_ACDEL RTC_ACCTRL_ACDEL_Msk /*!< Auto-calibration delay period selection, before doing auto-calibration, a specified delay will be applied to ensure the main power is stable */ +#define RTC_ACCTRL_ACDEL_0 (0x0U << RTC_ACCTRL_ACDEL_Pos) +#define RTC_ACCTRL_ACDEL_1 (0x1U << RTC_ACCTRL_ACDEL_Pos) +#define RTC_ACCTRL_ACDEL_2 (0x2U << RTC_ACCTRL_ACDEL_Pos) +#define RTC_ACCTRL_ACDEL_3 (0x3U << RTC_ACCTRL_ACDEL_Pos) +#define RTC_ACCTRL_ACPER_Pos (8U) +#define RTC_ACCTRL_ACPER_Msk (0x3FU << RTC_ACCTRL_ACPER_Pos) /*!< 0x00003F00 */ +#define RTC_ACCTRL_ACPER RTC_ACCTRL_ACPER_Msk /*!< Auto trigger period control register, the actual period is controlled by (ACPER + 1)*ACCLK. For example, when ACCLK is set to 2 (1 minute), and ACPER is set to 5, then the auto trigger period is (5+1)*1 minute = 6 minutes */ + +/************** Bits definition for RTC_ACTI register ******************/ +#define RTC_ACTI_ACTI_Pos (0U) +#define RTC_ACTI_ACTI_Msk (0x3FFFU << RTC_ACTI_ACTI_Pos) /*!< 0x00003FFF */ +#define RTC_ACTI_ACTI RTC_ACTI_ACTI_Msk /*!< Auto-calibration Ti control register. This register is used to store the Ti value which is used as the center temperature during calibration. This register is 8 bits integer and 8 bits fraction value. For example, 0x1880 means 24.5 degree. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ + +/************** Bits definition for RTC_ACF200 register ******************/ +#define RTC_ACF200_F200_Pos (0U) +#define RTC_ACF200_F200_Msk (0x3FFFFFFU << RTC_ACF200_F200_Pos) /*!< 0x03FFFFFF */ +#define RTC_ACF200_F200 RTC_ACF200_F200_Msk /*!< Auto-calibration F200 control register. This register is used to store the current PCLK speed value which is used for the calculation of PLLDIV value. This register is 26 bits integer */ + +/************** Bits definition for RTC_ACADCW register ******************/ +#define RTC_ACADCW_ADCW_Pos (0U) +#define RTC_ACADCW_ADCW_Msk (0xFFFU << RTC_ACADCW_ADCW_Pos) /*!< 0x00000FFF */ +#define RTC_ACADCW_ADCW RTC_ACADCW_ADCW_Msk /*!< Auto-calibration manual ADC value control register. This register is used to store the manual ADC value which is used for the calculation for temperature. By default, the auto-calibration engine will read the ADC value automatically, but if programmer wishes to control the ADC value manually, this register can be used to control the ADC value read by the engine. This register is 12 bits integer. This register is valid only when ADCSEL is set to 1 */ + +/************** Bits definition for RTC_ACP0 register ******************/ +#define RTC_ACP_P0_Pos (0U) +#define RTC_ACP_P0_Msk (0xFFFF << RTC_ACP_P0_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P0 RTC_ACP_P0_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP1 register ******************/ +#define RTC_ACP_P1_Pos (0U) +#define RTC_ACP_P1_Msk (0xFFFF << RTC_ACP_P1_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P1 RTC_ACP_P1_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP2 register ******************/ +#define RTC_ACP_P2_Pos (0U) +#define RTC_ACP_P2_Msk (0xFFFFFFFF << RTC_ACP_P2_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ACP_P2 RTC_ACP_P2_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP3 register ******************/ +#define RTC_ACP_P3_Pos (0U) +#define RTC_ACP_P3_Msk (0xFFFF << RTC_ACP_P3_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P3 RTC_ACP_P3_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP4 register ******************/ +#define RTC_ACP_P4_Pos (0U) +#define RTC_ACP_P4_Msk (0xFFFF << RTC_ACP_P4_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P4 RTC_ACP_P4_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP5 register ******************/ +#define RTC_ACP_P5_Pos (0U) +#define RTC_ACP_P5_Msk (0xFFFF << RTC_ACP_P5_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P5 RTC_ACP_P5_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP6 register ******************/ +#define RTC_ACP_P6_Pos (0U) +#define RTC_ACP_P6_Msk (0xFFFF << RTC_ACP_P6_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P6 RTC_ACP_P6_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP7 register ******************/ +#define RTC_ACP_P7_Pos (0U) +#define RTC_ACP_P7_Msk (0xFFFF << RTC_ACP_P7_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P7 RTC_ACP_P7_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACK1 register ******************/ +#define RTC_ACK_K1_Pos (0U) +#define RTC_ACK_K1_Msk (0xFFFFU << RTC_ACK_K1_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K1 RTC_ACK_K1_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACK2 register ******************/ +#define RTC_ACK_K2_Pos (0U) +#define RTC_ACK_K2_Msk (0xFFFFU << RTC_ACK_K2_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K2 RTC_ACK_K2_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACK3 register ******************/ +#define RTC_ACK_K3_Pos (0U) +#define RTC_ACK_K3_Msk (0xFFFFU << RTC_ACK_K3_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K3 RTC_ACK_K3_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACK4 register ******************/ +#define RTC_ACK_K4_Pos (0U) +#define RTC_ACK_K4_Msk (0xFFFFU << RTC_ACK_K4_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K4 RTC_ACK_K4_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACK5 register ******************/ +#define RTC_ACK_K5_Pos (0U) +#define RTC_ACK_K5_Msk (0xFFFFU << RTC_ACK_K5_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K5 RTC_ACK_K5_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACTEMP register ******************/ +#define RTC_ACTEMP_TEMP_Pos (0U) +#define RTC_ACTEMP_TEMP_Msk (0xFFFFU << RTC_ACTEMP_TEMP_Pos) /*!< 0x0000FFFF */ +#define RTC_ACTEMP_TEMP RTC_ACTEMP_TEMP_Msk /*!< This register is used to store the calculated result of current temperature. This register will be updated automatically after the auto-calibration procedure is done */ + +/************** Bits definition for RTC_ACPPM register ******************/ +#define RTC_ACPPM_PPM_Pos (0U) +#define RTC_ACPPM_PPM_Msk (0xFFFFU << RTC_ACPPM_PPM_Pos) /*!< 0x0000FFFF */ +#define RTC_ACPPM_PPM RTC_ACPPM_PPM_Msk /*!< This register is used to store the calculated result of current temperature. This register will be updated automatically after the auto-calibration procedure is done. This register is a 16 bits signed value and the unit of this register is 0.1 PPM */ + +/************** Bits definition for RTC_ACADCR register ******************/ +#define RTC_ACADCR_ADCR_Pos (0U) +#define RTC_ACADCR_ADCR_Msk (0xFFFFU << RTC_ACADCR_ADCR_Pos) /*!< 0x0000FFFF */ +#define RTC_ACADCR_ADCR RTC_ACADCR_ADCR_Msk /*!< This register is used to represent the ADC value used by the auto-calibration engine, the value of this register is the 12 bits ADC value * 8. When the ADCSEL is 0, it will store the value read from ADC and multiplied by 8, when ADCSEL is 1, this value will equal to ADCW *8 */ + +/************** Bits definition for RTC_ACKTEMP register ******************/ +#define RTC_ACKTEMP_KTEMP1_Pos (0U) +#define RTC_ACKTEMP_KTEMP1_Msk (0xFFU << RTC_ACKTEMP_KTEMP1_Pos) /*!< 0x000000FF */ +#define RTC_ACKTEMP_KTEMP1 RTC_ACKTEMP_KTEMP1_Msk /*!< This register is used to control the section 1 temperature. This is a signed 8 bits value. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ +#define RTC_ACKTEMP_KTEMP2_Pos (8U) +#define RTC_ACKTEMP_KTEMP2_Msk (0xFFU << RTC_ACKTEMP_KTEMP2_Pos) /*!< 0x0000FF00 */ +#define RTC_ACKTEMP_KTEMP2 RTC_ACKTEMP_KTEMP2_Msk /*!< This register is used to control the section 2 temperature. This is a signed 8 bits value. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ +#define RTC_ACKTEMP_KTEMP3_Pos (16U) +#define RTC_ACKTEMP_KTEMP3_Msk (0xFFU << RTC_ACKTEMP_KTEMP3_Pos) /*!< 0x00FF0000 */ +#define RTC_ACKTEMP_KTEMP3 RTC_ACKTEMP_KTEMP3_Msk /*!< This register is used to control the section 3 temperature. This is a signed 8 bits value. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ +#define RTC_ACKTEMP_KTEMP4_Pos (24U) +#define RTC_ACKTEMP_KTEMP4_Msk (0xFFU << RTC_ACKTEMP_KTEMP4_Pos) /*!< 0xFF000000 */ +#define RTC_ACKTEMP_KTEMP4 RTC_ACKTEMP_KTEMP4_Msk /*!< This register is used to control the section 3 temperature. This is a signed 8 bits value. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ + +/************** Bits definition for RTC_ACOPx register ******************/ +#define RTC_ACOP_OP_Pos (0U) +#define RTC_ACOP_OP_Msk (0x1FFU << RTC_ACOP_OP_Pos) /*!< 0x000001FF */ +#define RTC_ACOP_OP RTC_ACOP_OP_Msk /*!< The OP0~OP63 register is valid only for FPGA. These Ops are used for internal ALU to calculate the auto-calibration data. Before the auto-calibration procedure, all necessary OP should be program correctly into these registers. For real chip, this part will become ROM table and no longer be able to read/write by CPU */ + +/******************************************************************************/ +/* */ +/* FLASH controller (FLASH) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for FLASH_STS register ******************/ +#define FLASH_STS_Pos (0U) +#define FLASH_STS_Msk (0x1U << FLASH_STS_Pos) /*!< 0x00000001 */ +#define FLASH_STS FLASH_STS_Msk /*!< */ + +/************** Bits definition for FLASH_NVRPASS register ******************/ +#define FLASH_NVRPASS_Pos (0U) +#define FLASH_NVRPASS_Msk (0xFFFFFFFFU << FLASH_NVRPASS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_NVRPASS_NVRPASS FLASH_NVRPASS_Msk /*!< programmer should write 0xAA5555AA to this register */ +#define FLASH_NVRPASS_NVRUNLOCK_Pos (0U) +#define FLASH_NVRPASS_NVRUNLOCK_Msk (0x1U << FLASH_NVRPASS_NVRUNLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_NVRPASS_NVRUNLOCK FLASH_NVRPASS_NVRUNLOCK_Msk /*!< The NVRUNLOCK bit is used to indicate the NVR sector program has been unlocked or not */ + +/************** Bits definition for FLASH_BDPASS register ******************/ +//#define FLASH_BDPASS_BDEN_Pos (0U) +//#define FLASH_BDPASS_BDEN_Msk (0x1U << FLASH_BDPASS_BDEN_Pos) /*!< 0x00000001 */ +//#define FLASH_BDPASS_BDEN FLASH_BDPASS_BDEN_Msk /*!< This register is not opened for customer */ + +/************** Bits definition for FLASH_KEY register ******************/ +#define FLASH_KEY_Pos (0U) +#define FLASH_KEY_Msk (0xFFFFFFFFU << FLASH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEY_KEY FLASH_KEY_Msk /*!< The KEY register is used to unlock those blocked function */ + +/************** Bits definition for FLASH_INT register ******************/ +#define FLASH_INT_CSERR_Pos (0U) +#define FLASH_INT_CSERR_Msk (0x1U << FLASH_INT_CSERR_Pos) /*!< 0x00000001 */ +#define FLASH_INT_CSERR FLASH_INT_CSERR_Msk /*!< Checksum error status bit */ + +/************** Bits definition for FLASH_CSSADDR register ******************/ +#define FLASH_CSSADDR_Pos (0U) +#define FLASH_CSSADDR_Msk (0x3FFFFU << FLASH_CSSADDR_Pos) /*!< 0x0003FFFF */ +#define FLASH_CSSADDR_CSSADDR FLASH_CSSADDR_Msk /*!< Checksum start address register */ + +/************** Bits definition for FLASH_CSEADDR register ******************/ +#define FLASH_CSEADDR_Pos (0U) +#define FLASH_CSEADDR_Msk (0x3FFFFU << FLASH_CSEADDR_Pos) /*!< 0x0003FFFF */ +#define FLASH_CSEADDR_CSEADDR FLASH_CSEADDR_Msk /*!< Checksum end address register */ + +/************** Bits definition for FLASH_CSVALUE register ******************/ +#define FLASH_CSVALUE_Pos (0U) +#define FLASH_CSVALUE_Msk (0xFFFFFFFFU << FLASH_CSVALUE_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CSVALUE_CSVALUE FLASH_CSVALUE_Msk /*!< Checksum latched value register */ + +/************** Bits definition for FLASH_CSCVALUE register ******************/ +#define FLASH_CSCVALUE_Pos (0U) +#define FLASH_CSCVALUE_Msk (0xFFFFFFFFU << FLASH_CSCVALUE_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CSCVALUE_CSCVALUE FLASH_CSCVALUE_Msk /*!< Checksum compare value register */ + +/************** Bits definition for FLASH_PASS register ******************/ +#define FLASH_PASS_Pos (0U) +#define FLASH_PASS_Msk (0xFFFFFFFFU << FLASH_PASS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PASS_PASS FLASH_PASS_Msk /*!< programmer should write 0x55AAAA55 to this register */ +#define FLASH_PASS_UNLOCK_Pos (0U) +#define FLASH_PASS_UNLOCK_Msk (0x1U << FLASH_PASS_UNLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_PASS_UNLOCK FLASH_PASS_UNLOCK_Msk /*!< The UNLOCK bit is used to indicate the Flash program has been unlocked or not */ + +/************** Bits definition for FLASH_CTRL register ******************/ +#define FLASH_CTRL_CSMODE_Pos (0U) +#define FLASH_CTRL_CSMODE_Msk (0x3U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000003 */ +#define FLASH_CTRL_CSMODE FLASH_CTRL_CSMODE_Msk /*!< This register is used to control the checksum mode */ +#define FLASH_CTRL_CSMODE_DISABLE (0x0U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000000 */ +#define FLASH_CTRL_CSMODE_ALWAYSON (0x1U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000001 */ +#define FLASH_CTRL_CSMODE_TIM2OV (0x2U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000002 */ +#define FLASH_CTRL_CSMODE_RTC (0x3U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000003 */ +#define FLASH_CTRL_CSINTEN_Pos (2U) +#define FLASH_CTRL_CSINTEN_Msk (0x1U << FLASH_CTRL_CSINTEN_Pos) /*!< 0x00000004 */ +#define FLASH_CTRL_CSINTEN FLASH_CTRL_CSINTEN_Msk /*!< This register is used to control the interrupt enable of checksum error */ +//#define FLASH_CTRL_READM0_Pos (4U) +//#define FLASH_CTRL_READM0_Msk (0x1U << FLASH_CTRL_READM0_Pos) /*!< 0x00000010 */ +//#define FLASH_CTRL_READM0 FLASH_CTRL_READM0_Msk /*!< This bit is used to control the READM0 pin of Flash IP */ +//#define FLASH_CTRL_READM1_Pos (5U) +//#define FLASH_CTRL_READM1_Msk (0x1U << FLASH_CTRL_READM1_Pos) /*!< 0x00000020 */ +//#define FLASH_CTRL_READM1 FLASH_CTRL_READM1_Msk /*!< This bit is used to control the READM1 pin of Flash IP */ +//#define FLASH_CTRL_NVR_Pos (6U) +//#define FLASH_CTRL_NVR_Msk (0x1U << FLASH_CTRL_NVR_Pos) /*!< 0x00000040 */ +//#define FLASH_CTRL_NVR FLASH_CTRL_NVR_Msk /*!< This register is used to control the NVR program */ +//#define FLASH_CTRL_SFTRST_Pos (7U) +//#define FLASH_CTRL_SFTRST_Msk (0x1U << FLASH_CTRL_SFTRST_Pos) /*!< 0x00000080 */ +//#define FLASH_CTRL_SFTRST FLASH_CTRL_SFTRST_Msk /*!< This register is used to reset the internal FIFO, just for test usage */ +//#define FLASH_CTRL_FORCESWAP_Pos (8U) +//#define FLASH_CTRL_FORCESWAP_Msk (0x1U << FLASH_CTRL_FORCESWAP_Pos) /*!< 0x00000100 */ +//#define FLASH_CTRL_FORCESWAP FLASH_CTRL_FORCESWAP_Msk /*!< This register is used to control the swap function in-between normal sector and NVR sector */ + +/************** Bits definition for FLASH_PGADDR register ******************/ +#define FLASH_PGADDR_Pos (0U) +#define FLASH_PGADDR_Msk (0x3FFFFU << FLASH_PGADDR_Pos) /*!< 0x0003FFFF */ +#define FLASH_PGADDR_PGADDR FLASH_PGADDR_Msk /*!< This register is used to control the program address before doing program */ + +/************** Bits definition for FLASH_PGDATA register ******************/ +#define FLASH_PGDATA_Pos (0U) +#define FLASH_PGDATA_Msk (0xFFFFFFFFU << FLASH_PGDATA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PGDATA_PGDATA FLASH_PGDATA_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDB0 register ******************/ +#define FLASH_PGDB0_Pos (0U) +#define FLASH_PGDB0_Msk (0xFFU << FLASH_PGDB0_Pos) /*!< 0x000000FF */ +#define FLASH_PGDB0 FLASH_PGDB0_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDB1 register ******************/ +#define FLASH_PGDB1_Pos (0U) +#define FLASH_PGDB1_Msk (0xFFU << FLASH_PGDB1_Pos) /*!< 0x000000FF */ +#define FLASH_PGDB1 FLASH_PGDB1_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDB2 register ******************/ +#define FLASH_PGDB2_Pos (0U) +#define FLASH_PGDB2_Msk (0xFFU << FLASH_PGDB2_Pos) /*!< 0x000000FF */ +#define FLASH_PGDB2 FLASH_PGDB2_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDB3 register ******************/ +#define FLASH_PGDB3_Pos (0U) +#define FLASH_PGDB3_Msk (0xFFU << FLASH_PGDB3_Pos) /*!< 0x000000FF */ +#define FLASH_PGDB3 FLASH_PGDB3_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDHW0 register ******************/ +#define FLASH_PGDHW0_Pos (0U) +#define FLASH_PGDHW0_Msk (0xFFFFU << FLASH_PGDHW0_Pos) /*!< 0x0000FFFF */ +#define FLASH_PGDHW0 FLASH_PGDHW0_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDHW1 register ******************/ +#define FLASH_PGDHW1_Pos (0U) +#define FLASH_PGDHW1_Msk (0xFFFFU << FLASH_PGDHW1_Pos) /*!< 0x0000FFFF */ +#define FLASH_PGDHW1 FLASH_PGDHW1_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_CONF register ******************/ +//#define FLASH_CONF_Pos (0U) +//#define FLASH_CONF_Msk (0xFFFFFFFFU << FLASH_CONF_Pos) /*!< 0xFFFFFFFF */ +//#define FLASH_CONF_CONF FLASH_CONF_Msk /*!< This register is used to read/write the Flash IP��s configuration register */ + +/************** Bits definition for FLASH_SERASE register ******************/ +#define FLASH_SERASE_Pos (0U) +#define FLASH_SERASE_Msk (0xFFFFFFFFU << FLASH_SERASE_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_SERASE_SERASE FLASH_SERASE_Msk /*!< This bit can be set when UNLOCK is 1 and programmer write 0xAA5555AA to this register */ +#define FLASH_SERASE_BIT0_Pos (0U) +#define FLASH_SERASE_BIT0_Msk (0x1U << FLASH_SERASE_BIT0_Pos) /*!< 0x00000001 */ +#define FLASH_SERASE_BIT0 FLASH_SERASE_BIT0_Msk /*!< This bit is used to indicate if the sector erase is ongoing or not */ + +/************** Bits definition for FLASH_CERASE register ******************/ +#define FLASH_CERASE_Pos (0U) +#define FLASH_CERASE_Msk (0xFFFFFFFFU << FLASH_CERASE_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CERASE_CERASE FLASH_CERASE_Msk /*!< This bit can be set when UNLOCK is 1 and programmer write 0xAA5555AA to this register */ +#define FLASH_CERASE_BIT0_Pos (0U) +#define FLASH_CERASE_BIT0_Msk (0x1U << FLASH_CERASE_BIT0_Pos) /*!< 0x00000001 */ +#define FLASH_CERASE_BIT0 FLASH_CERASE_BIT0_Msk /*!< This bit is used to indicate if the chip erase is ongoing or not */ + +/************** Bits definition for FLASH_DSTB register ******************/ +#define FLASH_DSTB_Pos (0U) +#define FLASH_DSTB_Msk (0xFFFFFFFFU << FLASH_DSTB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_DSTB_DSTB FLASH_DSTB_Msk /*!< This bit can be set when UNLOCK is 1 and programmer write 0xAA5555AA to this register */ +#define FLASH_DSTB_BIT0_Pos (0U) +#define FLASH_DSTB_BIT0_Msk (0x1U << FLASH_DSTB_BIT0_Pos) /*!< 0x00000001 */ +#define FLASH_DSTB_BIT0 FLASH_DSTB_BIT0_Msk /*!< This bit is used to indicate if the Flash IP is entering deep standby */ + + +/******************************************************************************/ +/* */ +/* GPIO controller (GPIO) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for IOx_OEN register ******************/ +#define IOx_OEN_IOXOEN_Pos (0U) +#define IOx_OEN_IOXOEN_Msk (0xFFFFU << IOx_OEN_IOXOEN_Pos) /*!< 0x0000FFFF */ +#define IOx_OEN_IOXOEN IOx_OEN_IOXOEN_Msk /*!< Each bit control the IOX��s output enable signal */ + +/************** Bits definition for IOx_IE register ******************/ +#define IOx_IE_IOXIE_Pos (0U) +#define IOx_IE_IOXIE_Msk (0xFFFFU << IOx_IE_IOXIE_Pos) /*!< 0x0000FFFF */ +#define IOx_IE_IOXIE IOx_IE_IOXIE_Msk /*!< Each bit control the IOX��s input enable signal */ + +/************** Bits definition for IOx_DAT register ******************/ +#define IOx_DAT_IOXDAT_Pos (0U) +#define IOx_DAT_IOXDAT_Msk (0xFFFFU << IOx_DAT_IOXDAT_Pos) /*!< 0x0000FFFF */ +#define IOx_DAT_IOXDAT IOx_DAT_IOXDAT_Msk /*!< Each bit control the IOX��s output data and pull low/high function */ + +/************** Bits definition for IOx_ATT register ******************/ +#define IOx_ATT_IOXATT_Pos (0U) +#define IOx_ATT_IOXATT_Msk (0xFFFFU << IOx_ATT_IOXATT_Pos) /*!< 0x0000FFFF */ +#define IOx_ATT_IOXATT IOx_ATT_IOXATT_Msk /*!< Each bit control the IOX��s attribute and pull low/high function */ + +/************** Bits definition for IOx_STS register ******************/ +#define IOx_STS_IOXSTS_Pos (0U) +#define IOx_STS_IOXSTS_Msk (0xFFFFU << IOx_STS_IOXSTS_Pos) /*!< 0x0000FFFF */ +#define IOx_STS_IOXSTS IOx_STS_IOXSTS_Msk /*!< Each bit represents the current IOX��s input data value */ + +///************** Bits definition for IOx_CM register ******************/ +//#define IOx_CM_IOXCM0_Pos (0U) +//#define IOx_CM_IOXCM0_Msk (0x1U << IOx_CM_IOXCM0_Pos) /*!< 0x00000001 */ +//#define IOx_CM_IOXCM0 IOx_CM_IOXCM0_Msk /*!< IOX0��s Schmitt trigger setting, change to this register will change all setting of IOX0~IOX7 */ +//#define IOx_CM_IOXCM1_7_Pos (1U) +//#define IOx_CM_IOXCM1_7_Msk (0x7FU << IOx_CM_IOXCM1_7_Pos) /*!< 0x000000FE */ +//#define IOx_CM_IOXCM1_7 IOx_CM_IOXCM1_7_Msk /*!< Each bit represent the current Schmitt trigger setting of IOX1~IOX7 */ +//#define IOx_CM_IOXCM8_Pos (8U) +//#define IOx_CM_IOXCM8_Msk (0x1U << IOx_CM_IOXCM8_Pos) /*!< 0x00000100 */ +//#define IOx_CM_IOXCM8 IOx_CM_IOXCM8_Msk /*!< IOX8��s Schmitt trigger setting, change to this register will change all setting of IOX8~IOX15 */ +//#define IOx_CM_IOXCM9_15_Pos (9U) +//#define IOx_CM_IOXCM9_15_Msk (0x7FU << IOx_CM_IOXCM9_15_Pos) /*!< 0x0000FE00 */ +//#define IOx_CM_IOXCM9_15 IOx_CM_IOXCM9_15_Msk /*!< Each bit represent the current Schmitt trigger setting of IOX9~IOX15 */ +// +///************** Bits definition for IOx_SR register ******************/ +//#define IOx_SR_IOXSR0_Pos (0U) +//#define IOx_SR_IOXSR0_Msk (0x1U << IOx_SR_IOXSR0_Pos) /*!< 0x00000001 */ +//#define IOx_SR_IOXSR0 IOx_SR_IOXSR0_Msk /*!< IOX0��s slew rate setting, change to this register will change all setting of IOX0~IOX7 */ +//#define IOx_SR_IOXSR1_7_Pos (1U) +//#define IOx_SR_IOXSR1_7_Msk (0x7FU << IOx_SR_IOXSR1_7_Pos) /*!< 0x000000FE */ +//#define IOx_SR_IOXSR1_7 IOx_SR_IOXSR1_7_Msk /*!< Each bit represent the current slew rate setting of IOX1~IOX7 */ +//#define IOx_SR_IOXSR8_Pos (8U) +//#define IOx_SR_IOXSR8_Msk (0x1U << IOx_SR_IOXSR8_Pos) /*!< 0x00000100 */ +//#define IOx_SR_IOXSR8 IOx_SR_IOXSR8_Msk /*!< IOX8��s slew rate setting, change to this register will change all setting of IOX8~IOX15 */ +//#define IOx_SR_IOXSR9_15_Pos (9U) +//#define IOx_SR_IOXSR9_15_Msk (0x7FU << IOx_SR_IOXSR9_15_Pos) /*!< 0x0000FE00 */ +//#define IOx_SR_IOXSR9_15 IOx_SR_IOXSR9_15_Msk /*!< Each bit represent the current slew rate setting of IOX9~IOX15 */ +// +///************** Bits definition for IOx_DR register ******************/ +//#define IOx_DR_IOXDR0_Pos (0U) +//#define IOx_DR_IOXDR0_Msk (0x1U << IOx_DR_IOXDR0_Pos) /*!< 0x00000001 */ +//#define IOx_DR_IOXDR0 IOx_DR_IOXDR0_Msk /*!< IOX0��s driving strength setting, change to this register will change all setting of IOX0~IOX7 */ +//#define IOx_DR_IOXDR1_7_Pos (1U) +//#define IOx_DR_IOXDR1_7_Msk (0x7FU << IOx_DR_IOXDR1_7_Pos) /*!< 0x000000FE */ +//#define IOx_DR_IOXDR1_7 IOx_DR_IOXDR1_7_Msk /*!< Each bit represent the current driving strength setting of IOX1~IOX7 */ +//#define IOx_DR_IOXDR8_Pos (8U) +//#define IOx_DR_IOXDR8_Msk (0x1U << IOx_DR_IOXDR8_Pos) /*!< 0x00000100 */ +//#define IOx_DR_IOXDR8 IOx_DR_IOXDR8_Msk /*!< IOX8��s driving strength setting, change to this register will change all setting of IOX8~IOX15 */ +//#define IOx_DR_IOXDR9_15_Pos (9U) +//#define IOx_DR_IOXDR9_15_Msk (0x7FU << IOx_DR_IOXDR9_15_Pos) /*!< 0x0000FE00 */ +//#define IOx_DR_IOXDR9_15 IOx_DR_IOXDR9_15_Msk /*!< Each bit represent the current driving strength setting of IOX9~IOX15 */ + +/************** Bits definition for IOB_SEL register ******************/ +#define IOB_SEL_SEL1_Pos (1U) +#define IOB_SEL_SEL1_Msk (0x1U << IOB_SEL_SEL1_Pos) /*!< 0x00000002 */ +#define IOB_SEL_SEL1 IOB_SEL_SEL1_Msk /*!< IOB1 special function select register */ +#define IOB_SEL_SEL2_Pos (2U) +#define IOB_SEL_SEL2_Msk (0x1U << IOB_SEL_SEL2_Pos) /*!< 0x00000004 */ +#define IOB_SEL_SEL2 IOB_SEL_SEL2_Msk /*!< IOB2 special function select register */ +#define IOB_SEL_SEL6_Pos (6U) +#define IOB_SEL_SEL6_Msk (0x1U << IOB_SEL_SEL6_Pos) /*!< 0x00000040 */ +#define IOB_SEL_SEL6 IOB_SEL_SEL6_Msk /*!< IOB6 special function select register */ + + +/************** Bits definition for IOE_SEL register ******************/ +#define IOE_SEL_SEL7_Pos (7U) +#define IOE_SEL_SEL7_Msk (0x1U << IOE_SEL_SEL7_Pos) /*!< 0x00000080 */ +#define IOE_SEL_SEL7 IOE_SEL_SEL7_Msk /*!< IOE7 special function select register */ + +/************** Bits definition for IO_MISC register ******************/ +#define IO_MISC_PLLHDIV_Pos (0U) +#define IO_MISC_PLLHDIV_Msk (0x7U << IO_MISC_PLLHDIV_Pos) /*!< 0x00000007 */ +#define IO_MISC_PLLHDIV IO_MISC_PLLHDIV_Msk /*!< When IOB1 is selected to special function 3, this register is used to control the divide ratio of PLLH��s output */ +#define IO_MISC_PLLHDIV_1 (0x0U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_2 (0x1U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_4 (0x2U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_8 (0x3U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_16 (0x4U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_I2CIOC_Pos (5U) +#define IO_MISC_I2CIOC_Msk (0x1U << IO_MISC_I2CIOC_Pos) /*!< 0x00000020 */ +#define IO_MISC_I2CIOC IO_MISC_I2CIOC_Msk /*!< This register is used to control the I2C function is at IOB or IOC */ + +/******************************************************************************/ +/* */ +/* DMA controller (DMA) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for DMA_IE register ******************/ +#define DMA_IE_C0PEIE_Pos (0U) +#define DMA_IE_C0PEIE_Msk (0x1U << DMA_IE_C0PEIE_Pos) /*!< 0x00000001 */ +#define DMA_IE_C0PEIE DMA_IE_C0PEIE_Msk /*!< Channel 0 package end interrupt enable */ +#define DMA_IE_C1PEIE_Pos (1U) +#define DMA_IE_C1PEIE_Msk (0x1U << DMA_IE_C1PEIE_Pos) /*!< 0x00000002 */ +#define DMA_IE_C1PEIE DMA_IE_C1PEIE_Msk /*!< Channel 1 package end interrupt enable */ +#define DMA_IE_C2PEIE_Pos (2U) +#define DMA_IE_C2PEIE_Msk (0x1U << DMA_IE_C2PEIE_Pos) /*!< 0x00000004 */ +#define DMA_IE_C2PEIE DMA_IE_C2PEIE_Msk /*!< Channel 2 package end interrupt enable */ +#define DMA_IE_C3PEIE_Pos (3U) +#define DMA_IE_C3PEIE_Msk (0x1U << DMA_IE_C3PEIE_Pos) /*!< 0x00000008 */ +#define DMA_IE_C3PEIE DMA_IE_C3PEIE_Msk /*!< Channel 3 package end interrupt enable */ +#define DMA_IE_C0FEIE_Pos (4U) +#define DMA_IE_C0FEIE_Msk (0x1U << DMA_IE_C0FEIE_Pos) /*!< 0x00000010 */ +#define DMA_IE_C0FEIE DMA_IE_C0FEIE_Msk /*!< Channel 0 frame end interrupt enable */ +#define DMA_IE_C1FEIE_Pos (5U) +#define DMA_IE_C1FEIE_Msk (0x1U << DMA_IE_C1FEIE_Pos) /*!< 0x00000020 */ +#define DMA_IE_C1FEIE DMA_IE_C1FEIE_Msk /*!< Channel 1 frame end interrupt enable */ +#define DMA_IE_C2FEIE_Pos (6U) +#define DMA_IE_C2FEIE_Msk (0x1U << DMA_IE_C2FEIE_Pos) /*!< 0x00000040 */ +#define DMA_IE_C2FEIE DMA_IE_C2FEIE_Msk /*!< Channel 2 frame end interrupt enable */ +#define DMA_IE_C3FEIE_Pos (7U) +#define DMA_IE_C3FEIE_Msk (0x1U << DMA_IE_C3FEIE_Pos) /*!< 0x00000080 */ +#define DMA_IE_C3FEIE DMA_IE_C3FEIE_Msk /*!< Channel 3 frame end interrupt enable */ +#define DMA_IE_C0DAIE_Pos (8U) +#define DMA_IE_C0DAIE_Msk (0x1U << DMA_IE_C0DAIE_Pos) /*!< 0x00000100 */ +#define DMA_IE_C0DAIE DMA_IE_C0DAIE_Msk /*!< Channel 0 data about interrupt enable */ +#define DMA_IE_C1DAIE_Pos (9U) +#define DMA_IE_C1DAIE_Msk (0x1U << DMA_IE_C1DAIE_Pos) /*!< 0x00000200 */ +#define DMA_IE_C1DAIE DMA_IE_C1DAIE_Msk /*!< Channel 1 data about interrupt enable */ +#define DMA_IE_C2DAIE_Pos (10U) +#define DMA_IE_C2DAIE_Msk (0x1U << DMA_IE_C2DAIE_Pos) /*!< 0x00000400 */ +#define DMA_IE_C2DAIE DMA_IE_C2DAIE_Msk /*!< Channel 2 data about interrupt enable */ +#define DMA_IE_C3DAIE_Pos (11U) +#define DMA_IE_C3DAIE_Msk (0x1U << DMA_IE_C3DAIE_Pos) /*!< 0x00000800 */ +#define DMA_IE_C3DAIE DMA_IE_C3DAIE_Msk /*!< Channel 3 data about interrupt enable */ + +/************** Bits definition for DMA_STS register ******************/ +#define DMA_STS_C0BUSY_Pos (0U) +#define DMA_STS_C0BUSY_Msk (0x1U << DMA_STS_C0BUSY_Pos) /*!< 0x00000001 */ +#define DMA_STS_C0BUSY DMA_STS_C0BUSY_Msk /*!< DMA channel 0 busy register */ +#define DMA_STS_C1BUSY_Pos (1U) +#define DMA_STS_C1BUSY_Msk (0x1U << DMA_STS_C1BUSY_Pos) /*!< 0x00000002 */ +#define DMA_STS_C1BUSY DMA_STS_C1BUSY_Msk /*!< DMA channel 1 busy register */ +#define DMA_STS_C2BUSY_Pos (2U) +#define DMA_STS_C2BUSY_Msk (0x1U << DMA_STS_C2BUSY_Pos) /*!< 0x00000004 */ +#define DMA_STS_C2BUSY DMA_STS_C2BUSY_Msk /*!< DMA channel 2 busy register */ +#define DMA_STS_C3BUSY_Pos (3U) +#define DMA_STS_C3BUSY_Msk (0x1U << DMA_STS_C3BUSY_Pos) /*!< 0x00000008 */ +#define DMA_STS_C3BUSY DMA_STS_C3BUSY_Msk /*!< DMA channel 3 busy register */ +#define DMA_STS_C0PE_Pos (4U) +#define DMA_STS_C0PE_Msk (0x1U << DMA_STS_C0PE_Pos) /*!< 0x00000010 */ +#define DMA_STS_C0PE DMA_STS_C0PE_Msk /*!< Channel 0 package end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C1PE_Pos (5U) +#define DMA_STS_C1PE_Msk (0x1U << DMA_STS_C1PE_Pos) /*!< 0x00000020 */ +#define DMA_STS_C1PE DMA_STS_C1PE_Msk /*!< Channel 1 package end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C2PE_Pos (6U) +#define DMA_STS_C2PE_Msk (0x1U << DMA_STS_C2PE_Pos) /*!< 0x00000040 */ +#define DMA_STS_C2PE DMA_STS_C2PE_Msk /*!< Channel 2 package end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C3PE_Pos (7U) +#define DMA_STS_C3PE_Msk (0x1U << DMA_STS_C3PE_Pos) /*!< 0x00000080 */ +#define DMA_STS_C3PE DMA_STS_C3PE_Msk /*!< Channel 3 package end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C0FE_Pos (8U) +#define DMA_STS_C0FE_Msk (0x1U << DMA_STS_C0FE_Pos) /*!< 0x00000100 */ +#define DMA_STS_C0FE DMA_STS_C0FE_Msk /*!< Channel 0 frame end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C1FE_Pos (9U) +#define DMA_STS_C1FE_Msk (0x1U << DMA_STS_C1FE_Pos) /*!< 0x00000200 */ +#define DMA_STS_C1FE DMA_STS_C1FE_Msk /*!< Channel 1 frame end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C2FE_Pos (10U) +#define DMA_STS_C2FE_Msk (0x1U << DMA_STS_C2FE_Pos) /*!< 0x00000400 */ +#define DMA_STS_C2FE DMA_STS_C2FE_Msk /*!< Channel 2 frame end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C3FE_Pos (11U) +#define DMA_STS_C3FE_Msk (0x1U << DMA_STS_C3FE_Pos) /*!< 0x00000800 */ +#define DMA_STS_C3FE DMA_STS_C3FE_Msk /*!< Channel 3 frame end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C0DA_Pos (12U) +#define DMA_STS_C0DA_Msk (0x1U << DMA_STS_C0DA_Pos) /*!< 0x00001000 */ +#define DMA_STS_C0DA DMA_STS_C0DA_Msk /*!< Channel 0 data about interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C1DA_Pos (13U) +#define DMA_STS_C1DA_Msk (0x1U << DMA_STS_C1DA_Pos) /*!< 0x00002000 */ +#define DMA_STS_C1DA DMA_STS_C1DA_Msk /*!< Channel 1 data about interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C2DA_Pos (14U) +#define DMA_STS_C2DA_Msk (0x1U << DMA_STS_C2DA_Pos) /*!< 0x00004000 */ +#define DMA_STS_C2DA DMA_STS_C2DA_Msk /*!< Channel 2 data about interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C3DA_Pos (15U) +#define DMA_STS_C3DA_Msk (0x1U << DMA_STS_C3DA_Pos) /*!< 0x00008000 */ +#define DMA_STS_C3DA DMA_STS_C3DA_Msk /*!< Channel 3 data about interrupt flag, write 1 to clear this flag */ + +/************** Bits definition for DMA_CxCTL register ******************/ +#define DMA_CxCTL_EN_Pos (0U) +#define DMA_CxCTL_EN_Msk (0x1U << DMA_CxCTL_EN_Pos) /*!< 0x00000001 */ +#define DMA_CxCTL_EN DMA_CxCTL_EN_Msk /*!< DMA channel enable register */ +#define DMA_CxCTL_SIZE_Pos (1U) +#define DMA_CxCTL_SIZE_Msk (0x3U << DMA_CxCTL_SIZE_Pos) /*!< 0x00000006 */ +#define DMA_CxCTL_SIZE DMA_CxCTL_SIZE_Msk /*!< Transfer size mode */ +#define DMA_CxCTL_SIZE_BYTE (0x0U << DMA_CxCTL_SIZE_Pos) /*!< 0x00000000 */ +#define DMA_CxCTL_SIZE_HWORD (0x1U << DMA_CxCTL_SIZE_Pos) /*!< 0x00000002 */ +#define DMA_CxCTL_SIZE_WORD (0x2U << DMA_CxCTL_SIZE_Pos) /*!< 0x00000004 */ +#define DMA_CxCTL_SMODE_Pos (3U) +#define DMA_CxCTL_SMODE_Msk (0x3U << DMA_CxCTL_SMODE_Pos) /*!< 0x00000018 */ +#define DMA_CxCTL_SMODE DMA_CxCTL_SMODE_Msk /*!< Source address mode */ +#define DMA_CxCTL_SMODE_FIX (0x0U << DMA_CxCTL_SMODE_Pos) /*!< 0x00000000 */ +#define DMA_CxCTL_SMODE_PEND (0x1U << DMA_CxCTL_SMODE_Pos) /*!< 0x00000080 */ +#define DMA_CxCTL_SMODE_FEND (0x2U << DMA_CxCTL_SMODE_Pos) /*!< 0x00000010 */ +#define DMA_CxCTL_DMODE_Pos (5U) +#define DMA_CxCTL_DMODE_Msk (0x3U << DMA_CxCTL_DMODE_Pos) /*!< 0x00000060 */ +#define DMA_CxCTL_DMODE DMA_CxCTL_DMODE_Msk /*!< Destination address mode */ +#define DMA_CxCTL_DMODE_FIX (0x0U << DMA_CxCTL_DMODE_Pos) /*!< 0x00000000 */ +#define DMA_CxCTL_DMODE_PEND (0x1U << DMA_CxCTL_DMODE_Pos) /*!< 0x00000020 */ +#define DMA_CxCTL_DMODE_FEND (0x2U << DMA_CxCTL_DMODE_Pos) /*!< 0x00000040 */ +#define DMA_CTL_DMASEL_Pos (7U) +#define DMA_CTL_DMASEL_Msk (0x1FU << DMA_CTL_DMASEL_Pos) /*!< 0x00000F80 */ +#define DMA_CTL_DMASEL DMA_CTL_DMASEL_Msk /*!< DMA request source selection */ +#define DMA_CTL_DMASEL_SOFT (0x0U << DMA_CTL_DMASEL_Pos) /*!< 0x00000000 */ +#define DMA_CTL_DMASEL_UART0TX (0x2U << DMA_CTL_DMASEL_Pos) /*!< 0x00000100 */ +#define DMA_CTL_DMASEL_UART0RX (0x3U << DMA_CTL_DMASEL_Pos) /*!< 0x00000180 */ +#define DMA_CTL_DMASEL_UART1TX (0x4U << DMA_CTL_DMASEL_Pos) /*!< 0x00000200 */ +#define DMA_CTL_DMASEL_UART1RX (0x5U << DMA_CTL_DMASEL_Pos) /*!< 0x00000280 */ +#define DMA_CTL_DMASEL_UART2TX (0x6U << DMA_CTL_DMASEL_Pos) /*!< 0x00000300 */ +#define DMA_CTL_DMASEL_UART2RX (0x7U << DMA_CTL_DMASEL_Pos) /*!< 0x00000380 */ +#define DMA_CTL_DMASEL_UART3TX (0x8U << DMA_CTL_DMASEL_Pos) /*!< 0x00000400 */ +#define DMA_CTL_DMASEL_UART3RX (0x9U << DMA_CTL_DMASEL_Pos) /*!< 0x00000480 */ +#define DMA_CTL_DMASEL_UART4TX (0xAU << DMA_CTL_DMASEL_Pos) /*!< 0x00000500 */ +#define DMA_CTL_DMASEL_UART4RX (0xBU << DMA_CTL_DMASEL_Pos) /*!< 0x00000580 */ +#define DMA_CTL_DMASEL_UART5TX (0xCU << DMA_CTL_DMASEL_Pos) /*!< 0x00000600 */ +#define DMA_CTL_DMASEL_UART5RX (0xDU << DMA_CTL_DMASEL_Pos) /*!< 0x00000680 */ +#define DMA_CTL_DMASEL_ISO78160TX (0xEU << DMA_CTL_DMASEL_Pos) /*!< 0x00000700 */ +#define DMA_CTL_DMASEL_ISO78160RX (0xFU << DMA_CTL_DMASEL_Pos) /*!< 0x00000780 */ +#define DMA_CTL_DMASEL_ISO78161TX (0x10U << DMA_CTL_DMASEL_Pos) /*!< 0x00000800 */ +#define DMA_CTL_DMASEL_ISO78161RX (0x11U << DMA_CTL_DMASEL_Pos) /*!< 0x00000880 */ +#define DMA_CTL_DMASEL_TIMER0 (0x12U << DMA_CTL_DMASEL_Pos) /*!< 0x00000900 */ +#define DMA_CTL_DMASEL_TIMER1 (0x13U << DMA_CTL_DMASEL_Pos) /*!< 0x00000980 */ +#define DMA_CTL_DMASEL_TIMER2 (0x14U << DMA_CTL_DMASEL_Pos) /*!< 0x00000A00 */ +#define DMA_CTL_DMASEL_TIMER3 (0x15U << DMA_CTL_DMASEL_Pos) /*!< 0x00000A80 */ +#define DMA_CTL_DMASEL_SPI1TX (0x16U << DMA_CTL_DMASEL_Pos) /*!< 0x00000B00 */ +#define DMA_CTL_DMASEL_SPI1RX (0x17U << DMA_CTL_DMASEL_Pos) /*!< 0x00000B80 */ +#define DMA_CTL_DMASEL_U32K0 (0x18U << DMA_CTL_DMASEL_Pos) /*!< 0x00000C00 */ +#define DMA_CTL_DMASEL_U32K1 (0x19U << DMA_CTL_DMASEL_Pos) /*!< 0x00000C80 */ +#define DMA_CTL_DMASEL_CMP1 (0x1AU << DMA_CTL_DMASEL_Pos) /*!< 0x00000D00 */ +#define DMA_CTL_DMASEL_CMP2 (0x1BU << DMA_CTL_DMASEL_Pos) /*!< 0x00000D80 */ +//#define DMA_CTL_DMASEL_DSPPROG (0x1CU << DMA_CTL_DMASEL_Pos) /*!< 0x00000E00 */ +//#define DMA_CTL_DMASEL_DSPHBF (0x1DU << DMA_CTL_DMASEL_Pos) /*!< 0x00000E80 */ +#define DMA_CTL_DMASEL_SPI2TX (0x1EU << DMA_CTL_DMASEL_Pos) /*!< 0x00000F00 */ +#define DMA_CTL_DMASEL_SPI2RX (0x1FU << DMA_CTL_DMASEL_Pos) /*!< 0x00000F80 */ +#define DMA_CTL_TMODE_Pos (12U) +#define DMA_CTL_TMODE_Msk (0x1U << DMA_CTL_TMODE_Pos) /*!< 0x00001000 */ +#define DMA_CTL_TMODE DMA_CTL_TMODE_Msk /*!< Transfer mode selection register */ +#define DMA_CTL_CONT_Pos (13U) +#define DMA_CTL_CONT_Msk (0x1U << DMA_CTL_CONT_Pos) /*!< 0x00002000 */ +#define DMA_CTL_CONT DMA_CTL_CONT_Msk /*!< Continuous mode, DMA transfer will not stop until STOP bit is set to 1 */ +#define DMA_CTL_AESEN_Pos (14U) +#define DMA_CTL_AESEN_Msk (0x1U << DMA_CTL_AESEN_Pos) /*!< 0x00004000 */ +#define DMA_CTL_AESEN DMA_CTL_AESEN_Msk /*!< Enable AES encrypt/decrypt function of DMA channel */ +#define DMA_CTL_STOP_Pos (15U) +#define DMA_CTL_STOP_Msk (0x1U << DMA_CTL_STOP_Pos) /*!< 0x00008000 */ +#define DMA_CTL_STOP DMA_CTL_STOP_Msk /*!< Force stop DMA transfer */ +#define DMA_CTL_PLEN_Pos (16U) +#define DMA_CTL_PLEN_Msk (0xFFU << DMA_CTL_PLEN_Pos) /*!< 0x00FF0000 */ +#define DMA_CTL_PLEN DMA_CTL_PLEN_Msk /*!< Package length register, actual transfer package length is (PLEN + 1) */ +#define DMA_CTL_FLEN_Pos (24U) +#define DMA_CTL_FLEN_Msk (0xFFU << DMA_CTL_FLEN_Pos) /*!< 0xFF000000 */ +#define DMA_CTL_FLEN DMA_CTL_FLEN_Msk /*!< Frame length register, actual transfer frame length is (FLEN + 1) */ + +/************** Bits definition for DMA_CxSRC register ******************/ +#define DMA_CxSRC_SRC_Pos (0U) +#define DMA_CxSRC_SRC_Msk (0xFFFFFFFFU << DMA_CxSRC_SRC_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CxSRC_SRC DMA_CxSRC_SRC_Msk /*!< DMA source address register */ + +/************** Bits definition for DMA_CxDST register ******************/ +#define DMA_CxDST_DST_Pos (0U) +#define DMA_CxDST_DST_Msk (0xFFFFFFFFU << DMA_CxDST_DST_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CxDST_DST DMA_CxDST_DST_Msk /*!< DMA destination address register */ + +/************** Bits definition for DMA_CxLEN register ******************/ +#define DMA_CxLEN_CPLEN_Pos (0U) +#define DMA_CxLEN_CPLEN_Msk (0xFFU << DMA_CxLEN_CPLEN_Pos) /*!< 0x000000FF */ +#define DMA_CxLEN_CPLEN DMA_CxLEN_CPLEN_Msk /*!< Current package transferred length */ +#define DMA_CxLEN_CFLEN_Pos (8U) +#define DMA_CxLEN_CFLEN_Msk (0xFFU << DMA_CxLEN_CFLEN_Pos) /*!< 0x0000FF00 */ +#define DMA_CxLEN_CFLEN DMA_CxLEN_CFLEN_Msk /*!< Current frame transferred length */ + +/************** Bits definition for DMA_AESCTL register ******************/ +#define DMA_AESCTL_ENC_Pos (0U) +#define DMA_AESCTL_ENC_Msk (0x1U << DMA_AESCTL_ENC_Pos) /*!< 0x00000001 */ +#define DMA_AESCTL_ENC DMA_AESCTL_ENC_Msk /*!< AES encode/decode selection register */ +#define DMA_AESCTL_MODE_Pos (2U) +#define DMA_AESCTL_MODE_Msk (0x3U << DMA_AESCTL_MODE_Pos) /*!< 0x0000000C */ +#define DMA_AESCTL_MODE DMA_AESCTL_MODE_Msk /*!< AES mode selection register */ +#define DMA_AESCTL_MODE_AES128 (0x0U << DMA_AESCTL_MODE_Pos) /*!< 0x00000000 */ +#define DMA_AESCTL_MODE_AES192 (0x1U << DMA_AESCTL_MODE_Pos) /*!< 0x00000004 */ +#define DMA_AESCTL_MODE_AES256 (0x2U << DMA_AESCTL_MODE_Pos) /*!< 0x00000008 */ + +/************** Bits definition for DMA_AESKEY0 register ******************/ +#define DMA_AESKEY0_Pos (0U) +#define DMA_AESKEY0_Msk (0xFFFFFFFFU << DMA_AESKEY0_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY0_KEY0 DMA_AESKEY0_Msk /*!< AES KEY register 0 */ + +/************** Bits definition for DMA_AESKEY1 register ******************/ +#define DMA_AESKEY1_Pos (0U) +#define DMA_AESKEY1_Msk (0xFFFFFFFFU << DMA_AESKEY1_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY1_KEY1 DMA_AESKEY1_Msk /*!< AES KEY register 1 */ + +/************** Bits definition for DMA_AESKEY2 register ******************/ +#define DMA_AESKEY2_Pos (0U) +#define DMA_AESKEY2_Msk (0xFFFFFFFFU << DMA_AESKEY2_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY2_KEY2 DMA_AESKEY2_Msk /*!< AES KEY register 2 */ + +/************** Bits definition for DMA_AESKEY3 register ******************/ +#define DMA_AESKEY3_Pos (0U) +#define DMA_AESKEY3_Msk (0xFFFFFFFFU << DMA_AESKEY3_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY3_KEY3 DMA_AESKEY3_Msk /*!< AES KEY register 3 */ + +/************** Bits definition for DMA_AESKEY4 register ******************/ +#define DMA_AESKEY4_Pos (0U) +#define DMA_AESKEY4_Msk (0xFFFFFFFFU << DMA_AESKEY4_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY4_KEY4 DMA_AESKEY4_Msk /*!< AES KEY register 4 */ + +/************** Bits definition for DMA_AESKEY5 register ******************/ +#define DMA_AESKEY5_Pos (0U) +#define DMA_AESKEY5_Msk (0xFFFFFFFFU << DMA_AESKEY5_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY5_KEY5 DMA_AESKEY5_Msk /*!< AES KEY register 5 */ + +/************** Bits definition for DMA_AESKEY6 register ******************/ +#define DMA_AESKEY6_Pos (0U) +#define DMA_AESKEY6_Msk (0xFFFFFFFFU << DMA_AESKEY6_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY6_KEY6 DMA_AESKEY6_Msk /*!< AES KEY register 6 */ + +/************** Bits definition for DMA_AESKEY7 register ******************/ +#define DMA_AESKEY7_Pos (0U) +#define DMA_AESKEY7_Msk (0xFFFFFFFFU << DMA_AESKEY7_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY7_KEY7 DMA_AESKEY7_Msk /*!< AES KEY register 7 */ + +/******************************************************************************/ +/* */ +/* UART controller (UART) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for UARTx_DATA register ******************/ +#define UART_DATA_Pos (0U) +#define UART_DATA_Msk (0xFFU << UART_DATA_Pos) /*!< 0x000000FF */ +#define UART_DATA UART_DATA_Msk /*!< Receive data and Transmit data */ + +/************** Bits definition for UARTx_STATE register ******************/ +//#define UART_STATE_TXFULL_Pos (0U) +//#define UART_STATE_TXFULL_Msk (0x1U << UART_STATE_TXFULL_Pos) /*!< 0x00000001 */ +//#define UART_STATE_TXFULL UART_STATE_TXFULL_Msk /*!< Transmit buffer full register */ +#define UART_STATE_RXFULL_Pos (1U) +#define UART_STATE_RXFULL_Msk (0x1U << UART_STATE_RXFULL_Pos) /*!< 0x00000002 */ +#define UART_STATE_RXFULL UART_STATE_RXFULL_Msk /*!< Receive buffer full register */ +#define UART_STATE_TXOV_Pos (2U) +#define UART_STATE_TXOV_Msk (0x1U << UART_STATE_TXOV_Pos) /*!< 0x00000004 */ +#define UART_STATE_TXOV UART_STATE_TXOV_Msk /*!< Transmit buffer overrun flag */ +#define UART_STATE_RXOV_Pos (3U) +#define UART_STATE_RXOV_Msk (0x1U << UART_STATE_RXOV_Pos) /*!< 0x00000008 */ +#define UART_STATE_RXOV UART_STATE_RXOV_Msk /*!< Receive buffer overrun flag */ +#define UART_STATE_RXPE_Pos (4U) +#define UART_STATE_RXPE_Msk (0x1U << UART_STATE_RXPE_Pos) /*!< 0x00000010 */ +#define UART_STATE_RXPE UART_STATE_RXPE_Msk /*!< Receive parity error flag */ +#define UART_STATE_TXDONE_Pos (5U) +#define UART_STATE_TXDONE_Msk (0x1U << UART_STATE_TXDONE_Pos) /*!< 0x00000020 */ +#define UART_STATE_TXDONE UART_STATE_TXDONE_Msk /*!< Transmit done flag */ +#define UART_STATE_RXPSTS_Pos (6U) +#define UART_STATE_RXPSTS_Msk (0x1U << UART_STATE_RXPSTS_Pos) /*!< 0x00000040 */ +#define UART_STATE_RXPSTS UART_STATE_RXPSTS_Msk /*!< Receive parity data flag */ + +/************** Bits definition for UARTx_CTRL register ******************/ +#define UART_CTRL_TXEN_Pos (0U) +#define UART_CTRL_TXEN_Msk (0x1U << UART_CTRL_TXEN_Pos) /*!< 0x00000001 */ +#define UART_CTRL_TXEN UART_CTRL_TXEN_Msk /*!< Transmit engine enable register */ +#define UART_CTRL_RXEN_Pos (1U) +#define UART_CTRL_RXEN_Msk (0x1U << UART_CTRL_RXEN_Pos) /*!< 0x00000002 */ +#define UART_CTRL_RXEN UART_CTRL_RXEN_Msk /*!< Receive engine enable register */ +//#define UART_CTRL_TXIE_Pos (2U) +//#define UART_CTRL_TXIE_Msk (0x1U << UART_CTRL_TXIE_Pos) /*!< 0x00000004 */ +//#define UART_CTRL_TXIE UART_CTRL_TXIE_Msk /*!< Transmit interrupt enable register */ +#define UART_CTRL_RXIE_Pos (3U) +#define UART_CTRL_RXIE_Msk (0x1U << UART_CTRL_RXIE_Pos) /*!< 0x00000008 */ +#define UART_CTRL_RXIE UART_CTRL_RXIE_Msk /*!< Receive interrupt enable register */ +#define UART_CTRL_TXOVIE_Pos (4U) +#define UART_CTRL_TXOVIE_Msk (0x1U << UART_CTRL_TXOVIE_Pos) /*!< 0x00000010 */ +#define UART_CTRL_TXOVIE UART_CTRL_TXOVIE_Msk /*!< Transmit overrun interrupt enable register */ +#define UART_CTRL_RXOVIE_Pos (5U) +#define UART_CTRL_RXOVIE_Msk (0x1U << UART_CTRL_RXOVIE_Pos) /*!< 0x00000020 */ +#define UART_CTRL_RXOVIE UART_CTRL_RXOVIE_Msk /*!< Receive overrun interrupt enable register */ +//#define UART_CTRL_TEST_Pos (6U) +//#define UART_CTRL_TEST_Msk (0x1U << UART_CTRL_TEST_Pos) /*!< 0x00000040 */ +//#define UART_CTRL_TEST UART_CTRL_TEST_Msk /*!< High speed test mode for TX only */ +#define UART_CTRL_RXPEIE_Pos (7U) +#define UART_CTRL_RXPEIE_Msk (0x1U << UART_CTRL_RXPEIE_Pos) /*!< 0x00000080 */ +#define UART_CTRL_RXPEIE UART_CTRL_RXPEIE_Msk /*!< Receive parity error interrupt enable register */ +#define UART_CTRL_TXDONEIE_Pos (8U) +#define UART_CTRL_TXDONEIE_Msk (0x1U << UART_CTRL_TXDONEIE_Pos) /*!< 0x00000100 */ +#define UART_CTRL_TXDONEIE UART_CTRL_TXDONEIE_Msk /*!< Transmit done interrupt enable register */ + +/************** Bits definition for UARTx_INTSTS register ******************/ +//#define UART_INTSTS_TXIF_Pos (0U) +//#define UART_INTSTS_TXIF_Msk (0x1U << UART_INTSTS_TXIF_Pos) /*!< 0x00000001 */ +//#define UART_INTSTS_TXIF UART_INTSTS_TXIF_Msk /*!< Transmit interrupt flag */ +#define UART_INTSTS_RXIF_Pos (1U) +#define UART_INTSTS_RXIF_Msk (0x1U << UART_INTSTS_RXIF_Pos) /*!< 0x00000002 */ +#define UART_INTSTS_RXIF UART_INTSTS_RXIF_Msk /*!< Receive interrupt flag */ +#define UART_INTSTS_TXOVIF_Pos (2U) +#define UART_INTSTS_TXOVIF_Msk (0x1U << UART_INTSTS_TXOVIF_Pos) /*!< 0x00000004 */ +#define UART_INTSTS_TXOVIF UART_INTSTS_TXOVIF_Msk /*!< Transmit buffer overrun flag */ +#define UART_INTSTS_RXOVIF_Pos (3U) +#define UART_INTSTS_RXOVIF_Msk (0x1U << UART_INTSTS_RXOVIF_Pos) /*!< 0x00000008 */ +#define UART_INTSTS_RXOVIF UART_INTSTS_RXOVIF_Msk /*!< Receive buffer overrun flag */ +#define UART_INTSTS_RXPEIF_Pos (4U) +#define UART_INTSTS_RXPEIF_Msk (0x1U << UART_INTSTS_RXPEIF_Pos) /*!< 0x00000010 */ +#define UART_INTSTS_RXPEIF UART_INTSTS_RXPEIF_Msk /*!< Receive parity error flag */ +#define UART_INTSTS_TXDONEIF_Pos (5U) +#define UART_INTSTS_TXDONEIF_Msk (0x1U << UART_INTSTS_TXDONEIF_Pos) /*!< 0x00000020 */ +#define UART_INTSTS_TXDONEIF UART_INTSTS_TXDONEIF_Msk /*!< Transmit done flag */ + +/************** Bits definition for UARTx_BAUDDIV register ******************/ +#define UART_BAUDDIV_Pos (0U) +#define UART_BAUDDIV_Msk (0xFFFFFU << UART_BAUDDIV_Pos) /*!< 0x000FFFFF */ +#define UART_BAUDDIV UART_BAUDDIV_Msk /*!< Baud rate divider register */ + +/************** Bits definition for UARTx_CTRL2 register ******************/ +#define UART_CTRL2_MSB_Pos (0U) +#define UART_CTRL2_MSB_Msk (0x1U << UART_CTRL2_MSB_Pos) /*!< 0x00000001 */ +#define UART_CTRL2_MSB UART_CTRL2_MSB_Msk /*!< LSB/MSB transmit order control register */ +#define UART_CTRL2_MODE_Pos (1U) +#define UART_CTRL2_MODE_Msk (0x1U << UART_CTRL2_MODE_Pos) /*!< 0x00000002 */ +#define UART_CTRL2_MODE UART_CTRL2_MODE_Msk /*!< UART mode control register */ +#define UART_CTRL2_PMODE_Pos (2U) +#define UART_CTRL2_PMODE_Msk (0x3U << UART_CTRL2_PMODE_Pos) /*!< 0x0000000C */ +#define UART_CTRL2_PMODE UART_CTRL2_PMODE_Msk /*!< Parity mode control register */ +#define UART_CTRL2_PMODE_EVEN (0x0U << UART_CTRL2_PMODE_Pos) /*!< 0x00000000 */ +#define UART_CTRL2_PMODE_ODD (0x1U << UART_CTRL2_PMODE_Pos) /*!< 0x00000004 */ +#define UART_CTRL2_PMODE_0 (0x2U << UART_CTRL2_PMODE_Pos) /*!< 0x00000008 */ +#define UART_CTRL2_PMODE_1 (0x3U << UART_CTRL2_PMODE_Pos) /*!< 0x0000000C */ + + +/******************************************************************************/ +/* */ +/* U32K controller (U32K) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for U32Kx_CTRL0 register ******************/ +#define U32K_CTRL0_EN_Pos (0U) +#define U32K_CTRL0_EN_Msk (0x1U << U32K_CTRL0_EN_Pos) /*!< 0x00000001 */ +#define U32K_CTRL0_EN U32K_CTRL0_EN_Msk /*!< UART 32K controller enable register */ +#define U32K_CTRL0_ACOFF_Pos (1U) +#define U32K_CTRL0_ACOFF_Msk (0x1U << U32K_CTRL0_ACOFF_Pos) /*!< 0x00000002 */ +#define U32K_CTRL0_ACOFF U32K_CTRL0_ACOFF_Msk /*!< Auto-calibration off control register */ +#define U32K_CTRL0_MSB_Pos (2U) +#define U32K_CTRL0_MSB_Msk (0x1U << U32K_CTRL0_MSB_Pos) /*!< 0x00000004 */ +#define U32K_CTRL0_MSB U32K_CTRL0_MSB_Msk /*!< UART receive order control register */ +#define U32K_CTRL0_MODE_Pos (3U) +#define U32K_CTRL0_MODE_Msk (0x1U << U32K_CTRL0_MODE_Pos) /*!< 0x00000008 */ +#define U32K_CTRL0_MODE U32K_CTRL0_MODE_Msk /*!< UART mode control register */ +#define U32K_CTRL0_PMODE_Pos (4U) +#define U32K_CTRL0_PMODE_Msk (0x3U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000030 */ +#define U32K_CTRL0_PMODE U32K_CTRL0_PMODE_Msk /*!< Parity mode control register */ +#define U32K_CTRL0_PMODE_EVEN (0x0U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000000 */ +#define U32K_CTRL0_PMODE_ODD (0x1U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000010 */ +#define U32K_CTRL0_PMODE_0 (0x2U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000020 */ +#define U32K_CTRL0_PMODE_1 (0x3U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000030 */ +#define U32K_CTRL0_DEBSEL_Pos (6U) +#define U32K_CTRL0_DEBSEL_Msk (0x3U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x000000C0 */ +#define U32K_CTRL0_DEBSEL U32K_CTRL0_DEBSEL_Msk /*!< De-bounce control register */ +#define U32K_CTRL0_DEBSEL_0 (0x0U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000000 */ +#define U32K_CTRL0_DEBSEL_1 (0x1U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000040 */ +#define U32K_CTRL0_DEBSEL_2 (0x2U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000080 */ +#define U32K_CTRL0_DEBSEL_3 (0x3U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x000000C0 */ +#define U32K_CTRL0_WKUMODE_Pos (8U) +#define U32K_CTRL0_WKUMODE_Msk (0x1U << U32K_CTRL0_WKUMODE_Pos) /*!< 0x00000100 */ +#define U32K_CTRL0_WKUMODE U32K_CTRL0_WKUMODE_Msk /*!< Wake-up mode control register */ + +/************** Bits definition for U32Kx_CTRL1 register ******************/ +#define U32K_CTRL1_RXIE_Pos (0U) +#define U32K_CTRL1_RXIE_Msk (0x1U << U32K_CTRL1_RXIE_Pos) /*!< 0x00000001 */ +#define U32K_CTRL1_RXIE U32K_CTRL1_RXIE_Msk /*!< Receive interrupt/wake-up enable register */ +#define U32K_CTRL1_RXPEIE_Pos (1U) +#define U32K_CTRL1_RXPEIE_Msk (0x1U << U32K_CTRL1_RXPEIE_Pos) /*!< 0x00000002 */ +#define U32K_CTRL1_RXPEIE U32K_CTRL1_RXPEIE_Msk /*!< Receive parity error interrupt/wake-up enable register */ +#define U32K_CTRL1_RXOVIE_Pos (2U) +#define U32K_CTRL1_RXOVIE_Msk (0x1U << U32K_CTRL1_RXOVIE_Pos) /*!< 0x00000004 */ +#define U32K_CTRL1_RXOVIE U32K_CTRL1_RXOVIE_Msk /*!< Receive overrun interrupt/wake-up enable register */ +#define U32K_CTRL1_RXSEL_Pos (4U) +#define U32K_CTRL1_RXSEL_Msk (0x3U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000030 */ +#define U32K_CTRL1_RXSEL U32K_CTRL1_RXSEL_Msk /*!< Receive data select register */ +#define U32K_CTRL1_RXSEL_RX0 (0x0U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000000 */ +#define U32K_CTRL1_RXSEL_RX1 (0x1U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000010 */ +#define U32K_CTRL1_RXSEL_RX2 (0x2U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000020 */ +#define U32K_CTRL1_RXSEL_RX3 (0x3U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000030 */ + +/************** Bits definition for U32Kx_PHASE register ******************/ +#define U32K_PHASE_Pos (0U) +#define U32K_PHASE_Msk (0xFFFFU << U32K_PHASE_Pos) /*!< 0x0000FFFF */ +#define U32K_PHASE U32K_PHASE_Msk /*!< Baud rate divider register */ + +/************** Bits definition for U32Kx_DATA register ******************/ +#define U32K_DATA_Pos (0U) +#define U32K_DATA_Msk (0xFFU << U32K_DATA_Pos) /*!< 0x000000FF */ +#define U32K_DATA U32K_DATA_Msk /*!< Receive data */ + +/************** Bits definition for U32Kx_STS register ******************/ +#define U32K_STS_RCMsk (0x07UL) +#define U32K_STS_RXIF_Pos (0U) +#define U32K_STS_RXIF_Msk (0x1U << U32K_STS_RXIF_Pos) /*!< 0x00000001 */ +#define U32K_STS_RXIF U32K_STS_RXIF_Msk /*!< Receive interrupt flag */ +#define U32K_STS_RXPE_Pos (1U) +#define U32K_STS_RXPE_Msk (0x1U << U32K_STS_RXPE_Pos) /*!< 0x00000002 */ +#define U32K_STS_RXPE U32K_STS_RXPE_Msk /*!< Receive parity error flag */ +#define U32K_STS_RXOV_Pos (2U) +#define U32K_STS_RXOV_Msk (0x1U << U32K_STS_RXOV_Pos) /*!< 0x00000004 */ +#define U32K_STS_RXOV U32K_STS_RXOV_Msk /*!< Receive buffer overrun flag */ + +/******************************************************************************/ +/* */ +/* ISO7816 controller (ISO7816) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for ISO7816x_BAUDDIVL register **************/ +#define ISO7816_BAUDDIVL_Pos (0U) +#define ISO7816_BAUDDIVL_Msk (0xFFU << ISO7816_BAUDDIVL_Pos) /*!< 0x000000FF */ +#define ISO7816_BAUDDIVL ISO7816_BAUDDIVL_Msk /*!< Low byte of baud-rate divider */ + +/************** Bits definition for ISO7816x_BAUDDIVH register **************/ +#define ISO7816_BAUDDIVH_Pos (0U) +#define ISO7816_BAUDDIVH_Msk (0xFFU << ISO7816_BAUDDIVH_Pos) /*!< 0x000000FF */ +#define ISO7816_BAUDDIVH ISO7816_BAUDDIVH_Msk /*!< High byte of baud-rate divider */ + +/************** Bits definition for ISO7816x_DATA register ******************/ +#define ISO7816_DATA_Pos (0U) +#define ISO7816_DATA_Msk (0xFFU << ISO7816_DATA_Pos) /*!< 0x000000FF */ +#define ISO7816_DATA ISO7816_DATA_Msk /*!< Transmit or Receive data */ + +/************** Bits definition for ISO7816x_INFO register ******************/ +#define ISO7816_INFO_RCACK_Pos (0U) +#define ISO7816_INFO_RCACK_Msk (0x1U << ISO7816_INFO_RCACK_Pos) /*!< 0x00000001 */ +#define ISO7816_INFO_RCACK ISO7816_INFO_RCACK_Msk /*!< The received ACK at the end of transmit */ +#define ISO7816_INFO_CHKSUM_Pos (1U) +#define ISO7816_INFO_CHKSUM_Msk (0x1U << ISO7816_INFO_CHKSUM_Pos) /*!< 0x00000002 */ +#define ISO7816_INFO_CHKSUM ISO7816_INFO_CHKSUM_Msk /*!< The transmitted or received data��s check sum bit */ +#define ISO7816_INFO_RCERR_Pos (2U) +#define ISO7816_INFO_RCERR_Msk (0x1U << ISO7816_INFO_RCERR_Pos) /*!< 0x00000004 */ +#define ISO7816_INFO_RCERR ISO7816_INFO_RCERR_Msk /*!< When received data have check sum error */ +#define ISO7816_INFO_SDERR_Pos (3U) +#define ISO7816_INFO_SDERR_Msk (0x1U << ISO7816_INFO_SDERR_Pos) /*!< 0x00000008 */ +#define ISO7816_INFO_SDERR ISO7816_INFO_SDERR_Msk /*!< When the received ACK is 0 during transmit mode */ +#define ISO7816_INFO_LSB_Pos (4U) +#define ISO7816_INFO_LSB_Msk (0x1U << ISO7816_INFO_LSB_Pos) /*!< 0x00000010 */ +#define ISO7816_INFO_LSB ISO7816_INFO_LSB_Msk /*!< MSB/LSB transmit order control register */ +#define ISO7816_INFO_RCIF_Pos (5U) +#define ISO7816_INFO_RCIF_Msk (0x1U << ISO7816_INFO_RCIF_Pos) /*!< 0x00000020 */ +#define ISO7816_INFO_RCIF ISO7816_INFO_RCIF_Msk /*!< Receive interrupt flag */ +#define ISO7816_INFO_SDIF_Pos (6U) +#define ISO7816_INFO_SDIF_Msk (0x1U << ISO7816_INFO_SDIF_Pos) /*!< 0x00000040 */ +#define ISO7816_INFO_SDIF ISO7816_INFO_SDIF_Msk /*!< Transmit interrupt flag */ +#define ISO7816_INFO_OVIF_Pos (7U) +#define ISO7816_INFO_OVIF_Msk (0x1U << ISO7816_INFO_OVIF_Pos) /*!< 0x00000080 */ +#define ISO7816_INFO_OVIF ISO7816_INFO_OVIF_Msk /*!< Receive overflow flag */ + +/************** Bits definition for ISO7816x_CFG register ******************/ +#define ISO7816_CFG_EN_Pos (0U) +#define ISO7816_CFG_EN_Msk (0x1U << ISO7816_CFG_EN_Pos) /*!< 0x00000001 */ +#define ISO7816_CFG_EN ISO7816_CFG_EN_Msk /*!< ISO7816 enable register */ +#define ISO7816_CFG_CHKP_Pos (1U) +#define ISO7816_CFG_CHKP_Msk (0x1U << ISO7816_CFG_CHKP_Pos) /*!< 0x00000002 */ +#define ISO7816_CFG_CHKP ISO7816_CFG_CHKP_Msk /*!< Transmit interrupt enable register */ +//#define ISO7816_CFG_AUTORC_Pos (2U) +//#define ISO7816_CFG_AUTORC_Msk (0x1U << ISO7816_CFG_AUTORC_Pos) /*!< 0x00000004 */ +//#define ISO7816_CFG_AUTORC ISO7816_CFG_AUTORC_Msk /*!< Receive interrupt enable register */ +//#define ISO7816_CFG_AUTOSD_Pos (3U) +//#define ISO7816_CFG_AUTOSD_Msk (0x1U << ISO7816_CFG_AUTOSD_Pos) /*!< 0x00000008 */ +//#define ISO7816_CFG_AUTOSD ISO7816_CFG_AUTOSD_Msk /*!< ACK low period when receive an error data */ +#define ISO7816_CFG_ACKLEN_Pos (4U) +#define ISO7816_CFG_ACKLEN_Msk (0x1U << ISO7816_CFG_ACKLEN_Pos) /*!< 0x00000010 */ +#define ISO7816_CFG_ACKLEN ISO7816_CFG_ACKLEN_Msk /*!< Automatic re-transmit when receive ACK is 0 */ +#define ISO7816_CFG_RCIE_Pos (5U) +#define ISO7816_CFG_RCIE_Msk (0x1U << ISO7816_CFG_RCIE_Pos) /*!< 0x00000020 */ +#define ISO7816_CFG_RCIE ISO7816_CFG_RCIE_Msk /*!< Automatic response ACK as 0 when receive an error data to let transmitter re-send the data */ +#define ISO7816_CFG_SDIE_Pos (6U) +#define ISO7816_CFG_SDIE_Msk (0x1U << ISO7816_CFG_SDIE_Pos) /*!< 0x00000040 */ +#define ISO7816_CFG_SDIE ISO7816_CFG_SDIE_Msk /*!< Parity mode control register */ +#define ISO7816_CFG_OVIE_Pos (7U) +#define ISO7816_CFG_OVIE_Msk (0x1U << ISO7816_CFG_OVIE_Pos) /*!< 0x00000080 */ +#define ISO7816_CFG_OVIE ISO7816_CFG_OVIE_Msk /*!< Receive overrun interrupt enable register */ + +/************** Bits definition for ISO7816x_CLK register ******************/ +#define ISO7816_CLK_CLKDIV_Pos (0U) +#define ISO7816_CLK_CLKDIV_Msk (0x7FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007F */ +#define ISO7816_CLK_CLKDIV ISO7816_CLK_CLKDIV_Msk /*!< The ISO7816 clock divider ratio */ +#define ISO7816_CLK_CLKDIV_1 (0x0U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000000 */ +#define ISO7816_CLK_CLKDIV_2 (0x1U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000001 */ +#define ISO7816_CLK_CLKDIV_3 (0x2U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000002 */ +#define ISO7816_CLK_CLKDIV_4 (0x3U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000003 */ +#define ISO7816_CLK_CLKDIV_5 (0x4U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000004 */ +#define ISO7816_CLK_CLKDIV_6 (0x5U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000005 */ +#define ISO7816_CLK_CLKDIV_7 (0x6U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000006 */ +#define ISO7816_CLK_CLKDIV_8 (0x7U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000007 */ +#define ISO7816_CLK_CLKDIV_9 (0x8U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000008 */ +#define ISO7816_CLK_CLKDIV_10 (0x9U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000009 */ +#define ISO7816_CLK_CLKDIV_11 (0xAU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000A */ +#define ISO7816_CLK_CLKDIV_12 (0xBU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000B */ +#define ISO7816_CLK_CLKDIV_13 (0xCU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000C */ +#define ISO7816_CLK_CLKDIV_14 (0xDU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000D */ +#define ISO7816_CLK_CLKDIV_15 (0xEU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000E */ +#define ISO7816_CLK_CLKDIV_16 (0xFU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000F */ +#define ISO7816_CLK_CLKDIV_17 (0x10U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000010 */ +#define ISO7816_CLK_CLKDIV_18 (0x11U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000011 */ +#define ISO7816_CLK_CLKDIV_19 (0x12U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000012 */ +#define ISO7816_CLK_CLKDIV_20 (0x13U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000013 */ +#define ISO7816_CLK_CLKDIV_21 (0x14U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000014 */ +#define ISO7816_CLK_CLKDIV_22 (0x15U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000015 */ +#define ISO7816_CLK_CLKDIV_23 (0x16U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000016 */ +#define ISO7816_CLK_CLKDIV_24 (0x17U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000017 */ +#define ISO7816_CLK_CLKDIV_25 (0x18U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000018 */ +#define ISO7816_CLK_CLKDIV_26 (0x19U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000019 */ +#define ISO7816_CLK_CLKDIV_27 (0x1AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001A */ +#define ISO7816_CLK_CLKDIV_28 (0x1BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001B */ +#define ISO7816_CLK_CLKDIV_29 (0x1CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001C */ +#define ISO7816_CLK_CLKDIV_30 (0x1DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001D */ +#define ISO7816_CLK_CLKDIV_31 (0x1EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001E */ +#define ISO7816_CLK_CLKDIV_32 (0x1FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001F */ +#define ISO7816_CLK_CLKDIV_33 (0x20U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000020 */ +#define ISO7816_CLK_CLKDIV_34 (0x21U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000021 */ +#define ISO7816_CLK_CLKDIV_35 (0x22U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000022 */ +#define ISO7816_CLK_CLKDIV_36 (0x23U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000023 */ +#define ISO7816_CLK_CLKDIV_37 (0x24U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000024 */ +#define ISO7816_CLK_CLKDIV_38 (0x25U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000025 */ +#define ISO7816_CLK_CLKDIV_39 (0x26U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000026 */ +#define ISO7816_CLK_CLKDIV_40 (0x27U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000027 */ +#define ISO7816_CLK_CLKDIV_41 (0x28U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000028 */ +#define ISO7816_CLK_CLKDIV_42 (0x29U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000029 */ +#define ISO7816_CLK_CLKDIV_43 (0x2AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002A */ +#define ISO7816_CLK_CLKDIV_44 (0x2BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002B */ +#define ISO7816_CLK_CLKDIV_45 (0x2CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002C */ +#define ISO7816_CLK_CLKDIV_46 (0x2DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002D */ +#define ISO7816_CLK_CLKDIV_47 (0x2EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002E */ +#define ISO7816_CLK_CLKDIV_48 (0x2FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002F */ +#define ISO7816_CLK_CLKDIV_49 (0x30U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000030 */ +#define ISO7816_CLK_CLKDIV_50 (0x31U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000031 */ +#define ISO7816_CLK_CLKDIV_51 (0x32U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000032 */ +#define ISO7816_CLK_CLKDIV_52 (0x33U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000033 */ +#define ISO7816_CLK_CLKDIV_53 (0x34U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000034 */ +#define ISO7816_CLK_CLKDIV_54 (0x35U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000035 */ +#define ISO7816_CLK_CLKDIV_55 (0x36U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000036 */ +#define ISO7816_CLK_CLKDIV_56 (0x37U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000037 */ +#define ISO7816_CLK_CLKDIV_57 (0x38U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000038 */ +#define ISO7816_CLK_CLKDIV_58 (0x39U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000039 */ +#define ISO7816_CLK_CLKDIV_59 (0x3AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003A */ +#define ISO7816_CLK_CLKDIV_60 (0x3BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003B */ +#define ISO7816_CLK_CLKDIV_61 (0x3CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003C */ +#define ISO7816_CLK_CLKDIV_62 (0x3DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003D */ +#define ISO7816_CLK_CLKDIV_63 (0x3EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003E */ +#define ISO7816_CLK_CLKDIV_64 (0x3FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003F */ +#define ISO7816_CLK_CLKDIV_65 (0x40U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000040 */ +#define ISO7816_CLK_CLKDIV_66 (0x41U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000041 */ +#define ISO7816_CLK_CLKDIV_67 (0x42U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000042 */ +#define ISO7816_CLK_CLKDIV_68 (0x43U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000043 */ +#define ISO7816_CLK_CLKDIV_69 (0x44U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000044 */ +#define ISO7816_CLK_CLKDIV_70 (0x45U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000045 */ +#define ISO7816_CLK_CLKDIV_71 (0x46U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000046 */ +#define ISO7816_CLK_CLKDIV_72 (0x47U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000047 */ +#define ISO7816_CLK_CLKDIV_73 (0x48U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000048 */ +#define ISO7816_CLK_CLKDIV_74 (0x49U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000049 */ +#define ISO7816_CLK_CLKDIV_75 (0x4AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004A */ +#define ISO7816_CLK_CLKDIV_76 (0x4BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004B */ +#define ISO7816_CLK_CLKDIV_77 (0x4CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004C */ +#define ISO7816_CLK_CLKDIV_78 (0x4DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004D */ +#define ISO7816_CLK_CLKDIV_79 (0x4EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004E */ +#define ISO7816_CLK_CLKDIV_80 (0x4FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004F */ +#define ISO7816_CLK_CLKDIV_81 (0x50U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000050 */ +#define ISO7816_CLK_CLKDIV_82 (0x51U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000051 */ +#define ISO7816_CLK_CLKDIV_83 (0x52U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000052 */ +#define ISO7816_CLK_CLKDIV_84 (0x53U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000053 */ +#define ISO7816_CLK_CLKDIV_85 (0x54U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000054 */ +#define ISO7816_CLK_CLKDIV_86 (0x55U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000055 */ +#define ISO7816_CLK_CLKDIV_87 (0x56U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000056 */ +#define ISO7816_CLK_CLKDIV_88 (0x57U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000057 */ +#define ISO7816_CLK_CLKDIV_89 (0x58U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000058 */ +#define ISO7816_CLK_CLKDIV_90 (0x59U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000059 */ +#define ISO7816_CLK_CLKDIV_91 (0x5AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005A */ +#define ISO7816_CLK_CLKDIV_92 (0x5BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005B */ +#define ISO7816_CLK_CLKDIV_93 (0x5CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005C */ +#define ISO7816_CLK_CLKDIV_94 (0x5DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005D */ +#define ISO7816_CLK_CLKDIV_95 (0x5EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005E */ +#define ISO7816_CLK_CLKDIV_96 (0x5FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005F */ +#define ISO7816_CLK_CLKDIV_97 (0x60U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000060 */ +#define ISO7816_CLK_CLKDIV_98 (0x61U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000061 */ +#define ISO7816_CLK_CLKDIV_99 (0x62U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000062 */ +#define ISO7816_CLK_CLKDIV_100 (0x63U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000063 */ +#define ISO7816_CLK_CLKDIV_101 (0x64U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000064 */ +#define ISO7816_CLK_CLKDIV_102 (0x65U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000065 */ +#define ISO7816_CLK_CLKDIV_103 (0x66U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000066 */ +#define ISO7816_CLK_CLKDIV_104 (0x67U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000067 */ +#define ISO7816_CLK_CLKDIV_105 (0x68U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000068 */ +#define ISO7816_CLK_CLKDIV_106 (0x69U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000069 */ +#define ISO7816_CLK_CLKDIV_107 (0x6AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006A */ +#define ISO7816_CLK_CLKDIV_108 (0x6BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006B */ +#define ISO7816_CLK_CLKDIV_109 (0x6CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006C */ +#define ISO7816_CLK_CLKDIV_110 (0x6DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006D */ +#define ISO7816_CLK_CLKDIV_111 (0x6EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006E */ +#define ISO7816_CLK_CLKDIV_112 (0x6FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006F */ +#define ISO7816_CLK_CLKDIV_113 (0x70U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000070 */ +#define ISO7816_CLK_CLKDIV_114 (0x71U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000071 */ +#define ISO7816_CLK_CLKDIV_115 (0x72U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000072 */ +#define ISO7816_CLK_CLKDIV_116 (0x73U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000073 */ +#define ISO7816_CLK_CLKDIV_117 (0x74U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000074 */ +#define ISO7816_CLK_CLKDIV_118 (0x75U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000075 */ +#define ISO7816_CLK_CLKDIV_119 (0x76U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000076 */ +#define ISO7816_CLK_CLKDIV_120 (0x77U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000077 */ +#define ISO7816_CLK_CLKDIV_121 (0x78U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000078 */ +#define ISO7816_CLK_CLKDIV_122 (0x79U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000079 */ +#define ISO7816_CLK_CLKDIV_123 (0x7AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007A */ +#define ISO7816_CLK_CLKDIV_124 (0x7BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007B */ +#define ISO7816_CLK_CLKDIV_125 (0x7CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007C */ +#define ISO7816_CLK_CLKDIV_126 (0x7DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007D */ +#define ISO7816_CLK_CLKDIV_127 (0x7EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007E */ +#define ISO7816_CLK_CLKDIV_128 (0x7FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007F */ +#define ISO7816_CLK_CLKEN_Pos (7U) +#define ISO7816_CLK_CLKEN_Msk (0x1U << ISO7816_CLK_CLKEN_Pos) /*!< 0x00000080 */ +#define ISO7816_CLK_CLKEN ISO7816_CLK_CLKEN_Msk /*!< ISO7816 clock output enable */ + +/******************************************************************************/ +/* */ +/* Timer Controller (timer) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for TMRx_CTRL register ******************/ +#define TMR_CTRL_EN_Pos (0U) +#define TMR_CTRL_EN_Msk (0x1U << TMR_CTRL_EN_Pos) /*!< 0x00000001 */ +#define TMR_CTRL_EN TMR_CTRL_EN_Msk /*!< Timer x enable control register */ +#define TMR_CTRL_EXTEN_Pos (1U) +#define TMR_CTRL_EXTEN_Msk (0x1U << TMR_CTRL_EXTEN_Pos) /*!< 0x00000002 */ +#define TMR_CTRL_EXTEN TMR_CTRL_EXTEN_Msk /*!< Select ext_clk as clock enable */ +#define TMR_CTRL_EXTCLK_Pos (2U) +#define TMR_CTRL_EXTCLK_Msk (0x1U << TMR_CTRL_EXTCLK_Pos) /*!< 0x00000004 */ +#define TMR_CTRL_EXTCLK TMR_CTRL_EXTCLK_Msk /*!< Select ext_clk as clock source */ +#define TMR_CTRL_INTEN_Pos (3U) +#define TMR_CTRL_INTEN_Msk (0x1U << TMR_CTRL_INTEN_Pos) /*!< 0x00000008 */ +#define TMR_CTRL_INTEN TMR_CTRL_INTEN_Msk /*!< Timer x interrupt enable register */ + +/************** Bits definition for TMRx_VALUE register ******************/ +#define TMR_VALUE_VALUE_Pos (0U) +#define TMR_VALUE_VALUE_Msk (0xFFFFFFFFU << TMR_VALUE_VALUE_Pos) /*!< 0xFFFFFFFF */ +#define TMR_VALUE_VALUE TMR_VALUE_VALUE_Msk /*!< Timer x current value register */ + +/************** Bits definition for TMRx_RELOAD register ******************/ +#define TMR_RELOAD_RELOAD_Pos (0U) +#define TMR_RELOAD_RELOAD_Msk (0xFFFFFFFFU << TMR_RELOAD_RELOAD_Pos) /*!< 0xFFFFFFFF */ +#define TMR_RELOAD_RELOAD TMR_RELOAD_RELOAD_Msk /*!< Timer x reload value register. A write to this register sets the current value */ + +/************** Bits definition for TMRx_INT register ******************/ +#define TMR_INT_INT_Pos (0U) +#define TMR_INT_INT_Msk (0x1U << TMR_INT_INT_Pos) /*!< 0x00000001 */ +#define TMR_INT_INT TMR_INT_INT_Msk /*!< Timer x interrupt status register, write 1 to clear this bit. */ + +/******************************************************************************/ +/* */ +/* PWM controller (PWM) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for PWMx_CTL register ******************/ +#define PWM_CTL_IFG_Pos (0U) +#define PWM_CTL_IFG_Msk (0x1U << PWM_CTL_IFG_Pos) /*!< 0x00000001 */ +#define PWM_CTL_IFG PWM_CTL_IFG_Msk /*!< PWM Timer x��s interrupt status flag, write 1 to clear this flag to 0 */ +#define PWM_CTL_IE_Pos (1U) +#define PWM_CTL_IE_Msk (0x1U << PWM_CTL_IE_Pos) /*!< 0x00000002 */ +#define PWM_CTL_IE PWM_CTL_IE_Msk /*!< PWM Timer x��s interrupt enable register */ +#define PWM_CTL_CLR_Pos (2U) +#define PWM_CTL_CLR_Msk (0x1U << PWM_CTL_CLR_Pos) /*!< 0x00000004 */ +#define PWM_CTL_CLR PWM_CTL_CLR_Msk /*!< TAR clear register, when this bit is set to 1, the TAR will be clear to 0 */ +#define PWM_CTL_TESL_Pos (3U) +#define PWM_CTL_TESL_Msk (0x1U << PWM_CTL_TESL_Pos) /*!< 0x00000008 */ +#define PWM_CTL_TESL PWM_CTL_TESL_Msk /*!< Clock source selection */ +#define PWM_CTL_TESL_APBDIV128 (0x0U << PWM_CTL_TESL_Pos) /*!< 0x00000000 */ +#define PWM_CTL_TESL_APBDIV1 (0x1U << PWM_CTL_TESL_Pos) /*!< 0x00000008 */ +#define PWM_CTL_MC_Pos (4U) +#define PWM_CTL_MC_Msk (0x3U << PWM_CTL_MC_Pos) /*!< 0x00000030 */ +#define PWM_CTL_MC PWM_CTL_MC_Msk /*!< PWM Timer mode control */ +#define PWM_CTL_MC_STOP (0x0U << PWM_CTL_MC_Pos) /*!< 0x00000000 */ +#define PWM_CTL_MC_UP (0x1U << PWM_CTL_MC_Pos) /*!< 0x00000010 */ +#define PWM_CTL_MC_CONTINUE (0x2U << PWM_CTL_MC_Pos) /*!< 0x00000020 */ +#define PWM_CTL_MC_UPDOWN (0x3U << PWM_CTL_MC_Pos) /*!< 0x00000030 */ +#define PWM_CTL_ID_Pos (6U) +#define PWM_CTL_ID_Msk (0x3U << PWM_CTL_ID_Pos) /*!< 0x000000C0 */ +#define PWM_CTL_ID PWM_CTL_ID_Msk /*!< PWM timer x��s Input clock divider control */ +#define PWM_CTL_ID_DIV2 (0x0U << PWM_CTL_ID_Pos) /*!< 0x00000000 */ +#define PWM_CTL_ID_DIV4 (0x1U << PWM_CTL_ID_Pos) /*!< 0x00000040 */ +#define PWM_CTL_ID_DIV8 (0x2U << PWM_CTL_ID_Pos) /*!< 0x00000080 */ +#define PWM_CTL_ID_DIV16 (0x3U << PWM_CTL_ID_Pos) /*!< 0x000000C0 */ + +/************** Bits definition for PWMx_TAR register ******************/ +#define PWM_TAR_TAR_Pos (0U) +#define PWM_TAR_TAR_Msk (0xFFFFU << PWM_TAR_TAR_Pos) /*!< 0x0000FFFF */ +#define PWM_TAR_TAR PWM_TAR_TAR_Msk /*!< PWM Timer x��s current count register */ + +/************** Bits definition for PWMx_CCTLy register ******************/ +#define PWM_CCTL_CCIGG_Pos (0U) +#define PWM_CCTL_CCIGG_Msk (0x1U << PWM_CCTL_CCIGG_Pos) /*!< 0x00000001 */ +#define PWM_CCTL_CCIGG PWM_CCTL_CCIGG_Msk /*!< Under compare mode, this bit will be set when TAR=CCRx. */ +//#define PWM_CCTL_COV_Pos (1U) +//#define PWM_CCTL_COV_Msk (0x1U << PWM_CCTL_COV_Pos) /*!< 0x00000002 */ +//#define PWM_CCTL_COV PWM_CCTL_COV_Msk /*!< Capture overflow flag, this bit will be set when the CCIFG bit is 1 and another capture event is coming */ +#define PWM_CCTL_OUT_Pos (2U) +#define PWM_CCTL_OUT_Msk (0x1U << PWM_CCTL_OUT_Pos) /*!< 0x00000004 */ +#define PWM_CCTL_OUT PWM_CCTL_OUT_Msk /*!< This bit is used to control the output value of OUTx when OUTMOD is set to 0 */ +//#define PWM_CCTL_CCI_Pos (3U) +//#define PWM_CCTL_CCI_Msk (0x1U << PWM_CCTL_CCI_Pos) /*!< 0x00000008 */ +//#define PWM_CCTL_CCI PWM_CCTL_CCI_Msk /*!< The read only register shows the current status of INx��s input */ +#define PWM_CCTL_CCIE_Pos (4U) +#define PWM_CCTL_CCIE_Msk (0x1U << PWM_CCTL_CCIE_Pos) /*!< 0x00000010 */ +#define PWM_CCTL_CCIE PWM_CCTL_CCIE_Msk /*!< Compare interrupt enable register */ +#define PWM_CCTL_OUTMOD_Pos (5U) +#define PWM_CCTL_OUTMOD_Msk (0x7U << PWM_CCTL_OUTMOD_Pos) /*!< 0x000000E0 */ +#define PWM_CCTL_OUTMOD PWM_CCTL_OUTMOD_Msk /*!< Output mode selection */ +#define PWM_CCTL_OUTMOD_CONST (0x00UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_SET (0x01UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_TOGGLE_RESET (0x02UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_SET_RESET (0x03UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_TOGGLE (0x04UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_RESET (0x05UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_TOGGLE_SET (0x06UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_RESET_SET (0x07UL << PWM_CCTL_OUTMOD_Pos) +//#define PWM_CCTL_CAP_Pos (8U) +//#define PWM_CCTL_CAP_Msk (0x1U << PWM_CCTL_CAP_Pos) /*!< 0x00000100 */ +//#define PWM_CCTL_CAP PWM_CCTL_CAP_Msk /*!< Capture/Compare mode selection */ +#define PWM_CCTL_OUTEN_Pos (9U) +#define PWM_CCTL_OUTEN_Msk (0x1U << PWM_CCTL_OUTEN_Pos) /*!< 0x00000200 */ +#define PWM_CCTL_OUTEN PWM_CCTL_OUTEN_Msk /*!< OUTx output enable control register */ +//#define PWM_CCTL_SCCI_Pos (10U) +//#define PWM_CCTL_SCCI_Msk (0x1U << PWM_CCTL_SCCI_Pos) /*!< 0x00000400 */ +//#define PWM_CCTL_SCCI PWM_CCTL_SCCI_Msk /*!< The read only register shows the INx��s input value when the TAR is equal to CCRx */ +//#define PWM_CCTL_CM_Pos (14U) +//#define PWM_CCTL_CM_Msk (0x3U << PWM_CCTL_CM_Pos) /*!< 0x0000C000 */ +//#define PWM_CCTL_CM PWM_CCTL_CM_Msk /*!< Capture edge selection */ +//#define PWM_CCTL_CM_DISABLE (0x0U << PWM_CCTL_CM_Pos) +//#define PWM_CCTL_CM_RISING (0x1U << PWM_CCTL_CM_Pos) +//#define PWM_CCTL_CM_FALLING (0x2U << PWM_CCTL_CM_Pos) +//#define PWM_CCTL_CM_BOTH (0x3U << PWM_CCTL_CM_Pos) + +/************** Bits definition for PWMx_CCRy register ******************/ +#define PWM_CCR_CCR_Pos (0U) +#define PWM_CCR_CCR_Msk (0xFFFFU << PWM_CCR_CCR_Pos) /*!< 0x0000FFFF */ +#define PWM_CCR_CCR PWM_CCR_CCR_Msk /*!< Compare/Capture data register */ + +/************** Bits definition for PWM_O_SEL register ******************/ +#define PWM_O_SEL_O_SEL0_Pos (0U) +#define PWM_O_SEL_O_SEL0_Msk (0xFU << PWM_O_SEL_O_SEL0_Pos) /*!< 0x0000000F */ +#define PWM_O_SEL_O_SEL0 PWM_O_SEL_O_SEL0_Msk /*!< External output PWM0��s output selection register */ +#define PWM_O_SEL_O_SEL1_Pos (4U) +#define PWM_O_SEL_O_SEL1_Msk (0xFU << PWM_O_SEL_O_SEL1_Pos) /*!< 0x000000F0 */ +#define PWM_O_SEL_O_SEL1 PWM_O_SEL_O_SEL1_Msk /*!< External output PWM1��s output selection register */ +#define PWM_O_SEL_O_SEL2_Pos (8U) +#define PWM_O_SEL_O_SEL2_Msk (0xFU << PWM_O_SEL_O_SEL2_Pos) /*!< 0x000000F00 */ +#define PWM_O_SEL_O_SEL2 PWM_O_SEL_O_SEL2_Msk /*!< External output PWM2��s output selection register */ +#define PWM_O_SEL_O_SEL3_Pos (12U) +#define PWM_O_SEL_O_SEL3_Msk (0xFU << PWM_O_SEL_O_SEL3_Pos) /*!< 0x0000F000 */ +#define PWM_O_SEL_O_SEL3 PWM_O_SEL_O_SEL3_Msk /*!< External output PWM3��s output selection register */ + +///************** Bits definition for PWM_I_SEL01 register ******************/ +//#define PWM_I_SEL01_I_SEL00_Pos (0U) +//#define PWM_I_SEL01_I_SEL00_Msk (0x3U << PWM_I_SEL01_I_SEL00_Pos) /*!< 0x00000003 */ +//#define PWM_I_SEL01_I_SEL00 PWM_I_SEL01_I_SEL00_Msk /*!< PWM0��s IN0 external input control */ +//#define PWM_I_SEL01_I_SEL01_Pos (2U) +//#define PWM_I_SEL01_I_SEL01_Msk (0x3U << PWM_I_SEL01_I_SEL01_Pos) /*!< 0x000000C */ +//#define PWM_I_SEL01_I_SEL01 PWM_I_SEL01_I_SEL01_Msk /*!< PWM0��s IN1 external input control */ +//#define PWM_I_SEL01_I_SEL02_Pos (4U) +//#define PWM_I_SEL01_I_SEL02_Msk (0x3U << PWM_I_SEL01_I_SEL02_Pos) /*!< 0x00000030 */ +//#define PWM_I_SEL01_I_SEL02 PWM_I_SEL01_I_SEL02_Msk /*!< PWM0��s IN2 external input control */ +//#define PWM_I_SEL01_I_SEL10_Pos (16U) +//#define PWM_I_SEL01_I_SEL10_Msk (0x3U << PWM_I_SEL01_I_SEL10_Pos) /*!< 0x00030000 */ +//#define PWM_I_SEL01_I_SEL10 PWM_I_SEL01_I_SEL10_Msk /*!< PWM1��s IN0 external input control */ +//#define PWM_I_SEL01_I_SEL11_Pos (18U) +//#define PWM_I_SEL01_I_SEL11_Msk (0x3U << PWM_I_SEL01_I_SEL11_Pos) /*!< 0x000C0000 */ +//#define PWM_I_SEL01_I_SEL11 PWM_I_SEL01_I_SEL11_Msk /*!< PWM1��s IN1 external input control */ +//#define PWM_I_SEL01_I_SEL12_Pos (20U) +//#define PWM_I_SEL01_I_SEL12_Msk (0x3U << PWM_I_SEL01_I_SEL12_Pos) /*!< 0x00300000 */ +//#define PWM_I_SEL01_I_SEL12 PWM_I_SEL01_I_SEL12_Msk /*!< PWM1��s IN2 external input control */ +// +///************** Bits definition for PWM_I_SEL23 register ******************/ +//#define PWM_I_SEL23_I_SEL20_Pos (0U) +//#define PWM_I_SEL23_I_SEL20_Msk (0x3U << PWM_I_SEL23_I_SEL20_Pos) /*!< 0x00000003 */ +//#define PWM_I_SEL23_I_SEL20 PWM_I_SEL23_I_SEL20_Msk /*!< PWM2��s IN0 external input control */ +//#define PWM_I_SEL23_I_SEL21_Pos (2U) +//#define PWM_I_SEL23_I_SEL21_Msk (0x3U << PWM_I_SEL23_I_SEL21_Pos) /*!< 0x0000000C */ +//#define PWM_I_SEL23_I_SEL21 PWM_I_SEL23_I_SEL21_Msk /*!< PWM2��s IN1 external input control */ +//#define PWM_I_SEL23_I_SEL22_Pos (4U) +//#define PWM_I_SEL23_I_SEL22_Msk (0x3U << PWM_I_SEL23_I_SEL22_Pos) /*!< 0x00000030 */ +//#define PWM_I_SEL23_I_SEL22 PWM_I_SEL23_I_SEL22_Msk /*!< PWM2��s IN2 external input control */ +//#define PWM_I_SEL23_I_SEL30_Pos (16U) +//#define PWM_I_SEL23_I_SEL30_Msk (0x3U << PWM_I_SEL23_I_SEL30_Pos) /*!< 0x00030000 */ +//#define PWM_I_SEL23_I_SEL30 PWM_I_SEL23_I_SEL30_Msk /*!< PWM3��s IN0 external input control */ +//#define PWM_I_SEL23_I_SEL31_Pos (18U) +//#define PWM_I_SEL23_I_SEL31_Msk (0x3U << PWM_I_SEL23_I_SEL31_Pos) /*!< 0x000C0000 */ +//#define PWM_I_SEL23_I_SEL31 PWM_I_SEL23_I_SEL31_Msk /*!< PWM3��s IN1 external input control */ +//#define PWM_I_SEL23_I_SEL32_Pos (20U) +//#define PWM_I_SEL23_I_SEL32_Msk (0x3U << PWM_I_SEL23_I_SEL32_Pos) /*!< 0x00300000 */ +//#define PWM_I_SEL23_I_SEL32 PWM_I_SEL23_I_SEL32_Msk /*!< PWM3��s IN2 external input control */ + +/******************************************************************************/ +/* */ +/* LCD controller (LCD) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for LCD_FB00~27 register ******************/ +#define LCD_FB_WORD_Pos (0U) +#define LCD_FB_WORD_Msk (0xFFFFFFFFU << LCD_FB_WORD_Pos) /*!< 0xFFFFFFFF */ +#define LCD_FB_WORD LCD_FB_WORD_Msk /*!< LCD Frame buffer x register bit0~31 */ +#define LCD_FB_BYTE0_Pos (0U) +#define LCD_FB_BYTE0_Msk (0xFFU << LCD_FB_BYTE0_Pos) /*!< 0x000000FF */ +#define LCD_FB_BYTE0 LCD_FB_BYTE0_Msk /*!< LCD Frame buffer x register bit0~7 */ +#define LCD_FB_BYTE1_Pos (8U) +#define LCD_FB_BYTE1_Msk (0xFFU << LCD_FB_BYTE1_Pos) /*!< 0x0000FF00 */ +#define LCD_FB_BYTE1 LCD_FB_BYTE1_Msk /*!< LCD Frame buffer x register bit8~15 */ +#define LCD_FB_BYTE2_Pos (16U) +#define LCD_FB_BYTE2_Msk (0xFFU << LCD_FB_BYTE2_Pos) /*!< 0x00FF0000 */ +#define LCD_FB_BYTE2 LCD_FB_BYTE2_Msk /*!< LCD Frame buffer x register bit16~23 */ +#define LCD_FB_BYTE3_Pos (24U) +#define LCD_FB_BYTE3_Msk (0xFFU << LCD_FB_BYTE3_Pos) /*!< 0xFF000000 */ +#define LCD_FB_BYTE3 LCD_FB_BYTE3_Msk /*!< LCD Frame buffer x register bit24~31 */ + +/************** Bits definition for LCD_CTRL register ******************/ +#define LCD_CTRL_FRQ_Pos (0U) +#define LCD_CTRL_FRQ_Msk (0x3U << LCD_CTRL_FRQ_Pos) /*!< 0x00000003 */ +#define LCD_CTRL_FRQ LCD_CTRL_FRQ_Msk /*!< LCD scan frequency */ +#define LCD_CTRL_FRQ_64HZ (0x0U << LCD_CTRL_FRQ_Pos) /*!< 0x00000000 */ +#define LCD_CTRL_FRQ_128HZ (0x1U << LCD_CTRL_FRQ_Pos) /*!< 0x00000001 */ +#define LCD_CTRL_FRQ_256HZ (0x2U << LCD_CTRL_FRQ_Pos) /*!< 0x00000002 */ +#define LCD_CTRL_FRQ_512HZ (0x3U << LCD_CTRL_FRQ_Pos) /*!< 0x00000003 */ +#define LCD_CTRL_DRV_Pos (2U) +#define LCD_CTRL_DRV_Msk (0x3U << LCD_CTRL_DRV_Pos) /*!< 0x0000000C */ +#define LCD_CTRL_DRV LCD_CTRL_DRV_Msk /*!< LCD driving resister control register */ +#define LCD_CTRL_DRV_300KOHM (0x0U << LCD_CTRL_DRV_Pos) /*!< 0x00000000 */ +#define LCD_CTRL_DRV_600KOHM (0x1U << LCD_CTRL_DRV_Pos) /*!< 0x00000004 */ +#define LCD_CTRL_DRV_150KOHM (0x2U << LCD_CTRL_DRV_Pos) /*!< 0x00000008 */ +#define LCD_CTRL_DRV_200KOHM (0x3U << LCD_CTRL_DRV_Pos) /*!< 0x0000000C */ +#define LCD_CTRL_TYPE_Pos (4U) +#define LCD_CTRL_TYPE_Msk (0x3U << LCD_CTRL_TYPE_Pos) /*!< 0x00000030 */ +#define LCD_CTRL_TYPE LCD_CTRL_TYPE_Msk /*!< LCD type control register */ +#define LCD_CTRL_TYPE_4COM (0x0U << LCD_CTRL_TYPE_Pos) /*!< 0x00000000 */ +#define LCD_CTRL_TYPE_6COM (0x1U << LCD_CTRL_TYPE_Pos) /*!< 0x00000010 */ +#define LCD_CTRL_TYPE_8COM (0x2U << LCD_CTRL_TYPE_Pos) /*!< 0x00000020 */ +#define LCD_CTRL_EN_Pos (7U) +#define LCD_CTRL_EN_Msk (0x1U << LCD_CTRL_EN_Pos) /*!< 0x00000080 */ +#define LCD_CTRL_EN LCD_CTRL_EN_Msk /*!< LCD controller enable register */ + +/************** Bits definition for LCD_CTRL2 register ******************/ +#define LCD_CTRL2_BKFILL_Pos (4U) +#define LCD_CTRL2_BKFILL_Msk (0x1U << LCD_CTRL2_BKFILL_Pos) /*!< 0x00000010 */ +#define LCD_CTRL2_BKFILL LCD_CTRL2_BKFILL_Msk /*!< Fill value at blank period */ +#define LCD_CTRL2_FBMODE_Pos (6U) +#define LCD_CTRL2_FBMODE_Msk (0x3U << LCD_CTRL2_FBMODE_Pos) /*!< 0x000000C0 */ +#define LCD_CTRL2_FBMODE LCD_CTRL2_FBMODE_Msk /*!< LCD frame buffer switch mode control register */ +#define LCD_CTRL2_FBMODE_BUFA (0x0U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000000 */ +#define LCD_CTRL2_FBMODE_BUFAANDBUFB (0x1U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000040 */ +#define LCD_CTRL2_FBMODE_BUFAANDBLANK (0x2U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000080 */ +#define LCD_CTRL2_SWPR_Pos (8U) +#define LCD_CTRL2_SWPR_Msk (0xFFU << LCD_CTRL2_SWPR_Pos) /*!< 0x000FF00 */ +#define LCD_CTRL2_SWPR LCD_CTRL2_SWPR_Msk /*!< Frame buffer switch period */ + +/************** Bits definition for LCD_SEGCTRL0 register ******************/ +#define LCD_SEGCTRL0_SEG0_Pos (0U) +#define LCD_SEGCTRL0_SEG0_Msk (0x1U << LCD_SEGCTRL0_SEG0_Pos) /*!< 0x00000001 */ +#define LCD_SEGCTRL0_SEG0 LCD_SEGCTRL0_SEG0_Msk /*!< SEG 0��s enable control */ +#define LCD_SEGCTRL0_SEG1_Pos (1U) +#define LCD_SEGCTRL0_SEG1_Msk (0x1U << LCD_SEGCTRL0_SEG1_Pos) /*!< 0x00000002 */ +#define LCD_SEGCTRL0_SEG1 LCD_SEGCTRL0_SEG1_Msk /*!< SEG 1��s enable control */ +#define LCD_SEGCTRL0_SEG2_Pos (2U) +#define LCD_SEGCTRL0_SEG2_Msk (0x1U << LCD_SEGCTRL0_SEG2_Pos) /*!< 0x00000004 */ +#define LCD_SEGCTRL0_SEG2 LCD_SEGCTRL0_SEG2_Msk /*!< SEG 2��s enable control */ +#define LCD_SEGCTRL0_SEG3_Pos (3U) +#define LCD_SEGCTRL0_SEG3_Msk (0x1U << LCD_SEGCTRL0_SEG3_Pos) /*!< 0x00000008 */ +#define LCD_SEGCTRL0_SEG3 LCD_SEGCTRL0_SEG3_Msk /*!< SEG 3��s enable control */ +#define LCD_SEGCTRL0_SEG4_Pos (4U) +#define LCD_SEGCTRL0_SEG4_Msk (0x1U << LCD_SEGCTRL0_SEG4_Pos) /*!< 0x00000010 */ +#define LCD_SEGCTRL0_SEG4 LCD_SEGCTRL0_SEG4_Msk /*!< SEG 4��s enable control */ +#define LCD_SEGCTRL0_SEG5_Pos (5U) +#define LCD_SEGCTRL0_SEG5_Msk (0x1U << LCD_SEGCTRL0_SEG5_Pos) /*!< 0x00000020 */ +#define LCD_SEGCTRL0_SEG5 LCD_SEGCTRL0_SEG5_Msk /*!< SEG 5��s enable control */ +#define LCD_SEGCTRL0_SEG6_Pos (6U) +#define LCD_SEGCTRL0_SEG6_Msk (0x1U << LCD_SEGCTRL0_SEG6_Pos) /*!< 0x00000040 */ +#define LCD_SEGCTRL0_SEG6 LCD_SEGCTRL0_SEG6_Msk /*!< SEG 6��s enable control */ +#define LCD_SEGCTRL0_SEG7_Pos (7U) +#define LCD_SEGCTRL0_SEG7_Msk (0x1U << LCD_SEGCTRL0_SEG7_Pos) /*!< 0x00000080 */ +#define LCD_SEGCTRL0_SEG7 LCD_SEGCTRL0_SEG7_Msk /*!< SEG 7��s enable control */ +#define LCD_SEGCTRL0_SEG8_Pos (8U) +#define LCD_SEGCTRL0_SEG8_Msk (0x1U << LCD_SEGCTRL0_SEG8_Pos) /*!< 0x00000100 */ +#define LCD_SEGCTRL0_SEG8 LCD_SEGCTRL0_SEG8_Msk /*!< SEG 8��s enable control */ +#define LCD_SEGCTRL0_SEG9_Pos (9U) +#define LCD_SEGCTRL0_SEG9_Msk (0x1U << LCD_SEGCTRL0_SEG9_Pos) /*!< 0x00000200 */ +#define LCD_SEGCTRL0_SEG9 LCD_SEGCTRL0_SEG9_Msk /*!< SEG 9��s enable control */ +#define LCD_SEGCTRL0_SEG10_Pos (10U) +#define LCD_SEGCTRL0_SEG10_Msk (0x1U << LCD_SEGCTRL0_SEG10_Pos) /*!< 0x00000400 */ +#define LCD_SEGCTRL0_SEG10 LCD_SEGCTRL0_SEG10_Msk /*!< SEG 10��s enable control */ +#define LCD_SEGCTRL0_SEG11_Pos (11U) +#define LCD_SEGCTRL0_SEG11_Msk (0x1U << LCD_SEGCTRL0_SEG11_Pos) /*!< 0x00000800 */ +#define LCD_SEGCTRL0_SEG11 LCD_SEGCTRL0_SEG11_Msk /*!< SEG 11��s enable control */ +#define LCD_SEGCTRL0_SEG12_Pos (12U) +#define LCD_SEGCTRL0_SEG12_Msk (0x1U << LCD_SEGCTRL0_SEG12_Pos) /*!< 0x00001000 */ +#define LCD_SEGCTRL0_SEG12 LCD_SEGCTRL0_SEG12_Msk /*!< SEG 12��s enable control */ +#define LCD_SEGCTRL0_SEG13_Pos (13U) +#define LCD_SEGCTRL0_SEG13_Msk (0x1U << LCD_SEGCTRL0_SEG13_Pos) /*!< 0x00002000 */ +#define LCD_SEGCTRL0_SEG13 LCD_SEGCTRL0_SEG13_Msk /*!< SEG 13��s enable control */ +#define LCD_SEGCTRL0_SEG14_Pos (14U) +#define LCD_SEGCTRL0_SEG14_Msk (0x1U << LCD_SEGCTRL0_SEG14_Pos) /*!< 0x00004000 */ +#define LCD_SEGCTRL0_SEG14 LCD_SEGCTRL0_SEG14_Msk /*!< SEG 14��s enable control */ +#define LCD_SEGCTRL0_SEG15_Pos (15U) +#define LCD_SEGCTRL0_SEG15_Msk (0x1U << LCD_SEGCTRL0_SEG15_Pos) /*!< 0x00008000 */ +#define LCD_SEGCTRL0_SEG15 LCD_SEGCTRL0_SEG15_Msk /*!< SEG 15��s enable control */ +#define LCD_SEGCTRL0_SEG16_Pos (16U) +#define LCD_SEGCTRL0_SEG16_Msk (0x1U << LCD_SEGCTRL0_SEG16_Pos) /*!< 0x00010000 */ +#define LCD_SEGCTRL0_SEG16 LCD_SEGCTRL0_SEG16_Msk /*!< SEG 16��s enable control */ +#define LCD_SEGCTRL0_SEG17_Pos (17U) +#define LCD_SEGCTRL0_SEG17_Msk (0x1U << LCD_SEGCTRL0_SEG17_Pos) /*!< 0x00020000 */ +#define LCD_SEGCTRL0_SEG17 LCD_SEGCTRL0_SEG17_Msk /*!< SEG 17��s enable control */ +#define LCD_SEGCTRL0_SEG18_Pos (18U) +#define LCD_SEGCTRL0_SEG18_Msk (0x1U << LCD_SEGCTRL0_SEG18_Pos) /*!< 0x00040000 */ +#define LCD_SEGCTRL0_SEG18 LCD_SEGCTRL0_SEG18_Msk /*!< SEG 18��s enable control */ +#define LCD_SEGCTRL0_SEG19_Pos (19U) +#define LCD_SEGCTRL0_SEG19_Msk (0x1U << LCD_SEGCTRL0_SEG19_Pos) /*!< 0x00080000 */ +#define LCD_SEGCTRL0_SEG19 LCD_SEGCTRL0_SEG19_Msk /*!< SEG 19��s enable control */ +#define LCD_SEGCTRL0_SEG20_Pos (20U) +#define LCD_SEGCTRL0_SEG20_Msk (0x1U << LCD_SEGCTRL0_SEG20_Pos) /*!< 0x00100000 */ +#define LCD_SEGCTRL0_SEG20 LCD_SEGCTRL0_SEG20_Msk /*!< SEG 20��s enable control */ +#define LCD_SEGCTRL0_SEG21_Pos (21U) +#define LCD_SEGCTRL0_SEG21_Msk (0x1U << LCD_SEGCTRL0_SEG21_Pos) /*!< 0x00200000 */ +#define LCD_SEGCTRL0_SEG21 LCD_SEGCTRL0_SEG21_Msk /*!< SEG 21��s enable control */ +#define LCD_SEGCTRL0_SEG22_Pos (22U) +#define LCD_SEGCTRL0_SEG22_Msk (0x1U << LCD_SEGCTRL0_SEG22_Pos) /*!< 0x00400000 */ +#define LCD_SEGCTRL0_SEG22 LCD_SEGCTRL0_SEG22_Msk /*!< SEG 22��s enable control */ +#define LCD_SEGCTRL0_SEG23_Pos (23U) +#define LCD_SEGCTRL0_SEG23_Msk (0x1U << LCD_SEGCTRL0_SEG23_Pos) /*!< 0x00800000 */ +#define LCD_SEGCTRL0_SEG23 LCD_SEGCTRL0_SEG23_Msk /*!< SEG 23��s enable control */ +#define LCD_SEGCTRL0_SEG24_Pos (24U) +#define LCD_SEGCTRL0_SEG24_Msk (0x1U << LCD_SEGCTRL0_SEG24_Pos) /*!< 0x01000000 */ +#define LCD_SEGCTRL0_SEG24 LCD_SEGCTRL0_SEG24_Msk /*!< SEG 24��s enable control */ +#define LCD_SEGCTRL0_SEG25_Pos (25U) +#define LCD_SEGCTRL0_SEG25_Msk (0x1U << LCD_SEGCTRL0_SEG25_Pos) /*!< 0x02000000 */ +#define LCD_SEGCTRL0_SEG25 LCD_SEGCTRL0_SEG25_Msk /*!< SEG 25��s enable control */ +#define LCD_SEGCTRL0_SEG26_Pos (26U) +#define LCD_SEGCTRL0_SEG26_Msk (0x1U << LCD_SEGCTRL0_SEG26_Pos) /*!< 0x04000000 */ +#define LCD_SEGCTRL0_SEG26 LCD_SEGCTRL0_SEG26_Msk /*!< SEG 26��s enable control */ +#define LCD_SEGCTRL0_SEG27_Pos (27U) +#define LCD_SEGCTRL0_SEG27_Msk (0x1U << LCD_SEGCTRL0_SEG27_Pos) /*!< 0x08000000 */ +#define LCD_SEGCTRL0_SEG27 LCD_SEGCTRL0_SEG27_Msk /*!< SEG 27��s enable control */ +#define LCD_SEGCTRL0_SEG28_Pos (28U) +#define LCD_SEGCTRL0_SEG28_Msk (0x1U << LCD_SEGCTRL0_SEG28_Pos) /*!< 0x10000000 */ +#define LCD_SEGCTRL0_SEG28 LCD_SEGCTRL0_SEG28_Msk /*!< SEG 28��s enable control */ +#define LCD_SEGCTRL0_SEG29_Pos (29U) +#define LCD_SEGCTRL0_SEG29_Msk (0x1U << LCD_SEGCTRL0_SEG29_Pos) /*!< 0x20000000 */ +#define LCD_SEGCTRL0_SEG29 LCD_SEGCTRL0_SEG29_Msk /*!< SEG 29��s enable control */ +#define LCD_SEGCTRL0_SEG30_Pos (30U) +#define LCD_SEGCTRL0_SEG30_Msk (0x1U << LCD_SEGCTRL0_SEG30_Pos) /*!< 0x40000000 */ +#define LCD_SEGCTRL0_SEG30 LCD_SEGCTRL0_SEG30_Msk /*!< SEG 30��s enable control */ +#define LCD_SEGCTRL0_SEG31_Pos (31U) +#define LCD_SEGCTRL0_SEG31_Msk (0x1U << LCD_SEGCTRL0_SEG31_Pos) /*!< 0x80000000 */ +#define LCD_SEGCTRL0_SEG31 LCD_SEGCTRL0_SEG31_Msk /*!< SEG 31��s enable control */ + +/************** Bits definition for LCD_SEGCTRL1 register ******************/ +#define LCD_SEGCTRL1_SEG32_Pos (0U) +#define LCD_SEGCTRL1_SEG32_Msk (0x1U << LCD_SEGCTRL1_SEG32_Pos) /*!< 0x00000001 */ +#define LCD_SEGCTRL1_SEG32 LCD_SEGCTRL1_SEG32_Msk /*!< SEG 32��s enable control */ +#define LCD_SEGCTRL1_SEG33_Pos (1U) +#define LCD_SEGCTRL1_SEG33_Msk (0x1U << LCD_SEGCTRL1_SEG33_Pos) /*!< 0x00000002 */ +#define LCD_SEGCTRL1_SEG33 LCD_SEGCTRL1_SEG33_Msk /*!< SEG 33��s enable control */ +#define LCD_SEGCTRL1_SEG34_Pos (2U) +#define LCD_SEGCTRL1_SEG34_Msk (0x1U << LCD_SEGCTRL1_SEG34_Pos) /*!< 0x00000004 */ +#define LCD_SEGCTRL1_SEG34 LCD_SEGCTRL1_SEG34_Msk /*!< SEG 34��s enable control */ +#define LCD_SEGCTRL1_SEG35_Pos (3U) +#define LCD_SEGCTRL1_SEG35_Msk (0x1U << LCD_SEGCTRL1_SEG35_Pos) /*!< 0x00000008 */ +#define LCD_SEGCTRL1_SEG35 LCD_SEGCTRL1_SEG35_Msk /*!< SEG 35��s enable control */ +#define LCD_SEGCTRL1_SEG36_Pos (4U) +#define LCD_SEGCTRL1_SEG36_Msk (0x1U << LCD_SEGCTRL1_SEG36_Pos) /*!< 0x00000010 */ +#define LCD_SEGCTRL1_SEG36 LCD_SEGCTRL1_SEG36_Msk /*!< SEG 36��s enable control */ +#define LCD_SEGCTRL1_SEG37_Pos (5U) +#define LCD_SEGCTRL1_SEG37_Msk (0x1U << LCD_SEGCTRL1_SEG37_Pos) /*!< 0x00000020 */ +#define LCD_SEGCTRL1_SEG37 LCD_SEGCTRL1_SEG37_Msk /*!< SEG 37��s enable control */ +#define LCD_SEGCTRL1_SEG38_Pos (6U) +#define LCD_SEGCTRL1_SEG38_Msk (0x1U << LCD_SEGCTRL1_SEG38_Pos) /*!< 0x00000040 */ +#define LCD_SEGCTRL1_SEG38 LCD_SEGCTRL1_SEG38_Msk /*!< SEG 38��s enable control */ +#define LCD_SEGCTRL1_SEG39_Pos (7U) +#define LCD_SEGCTRL1_SEG39_Msk (0x1U << LCD_SEGCTRL1_SEG39_Pos) /*!< 0x00000080 */ +#define LCD_SEGCTRL1_SEG39 LCD_SEGCTRL1_SEG39_Msk /*!< SEG 39��s enable control */ +#define LCD_SEGCTRL1_SEG40_Pos (8U) +#define LCD_SEGCTRL1_SEG40_Msk (0x1U << LCD_SEGCTRL1_SEG40_Pos) /*!< 0x00000100 */ +#define LCD_SEGCTRL1_SEG40 LCD_SEGCTRL1_SEG40_Msk /*!< SEG 40��s enable control */ +#define LCD_SEGCTRL1_SEG41_Pos (9U) +#define LCD_SEGCTRL1_SEG41_Msk (0x1U << LCD_SEGCTRL1_SEG41_Pos) /*!< 0x00000200 */ +#define LCD_SEGCTRL1_SEG41 LCD_SEGCTRL1_SEG41_Msk /*!< SEG 41��s enable control */ +#define LCD_SEGCTRL1_SEG42_Pos (10U) +#define LCD_SEGCTRL1_SEG42_Msk (0x1U << LCD_SEGCTRL1_SEG42_Pos) /*!< 0x00000400 */ +#define LCD_SEGCTRL1_SEG42 LCD_SEGCTRL1_SEG42_Msk /*!< SEG 42��s enable control */ +#define LCD_SEGCTRL1_SEG43_Pos (11U) +#define LCD_SEGCTRL1_SEG43_Msk (0x1U << LCD_SEGCTRL1_SEG43_Pos) /*!< 0x00000800 */ +#define LCD_SEGCTRL1_SEG43 LCD_SEGCTRL1_SEG43_Msk /*!< SEG 43��s enable control */ +#define LCD_SEGCTRL1_SEG44_Pos (12U) +#define LCD_SEGCTRL1_SEG44_Msk (0x1U << LCD_SEGCTRL1_SEG44_Pos) /*!< 0x00001000 */ +#define LCD_SEGCTRL1_SEG44 LCD_SEGCTRL1_SEG44_Msk /*!< SEG 44��s enable control */ +#define LCD_SEGCTRL1_SEG45_Pos (13U) +#define LCD_SEGCTRL1_SEG45_Msk (0x1U << LCD_SEGCTRL1_SEG45_Pos) /*!< 0x00002000 */ +#define LCD_SEGCTRL1_SEG45 LCD_SEGCTRL1_SEG45_Msk /*!< SEG 45��s enable control */ +#define LCD_SEGCTRL1_SEG46_Pos (14U) +#define LCD_SEGCTRL1_SEG46_Msk (0x1U << LCD_SEGCTRL1_SEG46_Pos) /*!< 0x00004000 */ +#define LCD_SEGCTRL1_SEG46 LCD_SEGCTRL1_SEG46_Msk /*!< SEG 46��s enable control */ +#define LCD_SEGCTRL1_SEG47_Pos (15U) +#define LCD_SEGCTRL1_SEG47_Msk (0x1U << LCD_SEGCTRL1_SEG47_Pos) /*!< 0x00008000 */ +#define LCD_SEGCTRL1_SEG47 LCD_SEGCTRL1_SEG47_Msk /*!< SEG 47��s enable control */ +#define LCD_SEGCTRL1_SEG48_Pos (16U) +#define LCD_SEGCTRL1_SEG48_Msk (0x1U << LCD_SEGCTRL1_SEG48_Pos) /*!< 0x00010000 */ +#define LCD_SEGCTRL1_SEG48 LCD_SEGCTRL1_SEG48_Msk /*!< SEG 48��s enable control */ +#define LCD_SEGCTRL1_SEG49_Pos (17U) +#define LCD_SEGCTRL1_SEG49_Msk (0x1U << LCD_SEGCTRL1_SEG49_Pos) /*!< 0x00020000 */ +#define LCD_SEGCTRL1_SEG49 LCD_SEGCTRL1_SEG49_Msk /*!< SEG 49��s enable control */ +#define LCD_SEGCTRL1_SEG50_Pos (18U) +#define LCD_SEGCTRL1_SEG50_Msk (0x1U << LCD_SEGCTRL1_SEG50_Pos) /*!< 0x00040000 */ +#define LCD_SEGCTRL1_SEG50 LCD_SEGCTRL1_SEG50_Msk /*!< SEG 50��s enable control */ +#define LCD_SEGCTRL1_SEG51_Pos (19U) +#define LCD_SEGCTRL1_SEG51_Msk (0x1U << LCD_SEGCTRL1_SEG51_Pos) /*!< 0x00080000 */ +#define LCD_SEGCTRL1_SEG51 LCD_SEGCTRL1_SEG51_Msk /*!< SEG 51��s enable control */ +#define LCD_SEGCTRL1_SEG52_Pos (20U) +#define LCD_SEGCTRL1_SEG52_Msk (0x1U << LCD_SEGCTRL1_SEG52_Pos) /*!< 0x00100000 */ +#define LCD_SEGCTRL1_SEG52 LCD_SEGCTRL1_SEG52_Msk /*!< SEG 52��s enable control */ +#define LCD_SEGCTRL1_SEG53_Pos (21U) +#define LCD_SEGCTRL1_SEG53_Msk (0x1U << LCD_SEGCTRL1_SEG53_Pos) /*!< 0x00200000 */ +#define LCD_SEGCTRL1_SEG53 LCD_SEGCTRL1_SEG53_Msk /*!< SEG 53��s enable control */ +#define LCD_SEGCTRL1_SEG54_Pos (22U) +#define LCD_SEGCTRL1_SEG54_Msk (0x1U << LCD_SEGCTRL1_SEG54_Pos) /*!< 0x00400000 */ +#define LCD_SEGCTRL1_SEG54 LCD_SEGCTRL1_SEG54_Msk /*!< SEG 54��s enable control */ +#define LCD_SEGCTRL1_SEG55_Pos (23U) +#define LCD_SEGCTRL1_SEG55_Msk (0x1U << LCD_SEGCTRL1_SEG55_Pos) /*!< 0x00800000 */ +#define LCD_SEGCTRL1_SEG55 LCD_SEGCTRL1_SEG55_Msk /*!< SEG 55��s enable control */ +#define LCD_SEGCTRL1_SEG56_Pos (24U) +#define LCD_SEGCTRL1_SEG56_Msk (0x1U << LCD_SEGCTRL1_SEG56_Pos) /*!< 0x01000000 */ +#define LCD_SEGCTRL1_SEG56 LCD_SEGCTRL1_SEG56_Msk /*!< SEG 56��s enable control */ +#define LCD_SEGCTRL1_SEG57_Pos (25U) +#define LCD_SEGCTRL1_SEG57_Msk (0x1U << LCD_SEGCTRL1_SEG57_Pos) /*!< 0x02000000 */ +#define LCD_SEGCTRL1_SEG57 LCD_SEGCTRL1_SEG57_Msk /*!< SEG 57��s enable control */ +#define LCD_SEGCTRL1_SEG58_Pos (26U) +#define LCD_SEGCTRL1_SEG58_Msk (0x1U << LCD_SEGCTRL1_SEG58_Pos) /*!< 0x04000000 */ +#define LCD_SEGCTRL1_SEG58 LCD_SEGCTRL1_SEG58_Msk /*!< SEG 58��s enable control */ +#define LCD_SEGCTRL1_SEG59_Pos (27U) +#define LCD_SEGCTRL1_SEG59_Msk (0x1U << LCD_SEGCTRL1_SEG59_Pos) /*!< 0x08000000 */ +#define LCD_SEGCTRL1_SEG59 LCD_SEGCTRL1_SEG59_Msk /*!< SEG 59��s enable control */ +#define LCD_SEGCTRL1_SEG60_Pos (28U) +#define LCD_SEGCTRL1_SEG60_Msk (0x1U << LCD_SEGCTRL1_SEG60_Pos) /*!< 0x10000000 */ +#define LCD_SEGCTRL1_SEG60 LCD_SEGCTRL1_SEG60_Msk /*!< SEG 60��s enable control */ +#define LCD_SEGCTRL1_SEG61_Pos (29U) +#define LCD_SEGCTRL1_SEG61_Msk (0x1U << LCD_SEGCTRL1_SEG61_Pos) /*!< 0x20000000 */ +#define LCD_SEGCTRL1_SEG61 LCD_SEGCTRL1_SEG61_Msk /*!< SEG 61��s enable control */ +#define LCD_SEGCTRL1_SEG62_Pos (30U) +#define LCD_SEGCTRL1_SEG62_Msk (0x1U << LCD_SEGCTRL1_SEG62_Pos) /*!< 0x40000000 */ +#define LCD_SEGCTRL1_SEG62 LCD_SEGCTRL1_SEG62_Msk /*!< SEG 62��s enable control */ +#define LCD_SEGCTRL1_SEG63_Pos (31U) +#define LCD_SEGCTRL1_SEG63_Msk (0x1U << LCD_SEGCTRL1_SEG63_Pos) /*!< 0x80000000 */ +#define LCD_SEGCTRL1_SEG63 LCD_SEGCTRL1_SEG63_Msk /*!< SEG 63��s enable control */ + +/************** Bits definition for LCD_SEGCTRL2 register ******************/ +#define LCD_SEGCTRL2_SEG64_Pos (0U) +#define LCD_SEGCTRL2_SEG64_Msk (0x1U << LCD_SEGCTRL2_SEG64_Pos) /*!< 0x00000001 */ +#define LCD_SEGCTRL2_SEG64 LCD_SEGCTRL2_SEG64_Msk /*!< SEG 64��s enable control */ +#define LCD_SEGCTRL2_SEG65_Pos (1U) +#define LCD_SEGCTRL2_SEG65_Msk (0x1U << LCD_SEGCTRL2_SEG65_Pos) /*!< 0x00000002 */ +#define LCD_SEGCTRL2_SEG65 LCD_SEGCTRL2_SEG65_Msk /*!< SEG 65��s enable control */ +#define LCD_SEGCTRL2_SEG66_Pos (2U) +#define LCD_SEGCTRL2_SEG66_Msk (0x1U << LCD_SEGCTRL2_SEG66_Pos) /*!< 0x00000004 */ +#define LCD_SEGCTRL2_SEG66 LCD_SEGCTRL2_SEG66_Msk /*!< SEG 66��s enable control */ +#define LCD_SEGCTRL2_SEG67_Pos (3U) +#define LCD_SEGCTRL2_SEG67_Msk (0x1U << LCD_SEGCTRL2_SEG67_Pos) /*!< 0x00000008 */ +#define LCD_SEGCTRL2_SEG67 LCD_SEGCTRL2_SEG67_Msk /*!< SEG 67��s enable control */ +#define LCD_SEGCTRL2_SEG68_Pos (4U) +#define LCD_SEGCTRL2_SEG68_Msk (0x1U << LCD_SEGCTRL2_SEG68_Pos) /*!< 0x00000010 */ +#define LCD_SEGCTRL2_SEG68 LCD_SEGCTRL2_SEG68_Msk /*!< SEG 68��s enable control */ +#define LCD_SEGCTRL2_SEG69_Pos (5U) +#define LCD_SEGCTRL2_SEG69_Msk (0x1U << LCD_SEGCTRL2_SEG69_Pos) /*!< 0x00000020 */ +#define LCD_SEGCTRL2_SEG69 LCD_SEGCTRL2_SEG69_Msk /*!< SEG 69��s enable control */ +#define LCD_SEGCTRL2_SEG70_Pos (6U) +#define LCD_SEGCTRL2_SEG70_Msk (0x1U << LCD_SEGCTRL2_SEG70_Pos) /*!< 0x00000040 */ +#define LCD_SEGCTRL2_SEG70 LCD_SEGCTRL2_SEG70_Msk /*!< SEG 70��s enable control */ +#define LCD_SEGCTRL2_SEG71_Pos (7U) +#define LCD_SEGCTRL2_SEG71_Msk (0x1U << LCD_SEGCTRL2_SEG71_Pos) /*!< 0x00000080 */ +#define LCD_SEGCTRL2_SEG71 LCD_SEGCTRL2_SEG71_Msk /*!< SEG 71��s enable control */ +#define LCD_SEGCTRL2_SEG72_Pos (8U) +#define LCD_SEGCTRL2_SEG72_Msk (0x1U << LCD_SEGCTRL2_SEG72_Pos) /*!< 0x00000100 */ +#define LCD_SEGCTRL2_SEG72 LCD_SEGCTRL2_SEG72_Msk /*!< SEG 72��s enable control */ +#define LCD_SEGCTRL2_SEG73_Pos (9U) +#define LCD_SEGCTRL2_SEG73_Msk (0x1U << LCD_SEGCTRL2_SEG73_Pos) /*!< 0x00000200 */ +#define LCD_SEGCTRL2_SEG73 LCD_SEGCTRL2_SEG73_Msk /*!< SEG 73��s enable control */ +#define LCD_SEGCTRL2_SEG74_Pos (10U) +#define LCD_SEGCTRL2_SEG74_Msk (0x1U << LCD_SEGCTRL2_SEG74_Pos) /*!< 0x00000400 */ +#define LCD_SEGCTRL2_SEG74 LCD_SEGCTRL2_SEG74_Msk /*!< SEG 74��s enable control */ +#define LCD_SEGCTRL2_SEG75_Pos (11U) +#define LCD_SEGCTRL2_SEG75_Msk (0x1U << LCD_SEGCTRL2_SEG75_Pos) /*!< 0x00000800 */ +#define LCD_SEGCTRL2_SEG75 LCD_SEGCTRL2_SEG75_Msk /*!< SEG 75��s enable control */ +#define LCD_SEGCTRL2_SEG76_Pos (12U) +#define LCD_SEGCTRL2_SEG76_Msk (0x1U << LCD_SEGCTRL2_SEG76_Pos) /*!< 0x00001000 */ +#define LCD_SEGCTRL2_SEG76 LCD_SEGCTRL2_SEG76_Msk /*!< SEG 76��s enable control */ +#define LCD_SEGCTRL2_SEG77_Pos (13U) +#define LCD_SEGCTRL2_SEG77_Msk (0x1U << LCD_SEGCTRL2_SEG77_Pos) /*!< 0x00002000 */ +#define LCD_SEGCTRL2_SEG77 LCD_SEGCTRL2_SEG77_Msk /*!< SEG 77��s enable control */ +#define LCD_SEGCTRL2_SEG78_Pos (14U) +#define LCD_SEGCTRL2_SEG78_Msk (0x1U << LCD_SEGCTRL2_SEG78_Pos) /*!< 0x00004000 */ +#define LCD_SEGCTRL2_SEG78 LCD_SEGCTRL2_SEG78_Msk /*!< SEG 78��s enable control */ +#define LCD_SEGCTRL2_SEG79_Pos (15U) +#define LCD_SEGCTRL2_SEG79_Msk (0x1U << LCD_SEGCTRL2_SEG79_Pos) /*!< 0x00008000 */ +#define LCD_SEGCTRL2_SEG79 LCD_SEGCTRL2_SEG79_Msk /*!< SEG 79��s enable control */ + +/******************************************************************************/ +/* */ +/* SPI controller (SPI) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for SPIx_CTRL register ******************/ +#define SPI_CTRL_SCKSEL_Pos (0U) +#define SPI_CTRL_SCKSEL_Msk (0x7U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000007 */ +#define SPI_CTRL_SCKSEL SPI_CTRL_SCKSEL_Msk /*!< Master mode clock selection */ +#define SPI_CTRL_SCKSEL_0 (0x1U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000001 */ +#define SPI_CTRL_SCKSEL_1 (0x2U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000002 */ +#define SPI_CTRL_SCKSEL_2 (0x4U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000004 */ +#define SPI_CTRL_SCKPOL_Pos (4U) +#define SPI_CTRL_SCKPOL_Msk (0x1U << SPI_CTRL_SCKPOL_Pos) /*!< 0x00000010 */ +#define SPI_CTRL_SCKPOL SPI_CTRL_SCKPOL_Msk /*!< SPI clock polarity */ +#define SPI_CTRL_SCKPHA_Pos (5U) +#define SPI_CTRL_SCKPHA_Msk (0x1U << SPI_CTRL_SCKPHA_Pos) /*!< 0x00000020 */ +#define SPI_CTRL_SCKPHA SPI_CTRL_SCKPHA_Msk /*!< SPI clock phase */ +#define SPI_CTRL_MOD_Pos (8U) +#define SPI_CTRL_MOD_Msk (0x1U << SPI_CTRL_MOD_Pos) /*!< 0x00000100 */ +#define SPI_CTRL_MOD SPI_CTRL_MOD_Msk /*!< SPI Mode Selection register */ +#define SPI_CTRL_SWAP_Pos (9U) +#define SPI_CTRL_SWAP_Msk (0x1U << SPI_CTRL_SWAP_Pos) /*!< 0x00000200 */ +#define SPI_CTRL_SWAP SPI_CTRL_SWAP_Msk /*!< SPI MISO/MOSI swap control register */ +#define SPI_CTRL_CSGPIO_Pos (10U) +#define SPI_CTRL_CSGPIO_Msk (0x1U << SPI_CTRL_CSGPIO_Pos) /*!< 0x00000400 */ +#define SPI_CTRL_CSGPIO SPI_CTRL_CSGPIO_Msk /*!< SPI CS pin is controlled by GPIO or H/W */ +#define SPI_CTRL_SPIRST_Pos (11U) +#define SPI_CTRL_SPIRST_Msk (0x1U << SPI_CTRL_SPIRST_Pos) /*!< 0x00000800 */ +#define SPI_CTRL_SPIRST SPI_CTRL_SPIRST_Msk /*!< SPI Soft Reset */ +#define SPI_CTRL_SPIEN_Pos (15U) +#define SPI_CTRL_SPIEN_Msk (0x1U << SPI_CTRL_SPIEN_Pos) /*!< 0x00008000 */ +#define SPI_CTRL_SPIEN SPI_CTRL_SPIEN_Msk /*!< SPI enable */ + +/************** Bits definition for SPIx_TXSTS register ******************/ +#define SPI_TXSTS_TXFFLAG_Pos (0U) +#define SPI_TXSTS_TXFFLAG_Msk (0x7U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x0000000F */ +#define SPI_TXSTS_TXFFLAG SPI_TXSTS_TXFFLAG_Msk /*!< Transmit FIFO Data Level */ +#define SPI_TXSTS_TXFLEV_Pos (4U) +#define SPI_TXSTS_TXFLEV_Msk (0x7U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000070 */ +#define SPI_TXSTS_TXFLEV SPI_TXSTS_TXFLEV_Msk /*!< Transmit FIFO interrupt level register */ +#define SPI_TXSTS_TXFLEV_0 (0x1U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000010 */ +#define SPI_TXSTS_TXFLEV_1 (0x2U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000020 */ +#define SPI_TXSTS_TXFLEV_2 (0x4U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000040 */ +#define SPI_TXSTS_TXFUR_Pos (8U) +#define SPI_TXSTS_TXFUR_Msk (0x1U << SPI_TXSTS_TXFUR_Pos) /*!< 0x00000100 */ +#define SPI_TXSTS_TXFUR SPI_TXSTS_TXFUR_Msk /*!< Transmit FIFO under run register */ +#define SPI_TXSTS_TXEMPTY_Pos (9U) +#define SPI_TXSTS_TXEMPTY_Msk (0x1U << SPI_TXSTS_TXEMPTY_Pos) /*!< 0x00000200 */ +#define SPI_TXSTS_TXEMPTY SPI_TXSTS_TXEMPTY_Msk /*!< Transmot FIFO empty register */ +#define SPI_TXSTS_TXIEN_Pos (14U) +#define SPI_TXSTS_TXIEN_Msk (0x1U << SPI_TXSTS_TXIEN_Pos) /*!< 0x00004000 */ +#define SPI_TXSTS_TXIEN SPI_TXSTS_TXIEN_Msk /*!< SPI Transmit Interrupt Enable */ +#define SPI_TXSTS_TXIF_Pos (15U) +#define SPI_TXSTS_TXIF_Msk (0x1U << SPI_TXSTS_TXIF_Pos) /*!< 0x00008000 */ +#define SPI_TXSTS_TXIF SPI_TXSTS_TXIF_Msk /*!< SPI Transmit Interrupt flag */ + +/************** Bits definition for SPIx_TXDAT register ******************/ +#define SPI_TXDAT_SPITXD_Pos (0U) +#define SPI_TXDAT_SPITXD_Msk (0xFFU << SPI_TXDAT_SPITXD_Pos) /*!< 0x000000FF */ +#define SPI_TXDAT_SPITXD SPI_TXDAT_SPITXD_Msk /*!< Write data to SPI Transmit FIFO */ + +/************** Bits definition for SPIx_RXSTS register ******************/ +#define SPI_RXSTS_RXFFLAG_Pos (0U) +#define SPI_RXSTS_RXFFLAG_Msk (0x7U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x0000000F */ +#define SPI_RXSTS_RXFFLAG SPI_RXSTS_RXFFLAG_Msk /*!< Receive FIFO Data Level */ +#define SPI_RXSTS_RXFLEV_Pos (4U) +#define SPI_RXSTS_RXFLEV_Msk (0x7U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000070 */ +#define SPI_RXSTS_RXFLEV SPI_RXSTS_RXFLEV_Msk /*!< Receive FIFO interrupt level register */ +#define SPI_RXSTS_RXFLEV_0 (0x1U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000010 */ +#define SPI_RXSTS_RXFLEV_1 (0x2U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000020 */ +#define SPI_RXSTS_RXFLEV_2 (0x4U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000040 */ +#define SPI_RXSTS_RXFOV_Pos (8U) +#define SPI_RXSTS_RXFOV_Msk (0x1U << SPI_RXSTS_RXFOV_Pos) /*!< 0x00000100 */ +#define SPI_RXSTS_RXFOV SPI_RXSTS_RXFOV_Msk /*!< Receive FIFO over run register */ +#define SPI_RXSTS_RXFULL_Pos (9U) +#define SPI_RXSTS_RXFULL_Msk (0x1U << SPI_RXSTS_RXFULL_Pos) /*!< 0x00000200 */ +#define SPI_RXSTS_RXFULL SPI_RXSTS_RXFULL_Msk /*!< Receive FIFO full register */ +#define SPI_RXSTS_RXIEN_Pos (14U) +#define SPI_RXSTS_RXIEN_Msk (0x1U << SPI_RXSTS_RXIEN_Pos) /*!< 0x00004000 */ +#define SPI_RXSTS_RXIEN SPI_RXSTS_RXIEN_Msk /*!< SPI Receive Interrupt Enable */ +#define SPI_RXSTS_RXIF_Pos (15U) +#define SPI_RXSTS_RXIF_Msk (0x1U << SPI_RXSTS_RXIF_Pos) /*!< 0x00008000 */ +#define SPI_RXSTS_RXIF SPI_RXSTS_RXIF_Msk /*!< SPI Receive Interrupt flag */ + +/************** Bits definition for SPIx_RXDAT register ******************/ +#define SPI_RXDAT_SPIRXD_Pos (0U) +#define SPI_RXDAT_SPIRXD_Msk (0xFFU << SPI_RXDAT_SPIRXD_Pos) /*!< 0x000000FF */ +#define SPI_RXDAT_SPIRXD SPI_RXDAT_SPIRXD_Msk /*!< Read data from SPI Receive FIFO */ + +/************** Bits definition for SPIx_MISC register ******************/ +#define SPI_MISC_TFE_Pos (0U) +#define SPI_MISC_TFE_Msk (0x1U << SPI_MISC_TFE_Pos) /*!< 0x0000001 */ +#define SPI_MISC_TFE SPI_MISC_TFE_Msk /*!< Transmit FIFO Empty Flag */ +#define SPI_MISC_TNF_Pos (1U) +#define SPI_MISC_TNF_Msk (0x1U << SPI_MISC_TNF_Pos) /*!< 0x0000002 */ +#define SPI_MISC_TNF SPI_MISC_TNF_Msk /*!< Transmit FIFO Not Full Flag */ +#define SPI_MISC_RNE_Pos (2U) +#define SPI_MISC_RNE_Msk (0x1U << SPI_MISC_RNE_Pos) /*!< 0x0000004 */ +#define SPI_MISC_RNE SPI_MISC_RNE_Msk /*!< Receive FIFO Not Empty Flag */ +#define SPI_MISC_RFF_Pos (3U) +#define SPI_MISC_RFF_Msk (0x1U << SPI_MISC_RFF_Pos) /*!< 0x0000008 */ +#define SPI_MISC_RFF SPI_MISC_RFF_Msk /*!< Receive FIFO Full Flag */ +#define SPI_MISC_BSY_Pos (4U) +#define SPI_MISC_BSY_Msk (0x1U << SPI_MISC_BSY_Pos) /*!< 0x0000010 */ +#define SPI_MISC_BSY SPI_MISC_BSY_Msk /*!< SPI Controller Busy Flag */ +#define SPI_MISC_SMART_Pos (8U) +#define SPI_MISC_SMART_Msk (0x1U << SPI_MISC_SMART_Pos) /*!< 0x0000100 */ +#define SPI_MISC_SMART SPI_MISC_SMART_Msk /*!< SPI FIFO SMART Mode Register */ +#define SPI_MISC_OVER_Pos (9U) +#define SPI_MISC_OVER_Msk (0x1U << SPI_MISC_OVER_Pos) /*!< 0x0000200 */ +#define SPI_MISC_OVER SPI_MISC_OVER_Msk /*!< SPI FIFO Over Write Mode */ + +/******************************************************************************/ +/* */ +/* I2C controller (I2C) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for I2C_DATA register ******************/ +#define I2C_DATA_DATA_Pos (0U) +#define I2C_DATA_DATA_Msk (0xFFU << I2C_DATA_DATA_Pos) /*!< 0x00000FF */ +#define I2C_DATA_DATA I2C_DATA_DATA_Msk /*!< The I2C_DATA register contains a byte to be transmitted through I2C bus or a byte which has just been received through I2C bus */ + +/************** Bits definition for I2C_ADDR register ******************/ +#define I2C_ADDR_GC_Pos (0U) +#define I2C_ADDR_GC_Msk (0x1U << I2C_ADDR_GC_Pos) /*!< 0x0000001 */ +#define I2C_ADDR_GC I2C_ADDR_GC_Msk /*!< General Call Address Acknowledge */ +#define I2C_ADDR_SLA_Pos (1U) +#define I2C_ADDR_SLA_Msk (0xFEU << I2C_ADDR_SLA_Pos) /*!< 0x00000FE */ +#define I2C_ADDR_SLA I2C_ADDR_SLA_Msk /*!< Own I2C slave address (7 bit) */ + +/************** Bits definition for I2C_CTRL register ******************/ +#define I2C_CTRL_CR_Pos (0U) +#define I2C_CTRL_CR_Msk (0x83U << I2C_CTRL_CR_Pos) /*!< 0x0000083 */ +#define I2C_CTRL_CR I2C_CTRL_CR_Msk /*!< Clock rate bit0-2 */ +#define I2C_CTRL_CR_0 (0x0U << I2C_CTRL_CR_Pos) /*!< 0x0000000 */ +#define I2C_CTRL_CR_1 (0x1U << I2C_CTRL_CR_Pos) /*!< 0x0000001 */ +#define I2C_CTRL_CR_2 (0x2U << I2C_CTRL_CR_Pos) /*!< 0x0000002 */ +#define I2C_CTRL_CR_3 (0x3U << I2C_CTRL_CR_Pos) /*!< 0x0000003 */ +#define I2C_CTRL_CR_4 (0x80U << I2C_CTRL_CR_Pos) /*!< 0x0000080 */ +#define I2C_CTRL_CR_5 (0x81U << I2C_CTRL_CR_Pos) /*!< 0x0000081 */ +#define I2C_CTRL_CR_6 (0x82U << I2C_CTRL_CR_Pos) /*!< 0x0000082 */ +#define I2C_CTRL_CR_7 (0x83U << I2C_CTRL_CR_Pos) /*!< 0x0000083 */ +#define I2C_CTRL_AA_Pos (2U) +#define I2C_CTRL_AA_Msk (0x1U << I2C_CTRL_AA_Pos) /*!< 0x0000004 */ +#define I2C_CTRL_AA I2C_CTRL_AA_Msk /*!< Assert Acknowledge Flag */ +#define I2C_CTRL_SI_Pos (3U) +#define I2C_CTRL_SI_Msk (0x1U << I2C_CTRL_SI_Pos) /*!< 0x0000008 */ +#define I2C_CTRL_SI I2C_CTRL_SI_Msk /*!< Serial Interrupt Flag */ +#define I2C_CTRL_STO_Pos (4U) +#define I2C_CTRL_STO_Msk (0x1U << I2C_CTRL_STO_Pos) /*!< 0x0000010 */ +#define I2C_CTRL_STO I2C_CTRL_STO_Msk /*!< STOP Flag */ +#define I2C_CTRL_STA_Pos (5U) +#define I2C_CTRL_STA_Msk (0x1U << I2C_CTRL_STA_Pos) /*!< 0x0000020 */ +#define I2C_CTRL_STA I2C_CTRL_STA_Msk /*!< START Flag */ +#define I2C_CTRL_EN_Pos (6U) +#define I2C_CTRL_EN_Msk (0x1U << I2C_CTRL_EN_Pos) /*!< 0x0000040 */ +#define I2C_CTRL_EN I2C_CTRL_EN_Msk /*!< I2C enable bit */ + +/************** Bits definition for I2C_STS register ******************/ +#define I2C_STS_STS_Pos (3U) +#define I2C_STS_STS_Msk (0x1FU << I2C_STS_STS_Pos) /*!< 0x00000F8 */ +#define I2C_STS_STS I2C_STS_STS_Msk /*!< I2C Status Code */ +#define I2C_STS_STS_0x00 (0x0U << I2C_STS_STS_Pos) /*!< 0x0000000 */ +#define I2C_STS_STS_0x08 (0x1U << I2C_STS_STS_Pos) /*!< 0x0000008 */ +#define I2C_STS_STS_0x10 (0x2U << I2C_STS_STS_Pos) /*!< 0x0000010 */ +#define I2C_STS_STS_0x18 (0x3U << I2C_STS_STS_Pos) /*!< 0x0000018 */ +#define I2C_STS_STS_0x20 (0x4U << I2C_STS_STS_Pos) /*!< 0x0000020 */ +#define I2C_STS_STS_0x28 (0x5U << I2C_STS_STS_Pos) /*!< 0x0000028 */ +#define I2C_STS_STS_0x30 (0x6U << I2C_STS_STS_Pos) /*!< 0x0000030 */ +#define I2C_STS_STS_0x38 (0x7U << I2C_STS_STS_Pos) /*!< 0x0000038 */ +#define I2C_STS_STS_0x40 (0x8U << I2C_STS_STS_Pos) /*!< 0x0000040 */ +#define I2C_STS_STS_0x48 (0x9U << I2C_STS_STS_Pos) /*!< 0x0000048 */ +#define I2C_STS_STS_0x50 (0xAU << I2C_STS_STS_Pos) /*!< 0x0000050 */ +#define I2C_STS_STS_0x58 (0xBU << I2C_STS_STS_Pos) /*!< 0x0000058 */ +#define I2C_STS_STS_0x60 (0xCU << I2C_STS_STS_Pos) /*!< 0x0000060 */ +#define I2C_STS_STS_0x68 (0xDU << I2C_STS_STS_Pos) /*!< 0x0000068 */ +#define I2C_STS_STS_0x70 (0xEU << I2C_STS_STS_Pos) /*!< 0x0000070 */ +#define I2C_STS_STS_0x78 (0xFU << I2C_STS_STS_Pos) /*!< 0x0000078 */ +#define I2C_STS_STS_0x80 (0x10U << I2C_STS_STS_Pos) /*!< 0x0000080 */ +#define I2C_STS_STS_0x88 (0x11U << I2C_STS_STS_Pos) /*!< 0x0000088 */ +#define I2C_STS_STS_0x90 (0x12U << I2C_STS_STS_Pos) /*!< 0x0000090 */ +#define I2C_STS_STS_0x98 (0x13U << I2C_STS_STS_Pos) /*!< 0x0000098 */ +#define I2C_STS_STS_0xA0 (0x14U << I2C_STS_STS_Pos) /*!< 0x00000A0 */ +#define I2C_STS_STS_0xA8 (0x15U << I2C_STS_STS_Pos) /*!< 0x00000A8 */ +#define I2C_STS_STS_0xB0 (0x16U << I2C_STS_STS_Pos) /*!< 0x00000B0 */ +#define I2C_STS_STS_0xB8 (0x17U << I2C_STS_STS_Pos) /*!< 0x00000B8 */ +#define I2C_STS_STS_0xC0 (0x18U << I2C_STS_STS_Pos) /*!< 0x00000C0 */ +#define I2C_STS_STS_0xC8 (0x19U << I2C_STS_STS_Pos) /*!< 0x00000C8 */ +#define I2C_STS_STS_0xF8 (0x1FU << I2C_STS_STS_Pos) /*!< 0x00000F8 */ + +/************** Bits definition for I2C_CTRL2 register ******************/ +#define I2C_CTRL2_INTEN_Pos (0U) +#define I2C_CTRL2_INTEN_Msk (0x1U << I2C_CTRL2_INTEN_Pos) /*!< 0x0000001 */ +#define I2C_CTRL2_INTEN I2C_CTRL2_INTEN_Msk /*!< Interrupt enable control of I2C controller */ + +/******************************************************************************/ +/* */ +/* MISC controller (MISC) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for MISC_SRAMINT register ******************/ +#define MISC_SRAMINT_PERR_Pos (0U) +#define MISC_SRAMINT_PERR_Msk (0x1U << MISC_SRAMINT_PERR_Pos) /*!< 0x00000001 */ +#define MISC_SRAMINT_PERR MISC_SRAMINT_PERR_Msk /*!< This bit indicates that a SRAM parity error is happened during the SRAM read process */ +//#define MISC_SRAMINT_HIAL_Pos (1U) +//#define MISC_SRAMINT_HIAL_Msk (0x1U << MISC_SRAMINT_HIAL_Pos) /*!< 0x00000002 */ +//#define MISC_SRAMINT_HIAL MISC_SRAMINT_HIAL_Msk /*!< This bit indicates that an invalid align access on AHB bus is occurred */ +#define MISC_SRAMINT_HIAC_Pos (2U) +#define MISC_SRAMINT_HIAC_Msk (0x1U << MISC_SRAMINT_HIAC_Pos) /*!< 0x00000004 */ +#define MISC_SRAMINT_HIAC MISC_SRAMINT_HIAC_Msk /*!< This bit indicates that an invalid address access on AHB bus is occurred */ +#define MISC_SRAMINT_PIAC_Pos (3U) +#define MISC_SRAMINT_PIAC_Msk (0x1U << MISC_SRAMINT_PIAC_Pos) /*!< 0x00000008 */ +#define MISC_SRAMINT_PIAC MISC_SRAMINT_PIAC_Msk /*!< This bit indicates that an invalid address access on APB bus is occurred */ +#define MISC_SRAMINT_LOCKUP_Pos (4U) +#define MISC_SRAMINT_LOCKUP_Msk (0x1U << MISC_SRAMINT_LOCKUP_Pos) /*!< 0x00000010 */ +#define MISC_SRAMINT_LOCKUP MISC_SRAMINT_LOCKUP_Msk /*!< This bit indicates the CM0 lockup has happened */ + +/************** Bits definition for MISC_SRAMINIT register ******************/ +#define MISC_SRAMINIT_PEN_Pos (0U) +#define MISC_SRAMINIT_PEN_Msk (0x1U << MISC_SRAMINIT_PEN_Pos) /*!< 0x00000001 */ +#define MISC_SRAMINIT_PEN MISC_SRAMINIT_PEN_Msk /*!< Parity check enable register */ +#define MISC_SRAMINIT_PERRIE_Pos (1U) +#define MISC_SRAMINIT_PERRIE_Msk (0x1U << MISC_SRAMINIT_PERRIE_Pos) /*!< 0x00000002 */ +#define MISC_SRAMINIT_PERRIE MISC_SRAMINIT_PERRIE_Msk /*!< SRAM parity error NMI enable register */ +#define MISC_SRAMINIT_INIT_Pos (2U) +#define MISC_SRAMINIT_INIT_Msk (0x1U << MISC_SRAMINIT_INIT_Pos) /*!< 0x00000004 */ +#define MISC_SRAMINIT_INIT MISC_SRAMINIT_INIT_Msk /*!< SRAM initialize register */ +//#define MISC_SRAMINIT_HIALIE_Pos (4U) +//#define MISC_SRAMINIT_HIALIE_Msk (0x1U << MISC_SRAMINIT_HIALIE_Pos) /*!< 0x00000010 */ +//#define MISC_SRAMINIT_HIALIE MISC_SRAMINIT_HIALIE_Msk /*!< AHB invalid aligned access NMI enable register */ +#define MISC_SRAMINIT_HIACIE_Pos (5U) +#define MISC_SRAMINIT_HIACIE_Msk (0x1U << MISC_SRAMINIT_HIACIE_Pos) /*!< 0x00000020 */ +#define MISC_SRAMINIT_HIACIE MISC_SRAMINIT_HIACIE_Msk /*!< AHB invalid address access NMI enable register */ +#define MISC_SRAMINIT_PIACIE_Pos (6U) +#define MISC_SRAMINIT_PIACIE_Msk (0x1U << MISC_SRAMINIT_PIACIE_Pos) /*!< 0x00000040 */ +#define MISC_SRAMINIT_PIACIE MISC_SRAMINIT_PIACIE_Msk /*!< APB invalid address access NMI enable register */ +#define MISC_SRAMINIT_LOCKIE_Pos (7U) +#define MISC_SRAMINIT_LOCKIE_Msk (0x1U << MISC_SRAMINIT_LOCKIE_Pos) /*!< 0x00000080 */ +#define MISC_SRAMINIT_LOCKIE MISC_SRAMINIT_LOCKIE_Msk /*!< CM0 lockup NMI enable register */ + +/************** Bits definition for MISC_PARERR register ******************/ +#define MISC_PARERR_PEADDR_Pos (0U) +#define MISC_PARERR_PEADDR_Msk (0xFFFU << MISC_PARERR_PEADDR_Pos) /*!< 0x00000FFF */ +#define MISC_PARERR_PEADDR MISC_PARERR_PEADDR_Msk /*!< Parity error address */ + +/************** Bits definition for MISC_IREN register ******************/ +#define MISC_IREN_IREN_Pos (0U) +#define MISC_IREN_IREN_Msk (0x3FU << MISC_IREN_IREN_Pos) /*!< 0x0000003F */ +#define MISC_IREN_IREN MISC_IREN_IREN_Msk /*!< IR enable control register */ +#define MISC_IREN_UART0 (0x01U) +#define MISC_IREN_UART1 (0x02U) +#define MISC_IREN_UART2 (0x04U) +#define MISC_IREN_UART3 (0x08U) +#define MISC_IREN_UART4 (0x10U) +#define MISC_IREN_UART5 (0x20U) + +/************** Bits definition for MISC_DUTYL register ******************/ +#define MISC_DUTYL_DUTYL_Pos (0U) +#define MISC_DUTYL_DUTYL_Msk (0xFFFFU << MISC_DUTYL_DUTYL_Pos) /*!< 0x0000FFFF */ +#define MISC_DUTYL_DUTYL MISC_DUTYL_DUTYL_Msk /*!< IR low pulse width control register */ + +/************** Bits definition for MISC_DUTYH register ******************/ +#define MISC_DUTYH_DUTYH_Pos (0U) +#define MISC_DUTYH_DUTYH_Msk (0xFFFFU << MISC_DUTYH_DUTYH_Pos) /*!< 0x0000FFFF */ +#define MISC_DUTYH_DUTYH MISC_DUTYH_DUTYH_Msk /*!< IR high pulse width control register */ + +/************** Bits definition for MISC_IRQLAT register ******************/ +#define MISC_IRQLAT_IRQLAT_Pos (0U) +#define MISC_IRQLAT_IRQLAT_Msk (0xFFU << MISC_IRQLAT_IRQLAT_Pos) /*!< 0x000000FF */ +#define MISC_IRQLAT_IRQLAT MISC_IRQLAT_IRQLAT_Msk /*!< This register is used to control the Cortex M0 IRQ latency */ +#define MISC_IRQLAT_LOCKRESET_Pos (8U) +#define MISC_IRQLAT_LOCKRESET_Msk (0x1U << MISC_IRQLAT_LOCKRESET_Pos) /*!< 0x00000100 */ +#define MISC_IRQLAT_LOCKRESET MISC_IRQLAT_LOCKRESET_Msk /*!< This register is used to control if the lockup will issue a system reset */ +#define MISC_IRQLAT_NOHARDFAULT_Pos (9U) +#define MISC_IRQLAT_NOHARDFAULT_Msk (0x1U << MISC_IRQLAT_NOHARDFAULT_Pos) /*!< 0x00000200 */ +#define MISC_IRQLAT_NOHARDFAULT MISC_IRQLAT_NOHARDFAULT_Msk /*!< This register is used to disable the hard fault generation to CPU */ + +/************** Bits definition for MISC_HIADDR register ******************/ +#define MISC_HIADDR_Pos (0U) +#define MISC_HIADDR_Msk (0xFFFFFFFFU << MISC_HIADDR_Pos) /*!< 0xFFFFFFFF */ +#define MISC_HIADDR MISC_HIADDR_Msk /*!< AHB invalid access address */ + +/************** Bits definition for MISC_PIADDR register ******************/ +#define MISC_PIADDR_Pos (0U) +#define MISC_PIADDR_Msk (0xFFFFFFFFU << MISC_PIADDR_Pos) /*!< 0xFFFFFFFF */ +#define MISC_PIADDR MISC_PIADDR_Msk /*!< APB invalid access address */ + +/************** Bits definition for MISC2_FLASHWC register ******************/ +#define MISC2_FLASHWC_FLASHWC_Pos (0U) +#define MISC2_FLASHWC_FLASHWC_Msk (0x3U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000003 */ +#define MISC2_FLASHWC_FLASHWC MISC2_FLASHWC_FLASHWC_Msk /*!< This register is used to control wait cycle of Flash access */ +#define MISC2_FLASHWC_FLASHWC_0Wait (0x0U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000000 */ +#define MISC2_FLASHWC_FLASHWC_1Wait (0x1U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000001 */ +#define MISC2_FLASHWC_FLASHWC_2Wait (0x2U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000002 */ +#define MISC2_FLASHWC_FLASHWC_3Wait (0x3U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000003 */ +#define MISC2_FLASHWC_1USCYCLE_Pos (8U) +#define MISC2_FLASHWC_1USCYCLE_Msk (0x3FU << MISC2_FLASHWC_1USCYCLE_Pos) /*!< 0x00003F00 */ +#define MISC2_FLASHWC_1USCYCLE MISC2_FLASHWC_1USCYCLE_Msk /*!< This register is used for Flash controller to calculate 1us tick from AHB clock */ + +/************** Bits definition for MISC2_CLKSEL register ******************/ +#define MISC2_CLKSEL_CLKSEL_Pos (0U) +#define MISC2_CLKSEL_CLKSEL_Msk (0x7U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000007 */ +#define MISC2_CLKSEL_CLKSEL MISC2_CLKSEL_CLKSEL_Msk /*!< This register is used to control AHB clock source */ +#define MISC2_CLKSEL_CLKSEL_RCOH (0x0U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000000 */ +#define MISC2_CLKSEL_CLKSEL_XOH (0x1U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000001 */ +#define MISC2_CLKSEL_CLKSEL_PLLH (0x2U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000002 */ +#define MISC2_CLKSEL_CLKSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000003 */ +#define MISC2_CLKSEL_CLKSEL_PLLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000004 */ + +/************** Bits definition for MISC2_CLKDIVH register ******************/ +#define MISC2_CLKDIVH_CLKDIVH_Pos (0U) +#define MISC2_CLKDIVH_CLKDIVH_Msk (0xFFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FF */ +#define MISC2_CLKDIVH_CLKDIVH MISC2_CLKDIVH_CLKDIVH_Msk /*!< This register is used to control AHB clock divider */ +#define MISC2_CLKDIVH_CLKDIVH_DIV1 (0x0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000000 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV2 (0x1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000001 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV3 (0x2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000002 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV4 (0x3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000003 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV5 (0x4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000004 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV6 (0x5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000005 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV7 (0x6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000006 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV8 (0x7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000007 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV9 (0x8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000008 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV10 (0x9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000009 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV11 (0xAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV12 (0xBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV13 (0xCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV14 (0xDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV15 (0xEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV16 (0xFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV17 (0x10U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000010 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV18 (0x11U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000011 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV19 (0x12U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000012 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV20 (0x13U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000013 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV21 (0x14U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000014 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV22 (0x15U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000015 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV23 (0x16U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000016 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV24 (0x17U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000017 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV25 (0x18U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000018 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV26 (0x19U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000019 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV27 (0x1AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV28 (0x1BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV29 (0x1CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV30 (0x1DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV31 (0x1EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV32 (0x1FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV33 (0x20U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000020 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV34 (0x21U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000021 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV35 (0x22U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000022 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV36 (0x23U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000023 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV37 (0x24U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000024 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV38 (0x25U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000025 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV39 (0x26U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000026 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV40 (0x27U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000027 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV41 (0x28U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000028 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV42 (0x29U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000029 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV43 (0x2AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV44 (0x2BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV45 (0x2CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV46 (0x2DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV47 (0x2EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV48 (0x2FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV49 (0x30U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000030 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV50 (0x31U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000031 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV51 (0x32U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000032 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV52 (0x33U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000033 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV53 (0x34U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000034 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV54 (0x35U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000035 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV55 (0x36U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000036 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV56 (0x37U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000037 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV57 (0x38U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000038 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV58 (0x39U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000039 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV59 (0x3AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV60 (0x3BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV61 (0x3CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV62 (0x3DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV63 (0x3EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV64 (0x3FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV65 (0x40U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000040 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV66 (0x41U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000041 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV67 (0x42U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000042 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV68 (0x43U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000043 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV69 (0x44U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000044 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV70 (0x45U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000045 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV71 (0x46U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000046 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV72 (0x47U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000047 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV73 (0x48U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000048 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV74 (0x49U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000049 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV75 (0x4AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV76 (0x4BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV77 (0x4CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV78 (0x4DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV79 (0x4EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV80 (0x4FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV81 (0x50U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000050 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV82 (0x51U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000051 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV83 (0x52U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000052 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV84 (0x53U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000053 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV85 (0x54U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000054 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV86 (0x55U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000055 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV87 (0x56U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000056 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV88 (0x57U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000057 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV89 (0x58U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000058 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV90 (0x59U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000059 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV91 (0x5AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV92 (0x5BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV93 (0x5CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV94 (0x5DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV95 (0x5EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV96 (0x5FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV97 (0x60U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000060 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV98 (0x61U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000061 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV99 (0x62U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000062 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV100 (0x63U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000063 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV101 (0x64U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000064 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV102 (0x65U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000065 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV103 (0x66U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000066 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV104 (0x67U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000067 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV105 (0x68U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000068 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV106 (0x69U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000069 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV107 (0x6AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV108 (0x6BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV109 (0x6CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV110 (0x6DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV111 (0x6EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV112 (0x6FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV113 (0x70U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000070 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV114 (0x71U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000071 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV115 (0x72U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000072 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV116 (0x73U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000073 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV117 (0x74U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000074 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV118 (0x75U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000075 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV119 (0x76U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000076 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV120 (0x77U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000077 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV121 (0x78U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000078 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV122 (0x79U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000079 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV123 (0x7AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV124 (0x7BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV125 (0x7CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV126 (0x7DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV127 (0x7EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV128 (0x7FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV129 (0x80U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000080 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV130 (0x81U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000081 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV131 (0x82U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000082 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV132 (0x83U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000083 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV133 (0x84U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000084 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV134 (0x85U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000085 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV135 (0x86U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000086 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV136 (0x87U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000087 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV137 (0x88U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000088 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV138 (0x89U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000089 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV139 (0x8AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV140 (0x8BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV141 (0x8CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV142 (0x8DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV143 (0x8EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV144 (0x8FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV145 (0x90U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000090 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV146 (0x91U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000091 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV147 (0x92U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000092 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV148 (0x93U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000093 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV149 (0x94U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000094 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV150 (0x95U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000095 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV151 (0x96U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000096 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV152 (0x97U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000097 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV153 (0x98U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000098 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV154 (0x99U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000099 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV155 (0x9AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV156 (0x9BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV157 (0x9CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV158 (0x9DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV159 (0x9EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV160 (0x9FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV161 (0xA0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV162 (0xA1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV163 (0xA2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV164 (0xA3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV165 (0xA4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV166 (0xA5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV167 (0xA6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV168 (0xA7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV169 (0xA8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV170 (0xA9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV171 (0xAAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV172 (0xABU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV173 (0xACU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV174 (0xADU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV175 (0xAEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV176 (0xAFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV177 (0xB0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV178 (0xB1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV179 (0xB2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV180 (0xB3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV181 (0xB4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV182 (0xB5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV183 (0xB6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV184 (0xB7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV185 (0xB8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV186 (0xB9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV187 (0xBAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV188 (0xBBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV189 (0xBCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV190 (0xBDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV191 (0xBEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV192 (0xBFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV193 (0xC0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV194 (0xC1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV195 (0xC2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV196 (0xC3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV197 (0xC4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV198 (0xC5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV199 (0xC6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV200 (0xC7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV201 (0xC8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV202 (0xC9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV203 (0xCAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV204 (0xCBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV205 (0xCCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV206 (0xCDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV207 (0xCEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV208 (0xCFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV209 (0xD0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV210 (0xD1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV211 (0xD2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV212 (0xD3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV213 (0xD4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV214 (0xD5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV215 (0xD6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV216 (0xD7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV217 (0xD8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV218 (0xD9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV219 (0xDAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV220 (0xDBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV221 (0xDCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV222 (0xDDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV223 (0xDEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV224 (0xDFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV225 (0xE0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV226 (0xE1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV227 (0xE2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV228 (0xE3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV229 (0xE4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV230 (0xE5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV231 (0xE6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV232 (0xE7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV233 (0xE8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV234 (0xE9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV235 (0xEAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV236 (0xEBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV237 (0xECU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV238 (0xEDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000ED */ +#define MISC2_CLKDIVH_CLKDIVH_DIV239 (0xEEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV240 (0xEFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV241 (0xF0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV242 (0xF1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV243 (0xF2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV244 (0xF3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV245 (0xF4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV246 (0xF5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV247 (0xF6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV248 (0xF7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV249 (0xF8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV250 (0xF9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV251 (0xFAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV252 (0xFBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV253 (0xFCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV254 (0xFDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV255 (0xFEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV256 (0xFFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FF */ + +/************** Bits definition for MISC2_CLKDIVP register ******************/ +#define MISC2_CLKDIVP_CLKDIVP_Pos (0U) +#define MISC2_CLKDIVP_CLKDIVP_Msk (0xFFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FF */ +#define MISC2_CLKDIVP_CLKDIVP MISC2_CLKDIVP_CLKDIVP_Msk /*!< This register is used to control APB clock divider */ +#define MISC2_CLKDIVP_CLKDIVP_DIV1 (0x0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000000 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV2 (0x1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000001 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV3 (0x2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000002 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV4 (0x3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000003 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV5 (0x4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000004 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV6 (0x5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000005 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV7 (0x6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000006 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV8 (0x7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000007 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV9 (0x8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000008 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV10 (0x9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000009 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV11 (0xAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV12 (0xBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV13 (0xCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV14 (0xDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV15 (0xEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV16 (0xFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV17 (0x10U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000010 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV18 (0x11U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000011 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV19 (0x12U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000012 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV20 (0x13U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000013 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV21 (0x14U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000014 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV22 (0x15U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000015 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV23 (0x16U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000016 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV24 (0x17U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000017 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV25 (0x18U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000018 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV26 (0x19U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000019 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV27 (0x1AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV28 (0x1BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV29 (0x1CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV30 (0x1DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV31 (0x1EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV32 (0x1FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV33 (0x20U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000020 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV34 (0x21U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000021 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV35 (0x22U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000022 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV36 (0x23U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000023 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV37 (0x24U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000024 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV38 (0x25U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000025 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV39 (0x26U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000026 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV40 (0x27U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000027 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV41 (0x28U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000028 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV42 (0x29U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000029 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV43 (0x2AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV44 (0x2BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV45 (0x2CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV46 (0x2DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV47 (0x2EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV48 (0x2FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV49 (0x30U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000030 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV50 (0x31U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000031 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV51 (0x32U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000032 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV52 (0x33U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000033 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV53 (0x34U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000034 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV54 (0x35U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000035 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV55 (0x36U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000036 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV56 (0x37U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000037 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV57 (0x38U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000038 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV58 (0x39U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000039 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV59 (0x3AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV60 (0x3BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV61 (0x3CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV62 (0x3DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV63 (0x3EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV64 (0x3FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV65 (0x40U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000040 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV66 (0x41U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000041 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV67 (0x42U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000042 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV68 (0x43U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000043 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV69 (0x44U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000044 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV70 (0x45U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000045 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV71 (0x46U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000046 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV72 (0x47U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000047 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV73 (0x48U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000048 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV74 (0x49U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000049 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV75 (0x4AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV76 (0x4BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV77 (0x4CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV78 (0x4DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV79 (0x4EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV80 (0x4FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV81 (0x50U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000050 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV82 (0x51U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000051 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV83 (0x52U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000052 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV84 (0x53U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000053 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV85 (0x54U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000054 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV86 (0x55U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000055 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV87 (0x56U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000056 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV88 (0x57U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000057 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV89 (0x58U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000058 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV90 (0x59U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000059 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV91 (0x5AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV92 (0x5BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV93 (0x5CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV94 (0x5DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV95 (0x5EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV96 (0x5FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV97 (0x60U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000060 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV98 (0x61U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000061 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV99 (0x62U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000062 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV100 (0x63U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000063 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV101 (0x64U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000064 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV102 (0x65U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000065 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV103 (0x66U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000066 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV104 (0x67U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000067 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV105 (0x68U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000068 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV106 (0x69U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000069 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV107 (0x6AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV108 (0x6BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV109 (0x6CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV110 (0x6DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV111 (0x6EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV112 (0x6FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV113 (0x70U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000070 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV114 (0x71U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000071 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV115 (0x72U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000072 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV116 (0x73U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000073 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV117 (0x74U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000074 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV118 (0x75U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000075 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV119 (0x76U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000076 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV120 (0x77U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000077 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV121 (0x78U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000078 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV122 (0x79U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000079 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV123 (0x7AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV124 (0x7BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV125 (0x7CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV126 (0x7DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV127 (0x7EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV128 (0x7FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV129 (0x80U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000080 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV130 (0x81U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000081 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV131 (0x82U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000082 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV132 (0x83U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000083 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV133 (0x84U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000084 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV134 (0x85U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000085 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV135 (0x86U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000086 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV136 (0x87U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000087 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV137 (0x88U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000088 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV138 (0x89U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000089 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV139 (0x8AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV140 (0x8BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV141 (0x8CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV142 (0x8DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV143 (0x8EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV144 (0x8FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV145 (0x90U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000090 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV146 (0x91U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000091 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV147 (0x92U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000092 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV148 (0x93U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000093 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV149 (0x94U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000094 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV150 (0x95U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000095 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV151 (0x96U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000096 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV152 (0x97U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000097 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV153 (0x98U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000098 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV154 (0x99U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000099 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV155 (0x9AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV156 (0x9BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV157 (0x9CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV158 (0x9DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV159 (0x9EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV160 (0x9FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV161 (0xA0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV162 (0xA1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV163 (0xA2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV164 (0xA3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV165 (0xA4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV166 (0xA5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV167 (0xA6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV168 (0xA7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV169 (0xA8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV170 (0xA9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV171 (0xAAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV172 (0xABU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV173 (0xACU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV174 (0xADU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV175 (0xAEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV176 (0xAFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV177 (0xB0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV178 (0xB1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV179 (0xB2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV180 (0xB3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV181 (0xB4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV182 (0xB5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV183 (0xB6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV184 (0xB7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV185 (0xB8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV186 (0xB9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV187 (0xBAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV188 (0xBBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV189 (0xBCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV190 (0xBDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV191 (0xBEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV192 (0xBFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV193 (0xC0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV194 (0xC1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV195 (0xC2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV196 (0xC3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV197 (0xC4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV198 (0xC5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV199 (0xC6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV200 (0xC7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV201 (0xC8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV202 (0xC9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV203 (0xCAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV204 (0xCBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV205 (0xCCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV206 (0xCDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV207 (0xCEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV208 (0xCFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV209 (0xD0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV210 (0xD1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV211 (0xD2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV212 (0xD3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV213 (0xD4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV214 (0xD5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV215 (0xD6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV216 (0xD7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV217 (0xD8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV218 (0xD9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV219 (0xDAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV220 (0xDBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV221 (0xDCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV222 (0xDDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV223 (0xDEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV224 (0xDFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV225 (0xE0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV226 (0xE1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV227 (0xE2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV228 (0xE3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV229 (0xE4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV230 (0xE5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV231 (0xE6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV232 (0xE7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV233 (0xE8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV234 (0xE9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV235 (0xEAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV236 (0xEBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV237 (0xECU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV238 (0xEDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000ED */ +#define MISC2_CLKDIVP_CLKDIVP_DIV239 (0xEEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV240 (0xEFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV241 (0xF0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV242 (0xF1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV243 (0xF2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV244 (0xF3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV245 (0xF4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV246 (0xF5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV247 (0xF6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV248 (0xF7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV249 (0xF8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV250 (0xF9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV251 (0xFAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV252 (0xFBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV253 (0xFCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV254 (0xFDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV255 (0xFEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV256 (0xFFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FF */ + +/************** Bits definition for MISC2_HCLKEN register ******************/ +//#define MISC2_HCLKEN_HCLKEN_Pos (0U) +//#define MISC2_HCLKEN_HCLKEN_Msk (0x1FFU << MISC2_HCLKEN_HCLKEN_Pos) /*!< 0x000001FF */ +//#define MISC2_HCLKEN_HCLKEN MISC2_HCLKEN_HCLKEN_Msk /*!< This register is used to control clock enable of each AHB module */ +//#define MISC2_HCLKEN_ARB_Pos (1U) +//#define MISC2_HCLKEN_ARB_Msk (0x1U << MISC2_HCLKEN_ARB_Pos) /*!< 0x00000002 */ +//#define MISC2_HCLKEN_ARB MISC2_HCLKEN_ARB_Msk /*!< Arbiter & Bus Matrix */ +//#define MISC2_HCLKEN_FLASH_Pos (2U) +//#define MISC2_HCLKEN_FLASH_Msk (0x1U << MISC2_HCLKEN_FLASH_Pos) /*!< 0x00000004 */ +//#define MISC2_HCLKEN_FLASH MISC2_HCLKEN_FLASH_Msk /*!< Flash Controller */ +//#define MISC2_HCLKEN_SRAM_Pos (3U) +//#define MISC2_HCLKEN_SRAM_Msk (0x1U << MISC2_HCLKEN_SRAM_Pos) /*!< 0x00000008 */ +//#define MISC2_HCLKEN_SRAM MISC2_HCLKEN_SRAM_Msk /*!< SRAM Controller */ +#define MISC2_HCLKEN_DMA_Pos (4U) +#define MISC2_HCLKEN_DMA_Msk (0x1U << MISC2_HCLKEN_DMA_Pos) /*!< 0x00000010 */ +#define MISC2_HCLKEN_DMA MISC2_HCLKEN_DMA_Msk /*!< DMA Controller */ +#define MISC2_HCLKEN_GPIO_Pos (5U) +#define MISC2_HCLKEN_GPIO_Msk (0x1U << MISC2_HCLKEN_GPIO_Pos) /*!< 0x00000020 */ +#define MISC2_HCLKEN_GPIO MISC2_HCLKEN_GPIO_Msk /*!< GPIO Controller */ +#define MISC2_HCLKEN_LCD_Pos (6U) +#define MISC2_HCLKEN_LCD_Msk (0x1U << MISC2_HCLKEN_LCD_Pos) /*!< 0x00000040 */ +#define MISC2_HCLKEN_LCD MISC2_HCLKEN_LCD_Msk /*!< LCD Controller */ +#define MISC2_HCLKEN_CRYPT_Pos (8U) +#define MISC2_HCLKEN_CRYPT_Msk (0x1U << MISC2_HCLKEN_CRYPT_Pos) /*!< 0x00000100 */ +#define MISC2_HCLKEN_CRYPT MISC2_HCLKEN_CRYPT_Msk /*!< CRYPT Controller */ + +/************** Bits definition for MISC2_PCLKEN register ******************/ +//#define MISC2_PCLKEN_PCLKEN_Pos (0U) +//#define MISC2_PCLKEN_PCLKEN_Msk (0x002FFFFFU << MISC2_PCLKEN_PCLKEN_Pos) /*!< 0x002FFFFF */ +//#define MISC2_PCLKEN_PCLKEN MISC2_PCLKEN_PCLKEN_Msk /*!< This register is used to control clock enable of each APB module */ +//#define MISC2_PCLKEN_AHB2APB_Pos (0U) +//#define MISC2_PCLKEN_AHB2APB_Msk (0x1U << MISC2_PCLKEN_AHB2APB_Pos) /*!< 0x00000001 */ +//#define MISC2_PCLKEN_AHB2APB MISC2_PCLKEN_AHB2APB_Msk /*!< AHB2APB Bridge */ +#define MISC2_PCLKEN_DMA_Pos (1U) +#define MISC2_PCLKEN_DMA_Msk (0x1U << MISC2_PCLKEN_DMA_Pos) /*!< 0x00000002 */ +#define MISC2_PCLKEN_DMA MISC2_PCLKEN_DMA_Msk /*!< DMA Controller */ +#define MISC2_PCLKEN_I2C_Pos (2U) +#define MISC2_PCLKEN_I2C_Msk (0x1U << MISC2_PCLKEN_I2C_Pos) /*!< 0x00000004 */ +#define MISC2_PCLKEN_I2C MISC2_PCLKEN_I2C_Msk /*!< I2C */ +#define MISC2_PCLKEN_SPI1_Pos (3U) +#define MISC2_PCLKEN_SPI1_Msk (0x1U << MISC2_PCLKEN_SPI1_Pos) /*!< 0x00000008 */ +#define MISC2_PCLKEN_SPI1 MISC2_PCLKEN_SPI1_Msk /*!< SPI1 */ +#define MISC2_PCLKEN_UART0_Pos (4U) +#define MISC2_PCLKEN_UART0_Msk (0x1U << MISC2_PCLKEN_UART0_Pos) /*!< 0x00000010 */ +#define MISC2_PCLKEN_UART0 MISC2_PCLKEN_UART0_Msk /*!< UART0 */ +#define MISC2_PCLKEN_UART1_Pos (5U) +#define MISC2_PCLKEN_UART1_Msk (0x1U << MISC2_PCLKEN_UART1_Pos) /*!< 0x00000020 */ +#define MISC2_PCLKEN_UART1 MISC2_PCLKEN_UART1_Msk /*!< UART1 */ +#define MISC2_PCLKEN_UART2_Pos (6U) +#define MISC2_PCLKEN_UART2_Msk (0x1U << MISC2_PCLKEN_UART2_Pos) /*!< 0x00000040 */ +#define MISC2_PCLKEN_UART2 MISC2_PCLKEN_UART2_Msk /*!< UART2 */ +#define MISC2_PCLKEN_UART3_Pos (7U) +#define MISC2_PCLKEN_UART3_Msk (0x1U << MISC2_PCLKEN_UART3_Pos) /*!< 0x00000080 */ +#define MISC2_PCLKEN_UART3 MISC2_PCLKEN_UART3_Msk /*!< UART3 */ +#define MISC2_PCLKEN_UART4_Pos (8U) +#define MISC2_PCLKEN_UART4_Msk (0x1U << MISC2_PCLKEN_UART4_Pos) /*!< 0x00000100 */ +#define MISC2_PCLKEN_UART4 MISC2_PCLKEN_UART4_Msk /*!< UART4 */ +#define MISC2_PCLKEN_UART5_Pos (9U) +#define MISC2_PCLKEN_UART5_Msk (0x1U << MISC2_PCLKEN_UART5_Pos) /*!< 0x00000200 */ +#define MISC2_PCLKEN_UART5 MISC2_PCLKEN_UART5_Msk /*!< UART5 */ +#define MISC2_PCLKEN_ISO78160_Pos (10U) +#define MISC2_PCLKEN_ISO78160_Msk (0x1U << MISC2_PCLKEN_ISO78160_Pos) /*!< 0x00000400 */ +#define MISC2_PCLKEN_ISO78160 MISC2_PCLKEN_ISO78160_Msk /*!< ISO78160 */ +#define MISC2_PCLKEN_ISO78161_Pos (11U) +#define MISC2_PCLKEN_ISO78161_Msk (0x1U << MISC2_PCLKEN_ISO78161_Pos) /*!< 0x00000800 */ +#define MISC2_PCLKEN_ISO78161 MISC2_PCLKEN_ISO78161_Msk /*!< ISO78161 */ +#define MISC2_PCLKEN_TIMER_Pos (12U) +#define MISC2_PCLKEN_TIMER_Msk (0x1U << MISC2_PCLKEN_TIMER_Pos) /*!< 0x00001000 */ +#define MISC2_PCLKEN_TIMER MISC2_PCLKEN_TIMER_Msk /*!< Timer */ +#define MISC2_PCLKEN_MISC_Pos (13U) +#define MISC2_PCLKEN_MISC_Msk (0x1U << MISC2_PCLKEN_MISC_Pos) /*!< 0x00002000 */ +#define MISC2_PCLKEN_MISC MISC2_PCLKEN_MISC_Msk /*!< MISC */ +#define MISC2_PCLKEN_MISC2_Pos (14U) +#define MISC2_PCLKEN_MISC2_Msk (0x1U << MISC2_PCLKEN_MISC2_Pos) /*!< 0x00004000 */ +#define MISC2_PCLKEN_MISC2 MISC2_PCLKEN_MISC2_Msk /*!< LCD & MISC2 */ +#define MISC2_PCLKEN_PMU_Pos (15U) +#define MISC2_PCLKEN_PMU_Msk (0x1U << MISC2_PCLKEN_PMU_Pos) /*!< 0x00008000 */ +#define MISC2_PCLKEN_PMU MISC2_PCLKEN_PMU_Msk /*!< PMU */ +#define MISC2_PCLKEN_RTC_Pos (16U) +#define MISC2_PCLKEN_RTC_Msk (0x1U << MISC2_PCLKEN_RTC_Pos) /*!< 0x00010000 */ +#define MISC2_PCLKEN_RTC MISC2_PCLKEN_RTC_Msk /*!< RTC */ +#define MISC2_PCLKEN_ANA_Pos (17U) +#define MISC2_PCLKEN_ANA_Msk (0x1U << MISC2_PCLKEN_ANA_Pos) /*!< 0x00020000 */ +#define MISC2_PCLKEN_ANA MISC2_PCLKEN_ANA_Msk /*!< ANA */ +#define MISC2_PCLKEN_U32K0_Pos (18U) +#define MISC2_PCLKEN_U32K0_Msk (0x1U << MISC2_PCLKEN_U32K0_Pos) /*!< 0x00040000 */ +#define MISC2_PCLKEN_U32K0 MISC2_PCLKEN_U32K0_Msk /*!< U32K 0 */ +#define MISC2_PCLKEN_U32K1_Pos (19U) +#define MISC2_PCLKEN_U32K1_Msk (0x1U << MISC2_PCLKEN_U32K1_Pos) /*!< 0x00080000 */ +#define MISC2_PCLKEN_U32K1 MISC2_PCLKEN_U32K1_Msk /*!< U32K 1 */ +#define MISC2_PCLKEN_SPI2_Pos (21U) +#define MISC2_PCLKEN_SPI2_Msk (0x1U << MISC2_PCLKEN_SPI2_Pos) /*!< 0x00200000 */ +#define MISC2_PCLKEN_SPI2 MISC2_PCLKEN_SPI2_Msk /*!< SPI2 */ + +/******************************************************************************/ +/* */ +/* CRYPT controller (CRYPT) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for CRYPT_CTRL register ******************/ +#define CRYPT_CTRL_ACT_Pos (0U) +#define CRYPT_CTRL_ACT_Msk (0x1U << CRYPT_CTRL_ACT_Pos) /*!< 0x00000001 */ +#define CRYPT_CTRL_ACT CRYPT_CTRL_ACT_Msk /*!< Write 1 to this bit will start an operation specified in the MODE register */ +#define CRYPT_CTRL_MODE_Pos (4U) +#define CRYPT_CTRL_MODE_Msk (0x7U << CRYPT_CTRL_MODE_Pos) /*!< 0x00000070 */ +#define CRYPT_CTRL_MODE CRYPT_CTRL_MODE_Msk /*!< This register controls the operation mode of crypt engine */ +#define CRYPT_CTRL_MODE_MULTIPLY (0x0U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_MODE_ADD (0x1U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_MODE_SUB (0x2U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_MODE_RSHIFT1 (0x3U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_LENGTH_Pos (8U) +#define CRYPT_CTRL_LENGTH_Msk (0xFU << CRYPT_CTRL_LENGTH_Pos) /*!< 0x00000F00 */ +#define CRYPT_CTRL_LENGTH CRYPT_CTRL_LENGTH_Msk /*!< This bit is used to control the VLI length of current operation */ +#define CRYPT_CTRL_LENGTH_32 (0x0U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_64 (0x1U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_96 (0x2U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_128 (0x3U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_160 (0x4U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_192 (0x5U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_224 (0x6U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_256 (0x7U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_288 (0x8U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_320 (0x9U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_352 (0xAU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_384 (0xBU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_416 (0xCU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_448 (0xDU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_480 (0xEU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_512 (0xFU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_NOSTOP_Pos (15U) +#define CRYPT_CTRL_NOSTOP_Msk (0x1U << CRYPT_CTRL_NOSTOP_Pos) /*!< 0x00008000 */ +#define CRYPT_CTRL_NOSTOP CRYPT_CTRL_NOSTOP_Msk /*!< This register is used to control if the CPU will be stop by CRYPT engine when the CRYPT engine is busy and CPU read or write CRYPT engine register */ + +/************** Bits definition for CRYPT_PTRA register ******************/ +#define CRYPT_PTRA_PTRA_Pos (0U) +#define CRYPT_PTRA_PTRA_Msk (0x7FFFU << CRYPT_PTRA_PTRA_Pos) /*!< 0x00007FFF */ +#define CRYPT_PTRA_PTRA CRYPT_PTRA_PTRA_Msk /*!< This is the PTRA register of CRYPT controller */ + +/************** Bits definition for CRYPT_PTRB register ******************/ +#define CRYPT_PTRB_PTRB_Pos (0U) +#define CRYPT_PTRB_PTRB_Msk (0x7FFFU << CRYPT_PTRB_PTRB_Pos) /*!< 0x00007FFF */ +#define CRYPT_PTRB_PTRB CRYPT_PTRB_PTRB_Msk /*!< This is the PTRB register of CRYPT controller */ + +/************** Bits definition for CRYPT_PTRO register ******************/ +#define CRYPT_PTRO_PTRO_Pos (0U) +#define CRYPT_PTRO_PTRO_Msk (0x7FFFU << CRYPT_PTRO_PTRO_Pos) /*!< 0x00007FFF */ +#define CRYPT_PTRO_PTRO CRYPT_PTRO_PTRO_Msk /*!< This is the PTRO register of CRYPT controller */ + +/************* Bits definition for CRYPT_CARRY register ******************/ +#define CRYPT_CARRY_CARRY_Pos (0U) +#define CRYPT_CARRY_CARRY_Msk (0x1U << CRYPT_CARRY_CARRY_Pos) /*!< 0x00000001 */ +#define CRYPT_CARRY_CARRY CRYPT_CARRY_CARRY_Msk /*!< This bit represent the carry bit after add operation is done */ + + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Power Management Unit (PMU) */ +/* */ +/******************************************************************************/ +#define PMU_DSLEEPEN (volatile unsigned *)(PMU_BASE + 0x0000) +#define PMU_DSLEEPPASS (volatile unsigned *)(PMU_BASE + 0x0004) +#define PMU_CONTROL (volatile unsigned *)(PMU_BASE + 0x0008) +#define PMU_STS (volatile unsigned *)(PMU_BASE + 0x000C) +#define PMU_IOAOEN (volatile unsigned *)(PMU_BASE + 0x0010) +#define PMU_IOAIE (volatile unsigned *)(PMU_BASE + 0x0014) +#define PMU_IOADAT (volatile unsigned *)(PMU_BASE + 0x0018) +#define PMU_IOAATT (volatile unsigned *)(PMU_BASE + 0x001C) +#define PMU_IOAWKUEN (volatile unsigned *)(PMU_BASE + 0x0020) +#define PMU_IOASTS (volatile unsigned *)(PMU_BASE + 0x0024) +#define PMU_IOAINTSTS (volatile unsigned *)(PMU_BASE + 0x0028) +#define PMU_IOASEL (volatile unsigned *)(PMU_BASE + 0x0038) +#define VERSIONID (volatile unsigned *)(PMU_BASE + 0x003C) +#define PMU_WDTPASS (volatile unsigned *)(PMU_BASE + 0x0040) +#define PMU_WDTEN (volatile unsigned *)(PMU_BASE + 0x0044) +#define PMU_WDTCLR (volatile unsigned *)(PMU_BASE + 0x0048) +//#define PMU_WDTSTS (volatile unsigned *)(PMU_BASE + 0x004C) +#define PMU_IOANODEG (volatile unsigned *)(PMU_BASE + 0x0050) + +#define PMU_RAM0 (volatile unsigned *)(RETRAM_BASE + 0x0000) +#define PMU_RAM1 (volatile unsigned *)(RETRAM_BASE + 0x0004) +#define PMU_RAM2 (volatile unsigned *)(RETRAM_BASE + 0x0008) +#define PMU_RAM3 (volatile unsigned *)(RETRAM_BASE + 0x000C) +#define PMU_RAM4 (volatile unsigned *)(RETRAM_BASE + 0x0010) +#define PMU_RAM5 (volatile unsigned *)(RETRAM_BASE + 0x0014) +#define PMU_RAM6 (volatile unsigned *)(RETRAM_BASE + 0x0018) +#define PMU_RAM7 (volatile unsigned *)(RETRAM_BASE + 0x001C) +#define PMU_RAM8 (volatile unsigned *)(RETRAM_BASE + 0x0020) +#define PMU_RAM9 (volatile unsigned *)(RETRAM_BASE + 0x0024) +#define PMU_RAM10 (volatile unsigned *)(RETRAM_BASE + 0x0028) +#define PMU_RAM11 (volatile unsigned *)(RETRAM_BASE + 0x002C) +#define PMU_RAM12 (volatile unsigned *)(RETRAM_BASE + 0x0030) +#define PMU_RAM13 (volatile unsigned *)(RETRAM_BASE + 0x0034) +#define PMU_RAM14 (volatile unsigned *)(RETRAM_BASE + 0x0038) +#define PMU_RAM15 (volatile unsigned *)(RETRAM_BASE + 0x003C) +#define PMU_RAM16 (volatile unsigned *)(RETRAM_BASE + 0x0040) +#define PMU_RAM17 (volatile unsigned *)(RETRAM_BASE + 0x0044) +#define PMU_RAM18 (volatile unsigned *)(RETRAM_BASE + 0x0048) +#define PMU_RAM19 (volatile unsigned *)(RETRAM_BASE + 0x004C) +#define PMU_RAM20 (volatile unsigned *)(RETRAM_BASE + 0x0050) +#define PMU_RAM21 (volatile unsigned *)(RETRAM_BASE + 0x0054) +#define PMU_RAM22 (volatile unsigned *)(RETRAM_BASE + 0x0058) +#define PMU_RAM23 (volatile unsigned *)(RETRAM_BASE + 0x005C) +#define PMU_RAM24 (volatile unsigned *)(RETRAM_BASE + 0x0060) +#define PMU_RAM25 (volatile unsigned *)(RETRAM_BASE + 0x0064) +#define PMU_RAM26 (volatile unsigned *)(RETRAM_BASE + 0x0068) +#define PMU_RAM27 (volatile unsigned *)(RETRAM_BASE + 0x006C) +#define PMU_RAM28 (volatile unsigned *)(RETRAM_BASE + 0x0070) +#define PMU_RAM29 (volatile unsigned *)(RETRAM_BASE + 0x0074) +#define PMU_RAM30 (volatile unsigned *)(RETRAM_BASE + 0x0078) +#define PMU_RAM31 (volatile unsigned *)(RETRAM_BASE + 0x007C) +#define PMU_RAM32 (volatile unsigned *)(RETRAM_BASE + 0x0080) +#define PMU_RAM33 (volatile unsigned *)(RETRAM_BASE + 0x0084) +#define PMU_RAM34 (volatile unsigned *)(RETRAM_BASE + 0x0088) +#define PMU_RAM35 (volatile unsigned *)(RETRAM_BASE + 0x008C) +#define PMU_RAM36 (volatile unsigned *)(RETRAM_BASE + 0x0090) +#define PMU_RAM37 (volatile unsigned *)(RETRAM_BASE + 0x0094) +#define PMU_RAM38 (volatile unsigned *)(RETRAM_BASE + 0x0098) +#define PMU_RAM39 (volatile unsigned *)(RETRAM_BASE + 0x009C) +#define PMU_RAM40 (volatile unsigned *)(RETRAM_BASE + 0x00A0) +#define PMU_RAM41 (volatile unsigned *)(RETRAM_BASE + 0x00A4) +#define PMU_RAM42 (volatile unsigned *)(RETRAM_BASE + 0x00A8) +#define PMU_RAM43 (volatile unsigned *)(RETRAM_BASE + 0x00AC) +#define PMU_RAM44 (volatile unsigned *)(RETRAM_BASE + 0x00B0) +#define PMU_RAM45 (volatile unsigned *)(RETRAM_BASE + 0x00B4) +#define PMU_RAM46 (volatile unsigned *)(RETRAM_BASE + 0x00B8) +#define PMU_RAM47 (volatile unsigned *)(RETRAM_BASE + 0x00BC) +#define PMU_RAM48 (volatile unsigned *)(RETRAM_BASE + 0x00C0) +#define PMU_RAM49 (volatile unsigned *)(RETRAM_BASE + 0x00C4) +#define PMU_RAM50 (volatile unsigned *)(RETRAM_BASE + 0x00C8) +#define PMU_RAM51 (volatile unsigned *)(RETRAM_BASE + 0x00CC) +#define PMU_RAM52 (volatile unsigned *)(RETRAM_BASE + 0x00D0) +#define PMU_RAM53 (volatile unsigned *)(RETRAM_BASE + 0x00D4) +#define PMU_RAM54 (volatile unsigned *)(RETRAM_BASE + 0x00D8) +#define PMU_RAM55 (volatile unsigned *)(RETRAM_BASE + 0x00DC) +#define PMU_RAM56 (volatile unsigned *)(RETRAM_BASE + 0x00E0) +#define PMU_RAM57 (volatile unsigned *)(RETRAM_BASE + 0x00E4) +#define PMU_RAM58 (volatile unsigned *)(RETRAM_BASE + 0x00E8) +#define PMU_RAM59 (volatile unsigned *)(RETRAM_BASE + 0x00EC) +#define PMU_RAM60 (volatile unsigned *)(RETRAM_BASE + 0x00F0) +#define PMU_RAM61 (volatile unsigned *)(RETRAM_BASE + 0x00F4) +#define PMU_RAM62 (volatile unsigned *)(RETRAM_BASE + 0x00F8) +#define PMU_RAM63 (volatile unsigned *)(RETRAM_BASE + 0x00FC) + +/******************************************************************************/ +/* */ +/* Analog Controller (ANA) */ +/* */ +/******************************************************************************/ +#define ANA_REG0 (volatile unsigned *)(ANA_BASE + 0x0000) +#define ANA_REG1 (volatile unsigned *)(ANA_BASE + 0x0004) +#define ANA_REG2 (volatile unsigned *)(ANA_BASE + 0x0008) +#define ANA_REG3 (volatile unsigned *)(ANA_BASE + 0x000C) +#define ANA_REG4 (volatile unsigned *)(ANA_BASE + 0x0010) +#define ANA_REG5 (volatile unsigned *)(ANA_BASE + 0x0014) +#define ANA_REG6 (volatile unsigned *)(ANA_BASE + 0x0018) +#define ANA_REG7 (volatile unsigned *)(ANA_BASE + 0x001C) +#define ANA_REG8 (volatile unsigned *)(ANA_BASE + 0x0020) +#define ANA_REG9 (volatile unsigned *)(ANA_BASE + 0x0024) +#define ANA_REGA (volatile unsigned *)(ANA_BASE + 0x0028) +#define ANA_REGB (volatile unsigned *)(ANA_BASE + 0x002C) +#define ANA_REGC (volatile unsigned *)(ANA_BASE + 0x0030) +#define ANA_REGD (volatile unsigned *)(ANA_BASE + 0x0034) +#define ANA_REGE (volatile unsigned *)(ANA_BASE + 0x0038) +#define ANA_REGF (volatile unsigned *)(ANA_BASE + 0x003C) +//#define ANA_REG10 (volatile unsigned *)(ANA_BASE + 0x0040) +//#define ANA_REG11 (volatile unsigned *)(ANA_BASE + 0x0044) +//#define ANA_REG12 (volatile unsigned *)(ANA_BASE + 0x0048) +#define ANA_CTRL (volatile unsigned *)(ANA_BASE + 0x0050) +#define ANA_CMPOUT (volatile unsigned *)(ANA_BASE + 0x0054) +//#define ANA_VERSION (volatile unsigned *)(ANA_BASE + 0x0058) +//#define ANA_ADCSTATE (volatile unsigned *)(ANA_BASE + 0x005C) +#define ANA_INTSTS (volatile unsigned *)(ANA_BASE + 0x0060) +#define ANA_INTEN (volatile unsigned *)(ANA_BASE + 0x0064) +#define ANA_ADCCTRL (volatile unsigned *)(ANA_BASE + 0x0068) +#define ANA_ADCDATA0 (volatile unsigned *)(ANA_BASE + 0x0070) +#define ANA_ADCDATA1 (volatile unsigned *)(ANA_BASE + 0x0074) +#define ANA_ADCDATA2 (volatile unsigned *)(ANA_BASE + 0x0078) +#define ANA_ADCDATA3 (volatile unsigned *)(ANA_BASE + 0x007C) +#define ANA_ADCDATA4 (volatile unsigned *)(ANA_BASE + 0x0080) +#define ANA_ADCDATA5 (volatile unsigned *)(ANA_BASE + 0x0084) +#define ANA_ADCDATA6 (volatile unsigned *)(ANA_BASE + 0x0088) +#define ANA_ADCDATA7 (volatile unsigned *)(ANA_BASE + 0x008C) +#define ANA_ADCDATA8 (volatile unsigned *)(ANA_BASE + 0x0090) +#define ANA_ADCDATA9 (volatile unsigned *)(ANA_BASE + 0x0094) +#define ANA_ADCDATAA (volatile unsigned *)(ANA_BASE + 0x0098) +#define ANA_ADCDATAB (volatile unsigned *)(ANA_BASE + 0x009C) +//#define ANA_ADCDATAC (volatile unsigned *)(ANA_BASE + 0x00A0) +//#define ANA_ADCDATAD (volatile unsigned *)(ANA_BASE + 0x00A4) +//#define ANA_ADCDATAE (volatile unsigned *)(ANA_BASE + 0x00A8) +//#define ANA_ADCDATAF (volatile unsigned *)(ANA_BASE + 0x00AC) +#define ANA_CMPCNT1 (volatile unsigned *)(ANA_BASE + 0x00B0) +#define ANA_CMPCNT2 (volatile unsigned *)(ANA_BASE + 0x00B4) +#define ANA_MISC (volatile unsigned *)(ANA_BASE + 0x00B8) + +/******************************************************************************/ +/* */ +/* RTC Controller (RTC) */ +/* */ +/******************************************************************************/ +#define RTC_SEC (volatile unsigned *)(RTC_BASE + 0x0000) +#define RTC_MIN (volatile unsigned *)(RTC_BASE + 0x0004) +#define RTC_HOUR (volatile unsigned *)(RTC_BASE + 0x0008) +#define RTC_DAY (volatile unsigned *)(RTC_BASE + 0x000C) +#define RTC_WEEK (volatile unsigned *)(RTC_BASE + 0x0010) +#define RTC_MON (volatile unsigned *)(RTC_BASE + 0x0014) +#define RTC_YEAR (volatile unsigned *)(RTC_BASE + 0x0018) +#define RTC_WKUSEC (volatile unsigned *)(RTC_BASE + 0x0020) +#define RTC_WKUMIN (volatile unsigned *)(RTC_BASE + 0x0024) +#define RTC_WKUHOUR (volatile unsigned *)(RTC_BASE + 0x0028) +#define RTC_WKUCNT (volatile unsigned *)(RTC_BASE + 0x002C) +#define RTC_CAL (volatile unsigned *)(RTC_BASE + 0x0030) +#define RTC_DIV (volatile unsigned *)(RTC_BASE + 0x0034) +#define RTC_CTL (volatile unsigned *)(RTC_BASE + 0x0038) +//#define RTC_ITV (volatile unsigned *)(RTC_BASE + 0x003C) +//#define RTC_SITV (volatile unsigned *)(RTC_BASE + 0x0040) +#define RTC_PWD (volatile unsigned *)(RTC_BASE + 0x0044) +#define RTC_CE (volatile unsigned *)(RTC_BASE + 0x0048) +#define RTC_LOAD (volatile unsigned *)(RTC_BASE + 0x004C) +#define RTC_INTSTS (volatile unsigned *)(RTC_BASE + 0x0050) +#define RTC_INTEN (volatile unsigned *)(RTC_BASE + 0x0054) +#define RTC_PSCA (volatile unsigned *)(RTC_BASE + 0x0058) +#define RTC_ACCTRL (volatile unsigned *)(RTC_BASE + 0x0080) +#define RTC_ACTI (volatile unsigned *)(RTC_BASE + 0x0084) +#define RTC_ACF200 (volatile unsigned *)(RTC_BASE + 0x0088) +#define RTC_ACADCW (volatile unsigned *)(RTC_BASE + 0x008C) +#define RTC_ACP0 (volatile unsigned *)(RTC_BASE + 0x0090) +#define RTC_ACP1 (volatile unsigned *)(RTC_BASE + 0x0094) +#define RTC_ACP2 (volatile unsigned *)(RTC_BASE + 0x0098) +#define RTC_ACP3 (volatile unsigned *)(RTC_BASE + 0x009C) +#define RTC_ACP4 (volatile unsigned *)(RTC_BASE + 0x00A0) +#define RTC_ACP5 (volatile unsigned *)(RTC_BASE + 0x00A4) +#define RTC_ACP6 (volatile unsigned *)(RTC_BASE + 0x00A8) +#define RTC_ACP7 (volatile unsigned *)(RTC_BASE + 0x00AC) +#define RTC_ACK1 (volatile unsigned *)(RTC_BASE + 0x00B0) +#define RTC_ACK2 (volatile unsigned *)(RTC_BASE + 0x00B4) +#define RTC_ACK3 (volatile unsigned *)(RTC_BASE + 0x00B8) +#define RTC_ACK4 (volatile unsigned *)(RTC_BASE + 0x00BC) +#define RTC_ACK5 (volatile unsigned *)(RTC_BASE + 0x00C0) +#define RTC_ACTEMP (volatile unsigned *)(RTC_BASE + 0x00C4) +#define RTC_ACPPM (volatile unsigned *)(RTC_BASE + 0x00C8) +#define RTC_ACADCR (volatile unsigned *)(RTC_BASE + 0x00CC) +#define RTC_ACOP0 (volatile unsigned *)(RTC_BASE + 0x0400) +#define RTC_ACOP1 (volatile unsigned *)(RTC_BASE + 0x0404) +#define RTC_ACOP2 (volatile unsigned *)(RTC_BASE + 0x0408) +#define RTC_ACOP3 (volatile unsigned *)(RTC_BASE + 0x040C) +#define RTC_ACOP4 (volatile unsigned *)(RTC_BASE + 0x0410) +#define RTC_ACOP5 (volatile unsigned *)(RTC_BASE + 0x0414) +#define RTC_ACOP6 (volatile unsigned *)(RTC_BASE + 0x0418) +#define RTC_ACOP7 (volatile unsigned *)(RTC_BASE + 0x041C) +#define RTC_ACOP8 (volatile unsigned *)(RTC_BASE + 0x0420) +#define RTC_ACOP9 (volatile unsigned *)(RTC_BASE + 0x0424) +#define RTC_ACOP10 (volatile unsigned *)(RTC_BASE + 0x0428) +#define RTC_ACOP11 (volatile unsigned *)(RTC_BASE + 0x042C) +#define RTC_ACOP12 (volatile unsigned *)(RTC_BASE + 0x0430) +#define RTC_ACOP13 (volatile unsigned *)(RTC_BASE + 0x0434) +#define RTC_ACOP14 (volatile unsigned *)(RTC_BASE + 0x0438) +#define RTC_ACOP15 (volatile unsigned *)(RTC_BASE + 0x043C) +#define RTC_ACOP16 (volatile unsigned *)(RTC_BASE + 0x0440) +#define RTC_ACOP17 (volatile unsigned *)(RTC_BASE + 0x0444) +#define RTC_ACOP18 (volatile unsigned *)(RTC_BASE + 0x0448) +#define RTC_ACOP19 (volatile unsigned *)(RTC_BASE + 0x044C) +#define RTC_ACOP20 (volatile unsigned *)(RTC_BASE + 0x0450) +#define RTC_ACOP21 (volatile unsigned *)(RTC_BASE + 0x0454) +#define RTC_ACOP22 (volatile unsigned *)(RTC_BASE + 0x0458) +#define RTC_ACOP23 (volatile unsigned *)(RTC_BASE + 0x045C) +#define RTC_ACOP24 (volatile unsigned *)(RTC_BASE + 0x0460) +#define RTC_ACOP25 (volatile unsigned *)(RTC_BASE + 0x0464) +#define RTC_ACOP26 (volatile unsigned *)(RTC_BASE + 0x0468) +#define RTC_ACOP27 (volatile unsigned *)(RTC_BASE + 0x046C) +#define RTC_ACOP28 (volatile unsigned *)(RTC_BASE + 0x0470) +#define RTC_ACOP29 (volatile unsigned *)(RTC_BASE + 0x0474) +#define RTC_ACOP30 (volatile unsigned *)(RTC_BASE + 0x0478) +#define RTC_ACOP31 (volatile unsigned *)(RTC_BASE + 0x047C) +#define RTC_ACOP32 (volatile unsigned *)(RTC_BASE + 0x0480) +#define RTC_ACOP33 (volatile unsigned *)(RTC_BASE + 0x0484) +#define RTC_ACOP34 (volatile unsigned *)(RTC_BASE + 0x0488) +#define RTC_ACOP35 (volatile unsigned *)(RTC_BASE + 0x048C) +#define RTC_ACOP36 (volatile unsigned *)(RTC_BASE + 0x0490) +#define RTC_ACOP37 (volatile unsigned *)(RTC_BASE + 0x0494) +#define RTC_ACOP38 (volatile unsigned *)(RTC_BASE + 0x0498) +#define RTC_ACOP39 (volatile unsigned *)(RTC_BASE + 0x049C) +#define RTC_ACOP40 (volatile unsigned *)(RTC_BASE + 0x04A0) +#define RTC_ACOP41 (volatile unsigned *)(RTC_BASE + 0x04A4) +#define RTC_ACOP42 (volatile unsigned *)(RTC_BASE + 0x04A8) +#define RTC_ACOP43 (volatile unsigned *)(RTC_BASE + 0x04AC) +#define RTC_ACOP44 (volatile unsigned *)(RTC_BASE + 0x04B0) +#define RTC_ACOP45 (volatile unsigned *)(RTC_BASE + 0x04B4) +#define RTC_ACOP46 (volatile unsigned *)(RTC_BASE + 0x04B8) +#define RTC_ACOP47 (volatile unsigned *)(RTC_BASE + 0x04BC) +#define RTC_ACOP48 (volatile unsigned *)(RTC_BASE + 0x04C0) +#define RTC_ACOP49 (volatile unsigned *)(RTC_BASE + 0x04C4) +#define RTC_ACOP50 (volatile unsigned *)(RTC_BASE + 0x04C8) +#define RTC_ACOP51 (volatile unsigned *)(RTC_BASE + 0x04CC) +#define RTC_ACOP52 (volatile unsigned *)(RTC_BASE + 0x04D0) +#define RTC_ACOP53 (volatile unsigned *)(RTC_BASE + 0x04D4) +#define RTC_ACOP54 (volatile unsigned *)(RTC_BASE + 0x04D8) +#define RTC_ACOP55 (volatile unsigned *)(RTC_BASE + 0x04DC) +#define RTC_ACOP56 (volatile unsigned *)(RTC_BASE + 0x04E0) +#define RTC_ACOP57 (volatile unsigned *)(RTC_BASE + 0x04E4) +#define RTC_ACOP58 (volatile unsigned *)(RTC_BASE + 0x04E8) +#define RTC_ACOP59 (volatile unsigned *)(RTC_BASE + 0x04EC) +#define RTC_ACOP60 (volatile unsigned *)(RTC_BASE + 0x04F0) +#define RTC_ACOP61 (volatile unsigned *)(RTC_BASE + 0x04F4) +#define RTC_ACOP62 (volatile unsigned *)(RTC_BASE + 0x04F8) +#define RTC_ACOP63 (volatile unsigned *)(RTC_BASE + 0x04FC) + +/******************************************************************************/ +/* */ +/* Flash Controller (Flash) */ +/* */ +/******************************************************************************/ +#define FLASH_STA (volatile unsigned *) (FLASH_BASE + 0xFFFBC) +#define FLASH_INT (volatile unsigned *) (FLASH_BASE + 0x000FFFCC) +#define FLASH_CSSADDR (volatile unsigned *) (FLASH_BASE + 0x000FFFD0) +#define FLASH_CSEADDR (volatile unsigned *) (FLASH_BASE + 0x000FFFD4) +#define FLASH_CSVALUE (volatile unsigned *) (FLASH_BASE + 0x000FFFD8) +#define FLASH_CSCVALUE (volatile unsigned *) (FLASH_BASE + 0x000FFFDC) +#define FLASH_PASS (volatile unsigned *) (FLASH_BASE + 0x000FFFE0) +#define FLASH_CTRL (volatile unsigned *) (FLASH_BASE + 0x000FFFE4) +#define FLASH_PGADDR (volatile unsigned *) (FLASH_BASE + 0x000FFFE8) +#define FLASH_PGDATA (volatile unsigned *) (FLASH_BASE + 0x000FFFEC) +#define FLASH_PGB0 (volatile unsigned char*) (FLASH_BASE + 0x000FFFEC) +#define FLASH_PGB1 (volatile unsigned char*) (FLASH_BASE + 0x000FFFED) +#define FLASH_PGB2 (volatile unsigned char*) (FLASH_BASE + 0x000FFFEE) +#define FLASH_PGB3 (volatile unsigned char*) (FLASH_BASE + 0x000FFFEF) +#define FLASH_PGHW0 (volatile unsigned short*)(FLASH_BASE + 0x000FFFEC) +#define FLASH_PGHW1 (volatile unsigned short*)(FLASH_BASE + 0x000FFFEE) +#define FLASH_CONF (volatile unsigned *) (FLASH_BASE + 0x000FFFF0) +#define FLASH_SERASE (volatile unsigned *) (FLASH_BASE + 0x000FFFF4) +#define FLASH_CERASE (volatile unsigned *) (FLASH_BASE + 0x000FFFF8) +#define FLASH_DSTB (volatile unsigned *) (FLASH_BASE + 0x000FFFFC) + +#define FLASH_NVRPASS (volatile unsigned *) (FLASH_BASE + 0xFFFC0) +#define FLASH_BDPASS (volatile unsigned *) (FLASH_BASE + 0xFFFC4) +#define FLASH_KEY (volatile unsigned *) (FLASH_BASE + 0xFFFC8) + +/******************************************************************************/ +/* */ +/* GPIO Controller (GPIO) */ +/* */ +/******************************************************************************/ +#define IOB_OEN (volatile unsigned *)(GPIO_BASE + 0x00000020) +#define IOB_IE (volatile unsigned *)(GPIO_BASE + 0x00000024) +#define IOB_DAT (volatile unsigned *)(GPIO_BASE + 0x00000028) +#define IOB_ATT (volatile unsigned *)(GPIO_BASE + 0x0000002C) +#define IOB_STS (volatile unsigned *)(GPIO_BASE + 0x00000030) +#define IOC_OEN (volatile unsigned *)(GPIO_BASE + 0x00000040) +#define IOC_IE (volatile unsigned *)(GPIO_BASE + 0x00000044) +#define IOC_DAT (volatile unsigned *)(GPIO_BASE + 0x00000048) +#define IOC_ATT (volatile unsigned *)(GPIO_BASE + 0x0000004C) +#define IOC_STS (volatile unsigned *)(GPIO_BASE + 0x00000050) +#define IOD_OEN (volatile unsigned *)(GPIO_BASE + 0x00000060) +#define IOD_IE (volatile unsigned *)(GPIO_BASE + 0x00000064) +#define IOD_DAT (volatile unsigned *)(GPIO_BASE + 0x00000068) +#define IOD_ATT (volatile unsigned *)(GPIO_BASE + 0x0000006C) +#define IOD_STS (volatile unsigned *)(GPIO_BASE + 0x00000070) +#define IOE_OEN (volatile unsigned *)(GPIO_BASE + 0x00000080) +#define IOE_IE (volatile unsigned *)(GPIO_BASE + 0x00000084) +#define IOE_DAT (volatile unsigned *)(GPIO_BASE + 0x00000088) +#define IOE_ATT (volatile unsigned *)(GPIO_BASE + 0x0000008C) +#define IOE_STS (volatile unsigned *)(GPIO_BASE + 0x00000090) +#define IOF_OEN (volatile unsigned *)(GPIO_BASE + 0x000000A0) +#define IOF_IE (volatile unsigned *)(GPIO_BASE + 0x000000A4) +#define IOF_DAT (volatile unsigned *)(GPIO_BASE + 0x000000A8) +#define IOF_ATT (volatile unsigned *)(GPIO_BASE + 0x000000AC) +#define IOF_STS (volatile unsigned *)(GPIO_BASE + 0x000000B0) +#define IOB_SEL (volatile unsigned *)(GPIO_BASE + 0x000000C0) +#define IOE_SEL (volatile unsigned *)(GPIO_BASE + 0x000000CC) +#define IO_MISC (volatile unsigned *)(GPIO_BASE + 0x000000E0) + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ +#define DMA_IE (volatile unsigned *)(DMA_BASE + 0x0000) +#define DMA_STS (volatile unsigned *)(DMA_BASE + 0x0004) +#define DMA_C0CTL (volatile unsigned *)(DMA_BASE + 0x0010) +#define DMA_C0SRC (volatile unsigned *)(DMA_BASE + 0x0014) +#define DMA_C0DST (volatile unsigned *)(DMA_BASE + 0x0018) +#define DMA_C0LEN (volatile unsigned *)(DMA_BASE + 0x001C) +#define DMA_C1CTL (volatile unsigned *)(DMA_BASE + 0x0020) +#define DMA_C1SRC (volatile unsigned *)(DMA_BASE + 0x0024) +#define DMA_C1DST (volatile unsigned *)(DMA_BASE + 0x0028) +#define DMA_C1LEN (volatile unsigned *)(DMA_BASE + 0x002C) +#define DMA_C2CTL (volatile unsigned *)(DMA_BASE + 0x0030) +#define DMA_C2SRC (volatile unsigned *)(DMA_BASE + 0x0034) +#define DMA_C2DST (volatile unsigned *)(DMA_BASE + 0x0038) +#define DMA_C2LEN (volatile unsigned *)(DMA_BASE + 0x003C) +#define DMA_C3CTL (volatile unsigned *)(DMA_BASE + 0x0040) +#define DMA_C3SRC (volatile unsigned *)(DMA_BASE + 0x0044) +#define DMA_C3DST (volatile unsigned *)(DMA_BASE + 0x0048) +#define DMA_C3LEN (volatile unsigned *)(DMA_BASE + 0x004C) +#define DMA_AESCTL (volatile unsigned *)(DMA_BASE + 0x0050) +#define DMA_AESKEY0 (volatile unsigned *)(DMA_BASE + 0x0060) +#define DMA_AESKEY1 (volatile unsigned *)(DMA_BASE + 0x0064) +#define DMA_AESKEY2 (volatile unsigned *)(DMA_BASE + 0x0068) +#define DMA_AESKEY3 (volatile unsigned *)(DMA_BASE + 0x006C) +#define DMA_AESKEY4 (volatile unsigned *)(DMA_BASE + 0x0070) +#define DMA_AESKEY5 (volatile unsigned *)(DMA_BASE + 0x0074) +#define DMA_AESKEY6 (volatile unsigned *)(DMA_BASE + 0x0078) +#define DMA_AESKEY7 (volatile unsigned *)(DMA_BASE + 0x007C) + +/******************************************************************************/ +/* */ +/* UART Controller (UART) */ +/* */ +/******************************************************************************/ +#define UART0_DATA (volatile unsigned *)(UART0_BASE + 0x0000) +#define UART0_STATE (volatile unsigned *)(UART0_BASE + 0x0004) +#define UART0_CTRL (volatile unsigned *)(UART0_BASE + 0x0008) +#define UART0_INTSTS (volatile unsigned *)(UART0_BASE + 0x000C) +#define UART0_BAUDDIV (volatile unsigned *)(UART0_BASE + 0x0010) +#define UART0_CTRL2 (volatile unsigned *)(UART0_BASE + 0x0014) +#define UART1_DATA (volatile unsigned *)(UART1_BASE + 0x0000) +#define UART1_STATE (volatile unsigned *)(UART1_BASE + 0x0004) +#define UART1_CTRL (volatile unsigned *)(UART1_BASE + 0x0008) +#define UART1_INTSTS (volatile unsigned *)(UART1_BASE + 0x000C) +#define UART1_BAUDDIV (volatile unsigned *)(UART1_BASE + 0x0010) +#define UART1_CTRL2 (volatile unsigned *)(UART1_BASE + 0x0014) +#define UART2_DATA (volatile unsigned *)(UART2_BASE + 0x0000) +#define UART2_STATE (volatile unsigned *)(UART2_BASE + 0x0004) +#define UART2_CTRL (volatile unsigned *)(UART2_BASE + 0x0008) +#define UART2_INTSTS (volatile unsigned *)(UART2_BASE + 0x000C) +#define UART2_BAUDDIV (volatile unsigned *)(UART2_BASE + 0x0010) +#define UART2_CTRL2 (volatile unsigned *)(UART2_BASE + 0x0014) +#define UART3_DATA (volatile unsigned *)(UART3_BASE + 0x0000) +#define UART3_STATE (volatile unsigned *)(UART3_BASE + 0x0004) +#define UART3_CTRL (volatile unsigned *)(UART3_BASE + 0x0008) +#define UART3_INTSTS (volatile unsigned *)(UART3_BASE + 0x000C) +#define UART3_BAUDDIV (volatile unsigned *)(UART3_BASE + 0x0010) +#define UART3_CTRL2 (volatile unsigned *)(UART3_BASE + 0x0014) +#define UART4_DATA (volatile unsigned *)(UART4_BASE + 0x0000) +#define UART4_STATE (volatile unsigned *)(UART4_BASE + 0x0004) +#define UART4_CTRL (volatile unsigned *)(UART4_BASE + 0x0008) +#define UART4_INTSTS (volatile unsigned *)(UART4_BASE + 0x000C) +#define UART4_BAUDDIV (volatile unsigned *)(UART4_BASE + 0x0010) +#define UART4_CTRL2 (volatile unsigned *)(UART4_BASE + 0x0014) +#define UART5_DATA (volatile unsigned *)(UART5_BASE + 0x0000) +#define UART5_STATE (volatile unsigned *)(UART5_BASE + 0x0004) +#define UART5_CTRL (volatile unsigned *)(UART5_BASE + 0x0008) +#define UART5_INTSTS (volatile unsigned *)(UART5_BASE + 0x000C) +#define UART5_BAUDDIV (volatile unsigned *)(UART5_BASE + 0x0010) +#define UART5_CTRL2 (volatile unsigned *)(UART5_BASE + 0x0014) + +/******************************************************************************/ +/* */ +/* UART 32K Controller (U32K) */ +/* */ +/******************************************************************************/ +#define U32K0_CTRL0 (volatile unsigned *)(U32K0_BASE + 0x0000) +#define U32K0_CTRL1 (volatile unsigned *)(U32K0_BASE + 0x0004) +#define U32K0_PHASE (volatile unsigned *)(U32K0_BASE + 0x0008) +#define U32K0_DATA (volatile unsigned *)(U32K0_BASE + 0x000C) +#define U32K0_STS (volatile unsigned *)(U32K0_BASE + 0x0010) + +#define U32K1_CTRL0 (volatile unsigned *)(U32K1_BASE + 0x0000) +#define U32K1_CTRL1 (volatile unsigned *)(U32K1_BASE + 0x0004) +#define U32K1_PHASE (volatile unsigned *)(U32K1_BASE + 0x0008) +#define U32K1_DATA (volatile unsigned *)(U32K1_BASE + 0x000C) +#define U32K1_STS (volatile unsigned *)(U32K1_BASE + 0x0010) + +/******************************************************************************/ +/* */ +/* ISO7816 Controller (ISO7816) */ +/* */ +/******************************************************************************/ +#define ISO78160_BAUDDIVL (volatile unsigned *)(ISO78160_BASE + 0x0004) +#define ISO78160_BAUDDIVH (volatile unsigned *)(ISO78160_BASE + 0x0008) +#define ISO78160_DATA (volatile unsigned *)(ISO78160_BASE + 0x000C) +#define ISO78160_INFO (volatile unsigned *)(ISO78160_BASE + 0x0010) +#define ISO78160_CFG (volatile unsigned *)(ISO78160_BASE + 0x0014) +#define ISO78160_CLK (volatile unsigned *)(ISO78160_BASE + 0x0018) +#define ISO78161_BAUDDIVL (volatile unsigned *)(ISO78161_BASE + 0x0004) +#define ISO78161_BAUDDIVH (volatile unsigned *)(ISO78161_BASE + 0x0008) +#define ISO78161_DATA (volatile unsigned *)(ISO78161_BASE + 0x000C) +#define ISO78161_INFO (volatile unsigned *)(ISO78161_BASE + 0x0010) +#define ISO78161_CFG (volatile unsigned *)(ISO78161_BASE + 0x0014) +#define ISO78161_CLK (volatile unsigned *)(ISO78161_BASE + 0x0018) + +/******************************************************************************/ +/* */ +/* Timer Controller (Timer) */ +/* */ +/******************************************************************************/ +#define TMR0_CTRL (volatile unsigned *)(TMR0_BASE + 0x0000) +#define TMR0_VALUE (volatile unsigned *)(TMR0_BASE + 0x0004) +#define TMR0_RELOAD (volatile unsigned *)(TMR0_BASE + 0x0008) +#define TMR0_INT (volatile unsigned *)(TMR0_BASE + 0x000C) +#define TMR1_CTRL (volatile unsigned *)(TMR1_BASE + 0x0000) +#define TMR1_VALUE (volatile unsigned *)(TMR1_BASE + 0x0004) +#define TMR1_RELOAD (volatile unsigned *)(TMR1_BASE + 0x0008) +#define TMR1_INT (volatile unsigned *)(TMR1_BASE + 0x000C) +#define TMR2_CTRL (volatile unsigned *)(TMR2_BASE + 0x0000) +#define TMR2_VALUE (volatile unsigned *)(TMR2_BASE + 0x0004) +#define TMR2_RELOAD (volatile unsigned *)(TMR2_BASE + 0x0008) +#define TMR2_INT (volatile unsigned *)(TMR2_BASE + 0x000C) +#define TMR3_CTRL (volatile unsigned *)(TMR3_BASE + 0x0000) +#define TMR3_VALUE (volatile unsigned *)(TMR3_BASE + 0x0004) +#define TMR3_RELOAD (volatile unsigned *)(TMR3_BASE + 0x0008) +#define TMR3_INT (volatile unsigned *)(TMR3_BASE + 0x000C) + +/******************************************************************************/ +/* */ +/* PWM Controller (PWM) */ +/* */ +/******************************************************************************/ +#define PWM0_CTL (volatile unsigned *)(PWM0_BASE + 0x0000) +#define PWM0_TAR (volatile unsigned *)(PWM0_BASE + 0x0004) +#define PWM0_CCTL0 (volatile unsigned *)(PWM0_BASE + 0x0008) +#define PWM0_CCTL1 (volatile unsigned *)(PWM0_BASE + 0x000C) +#define PWM0_CCTL2 (volatile unsigned *)(PWM0_BASE + 0x0010) +#define PWM0_CCR0 (volatile unsigned *)(PWM0_BASE + 0x0014) +#define PWM0_CCR1 (volatile unsigned *)(PWM0_BASE + 0x0018) +#define PWM0_CCR2 (volatile unsigned *)(PWM0_BASE + 0x001C) +#define PWM1_CTL (volatile unsigned *)(PWM1_BASE + 0x0000) +#define PWM1_TAR (volatile unsigned *)(PWM1_BASE + 0x0004) +#define PWM1_CCTL0 (volatile unsigned *)(PWM1_BASE + 0x0008) +#define PWM1_CCTL1 (volatile unsigned *)(PWM1_BASE + 0x000C) +#define PWM1_CCTL2 (volatile unsigned *)(PWM1_BASE + 0x0010) +#define PWM1_CCR0 (volatile unsigned *)(PWM1_BASE + 0x0014) +#define PWM1_CCR1 (volatile unsigned *)(PWM1_BASE + 0x0018) +#define PWM1_CCR2 (volatile unsigned *)(PWM1_BASE + 0x001C) +#define PWM2_CTL (volatile unsigned *)(PWM2_BASE + 0x0000) +#define PWM2_TAR (volatile unsigned *)(PWM2_BASE + 0x0004) +#define PWM2_CCTL0 (volatile unsigned *)(PWM2_BASE + 0x0008) +#define PWM2_CCTL1 (volatile unsigned *)(PWM2_BASE + 0x000C) +#define PWM2_CCTL2 (volatile unsigned *)(PWM2_BASE + 0x0010) +#define PWM2_CCR0 (volatile unsigned *)(PWM2_BASE + 0x0014) +#define PWM2_CCR1 (volatile unsigned *)(PWM2_BASE + 0x0018) +#define PWM2_CCR2 (volatile unsigned *)(PWM2_BASE + 0x001C) +#define PWM3_CTL (volatile unsigned *)(PWM3_BASE + 0x0000) +#define PWM3_TAR (volatile unsigned *)(PWM3_BASE + 0x0004) +#define PWM3_CCTL0 (volatile unsigned *)(PWM3_BASE + 0x0008) +#define PWM3_CCTL1 (volatile unsigned *)(PWM3_BASE + 0x000C) +#define PWM3_CCTL2 (volatile unsigned *)(PWM3_BASE + 0x0010) +#define PWM3_CCR0 (volatile unsigned *)(PWM3_BASE + 0x0014) +#define PWM3_CCR1 (volatile unsigned *)(PWM3_BASE + 0x0018) +#define PWM3_CCR2 (volatile unsigned *)(PWM3_BASE + 0x001C) +#define PWM_O_SEL (volatile unsigned *)(PWM0_BASE + 0x00F0) +//#define PWM_I_SEL01 (volatile unsigned *)(PWM0_BASE + 0x00F4) +//#define PWM_I_SEL23 (volatile unsigned *)(PWM0_BASE + 0x00F8) + +/******************************************************************************/ +/* */ +/* LCD Controller (LCD) */ +/* */ +/******************************************************************************/ +#define LCD_FB00 (volatile unsigned *)(LCD_BASE + 0x0000) +#define LCD_FB01 (volatile unsigned *)(LCD_BASE + 0x0004) +#define LCD_FB02 (volatile unsigned *)(LCD_BASE + 0x0008) +#define LCD_FB03 (volatile unsigned *)(LCD_BASE + 0x000C) +#define LCD_FB04 (volatile unsigned *)(LCD_BASE + 0x0010) +#define LCD_FB05 (volatile unsigned *)(LCD_BASE + 0x0014) +#define LCD_FB06 (volatile unsigned *)(LCD_BASE + 0x0018) +#define LCD_FB07 (volatile unsigned *)(LCD_BASE + 0x001C) +#define LCD_FB08 (volatile unsigned *)(LCD_BASE + 0x0020) +#define LCD_FB09 (volatile unsigned *)(LCD_BASE + 0x0024) +#define LCD_FB0A (volatile unsigned *)(LCD_BASE + 0x0028) +#define LCD_FB0B (volatile unsigned *)(LCD_BASE + 0x002C) +#define LCD_FB0C (volatile unsigned *)(LCD_BASE + 0x0030) +#define LCD_FB0D (volatile unsigned *)(LCD_BASE + 0x0034) +#define LCD_FB0E (volatile unsigned *)(LCD_BASE + 0x0038) +#define LCD_FB0F (volatile unsigned *)(LCD_BASE + 0x003C) +#define LCD_FB10 (volatile unsigned *)(LCD_BASE + 0x0040) +#define LCD_FB11 (volatile unsigned *)(LCD_BASE + 0x0044) +#define LCD_FB12 (volatile unsigned *)(LCD_BASE + 0x0048) +#define LCD_FB13 (volatile unsigned *)(LCD_BASE + 0x004C) +#define LCD_FB14 (volatile unsigned *)(LCD_BASE + 0x0050) +#define LCD_FB15 (volatile unsigned *)(LCD_BASE + 0x0054) +#define LCD_FB16 (volatile unsigned *)(LCD_BASE + 0x0058) +#define LCD_FB17 (volatile unsigned *)(LCD_BASE + 0x005C) +#define LCD_FB18 (volatile unsigned *)(LCD_BASE + 0x0060) +#define LCD_FB19 (volatile unsigned *)(LCD_BASE + 0x0064) +#define LCD_FB1A (volatile unsigned *)(LCD_BASE + 0x0068) +#define LCD_FB1B (volatile unsigned *)(LCD_BASE + 0x006C) +#define LCD_FB1C (volatile unsigned *)(LCD_BASE + 0x0070) +#define LCD_FB1D (volatile unsigned *)(LCD_BASE + 0x0074) +#define LCD_FB1E (volatile unsigned *)(LCD_BASE + 0x0078) +#define LCD_FB1F (volatile unsigned *)(LCD_BASE + 0x007C) +#define LCD_FB20 (volatile unsigned *)(LCD_BASE + 0x0080) +#define LCD_FB21 (volatile unsigned *)(LCD_BASE + 0x0084) +#define LCD_FB22 (volatile unsigned *)(LCD_BASE + 0x0088) +#define LCD_FB23 (volatile unsigned *)(LCD_BASE + 0x008C) +#define LCD_FB24 (volatile unsigned *)(LCD_BASE + 0x0090) +#define LCD_FB25 (volatile unsigned *)(LCD_BASE + 0x0094) +#define LCD_FB26 (volatile unsigned *)(LCD_BASE + 0x0098) +#define LCD_FB27 (volatile unsigned *)(LCD_BASE + 0x009C) +#define LCD_CTRL (volatile unsigned *)(LCD_BASE + 0x0100) +#define LCD_CTRL2 (volatile unsigned *)(LCD_BASE + 0x0104) +#define LCD_SEGCTRL0 (volatile unsigned *)(LCD_BASE + 0x0108) +#define LCD_SEGCTRL1 (volatile unsigned *)(LCD_BASE + 0x010C) +#define LCD_SEGCTRL2 (volatile unsigned *)(LCD_BASE + 0x0110) + +/******************************************************************************/ +/* */ +/* SPI Controller (SPI) */ +/* */ +/******************************************************************************/ +#define SPI1_CTRL (volatile unsigned *)(SPI1_BASE + 0x0000) +#define SPI1_TXSTS (volatile unsigned *)(SPI1_BASE + 0x0004) +#define SPI1_TXDATA (volatile unsigned *)(SPI1_BASE + 0x0008) +#define SPI1_RXSTS (volatile unsigned *)(SPI1_BASE + 0x000C) +#define SPI1_RXDATA (volatile unsigned *)(SPI1_BASE + 0x0010) +#define SPI1_MISC (volatile unsigned *)(SPI1_BASE + 0x0014) +#define SPI2_CTRL (volatile unsigned *)(SPI2_BASE + 0x0000) +#define SPI2_TXSTS (volatile unsigned *)(SPI2_BASE + 0x0004) +#define SPI2_TXDATA (volatile unsigned *)(SPI2_BASE + 0x0008) +#define SPI2_RXSTS (volatile unsigned *)(SPI2_BASE + 0x000C) +#define SPI2_RXDATA (volatile unsigned *)(SPI2_BASE + 0x0010) +#define SPI2_MISC (volatile unsigned *)(SPI2_BASE + 0x0014) + +/******************************************************************************/ +/* */ +/* I2C Controller (I2C) */ +/* */ +/******************************************************************************/ +#define I2C_DATA (volatile unsigned *)(I2C_BASE + 0x0000) +#define I2C_ADDR (volatile unsigned *)(I2C_BASE + 0x0004) +#define I2C_CTRL (volatile unsigned *)(I2C_BASE + 0x0008) +#define I2C_STS (volatile unsigned *)(I2C_BASE + 0x000C) +#define I2C_SMBSEL (volatile unsigned *)(I2C_BASE + 0x0010) +#define I2C_SMBDST (volatile unsigned *)(I2C_BASE + 0x0014) +#define I2C_CTRL2 (volatile unsigned *)(I2C_BASE + 0x0018) + +/******************************************************************************/ +/* */ +/* MISC Controller (MISC) */ +/* */ +/******************************************************************************/ +#define MISC_SRAMINT (volatile unsigned *)(MISC_BASE + 0x0000) +#define MISC_SRAMINIT (volatile unsigned *)(MISC_BASE + 0x0004) +#define MISC_PARERR (volatile unsigned *)(MISC_BASE + 0x0008) +#define MISC_IREN (volatile unsigned *)(MISC_BASE + 0x000C) +#define MISC_DUTYL (volatile unsigned *)(MISC_BASE + 0x0010) +#define MISC_DUTYH (volatile unsigned *)(MISC_BASE + 0x0014) +#define MISC_IRQLAT (volatile unsigned *)(MISC_BASE + 0x0018) + +#define MISC2_FLASHWC (volatile unsigned *)(MISC2_BASE + 0x0000) +#define MISC2_CLKSEL (volatile unsigned *)(MISC2_BASE + 0x0004) +#define MISC2_CLKDIVH (volatile unsigned *)(MISC2_BASE + 0x0008) +#define MISC2_CLKDIVP (volatile unsigned *)(MISC2_BASE + 0x000C) +#define MISC2_HCLKEN (volatile unsigned *)(MISC2_BASE + 0x0010) +#define MISC2_PCLKEN (volatile unsigned *)(MISC2_BASE + 0x0014) + +/******************************************************************************/ +/* */ +/* CRYPT Controller (CRYPT) */ +/* */ +/******************************************************************************/ +#define CRYPT_CTRL (volatile unsigned *)(CRYPT_BASE + 0x0000) +#define CRYPT_PTRA (volatile unsigned *)(CRYPT_BASE + 0x0004) +#define CRYPT_PTRB (volatile unsigned *)(CRYPT_BASE + 0x0008) +#define CRYPT_PTRO (volatile unsigned *)(CRYPT_BASE + 0x000C) +#define CRYPT_CARRY (volatile unsigned *)(CRYPT_BASE + 0x0010) + +/** @addtogroup Exported_macro + * @{ + */ + +/****************************** PMU Instances *********************************/ +#define IS_PMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU) + +/****************************** PMU_RETRAM Instances **************************/ +#define IS_PMU_RETRAM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU_RETRAM) + +/****************************** ANA Instances *********************************/ +#define IS_ANA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ANA) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) + +/****************************** FLASH Instances *******************************/ +#define IS_FLASH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FLASH) + +/****************************** GPIO Instances ********************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOE) || \ + ((INSTANCE) == GPIOF)) + +#define IS_PMUIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPIOA) + +#define IS_GPIOAF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOE)) + +/****************************** DMA Instances *********************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA) + +/****************************** UART Instances ********************************/ +#define IS_UART_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UART0) || \ + ((INSTANCE) == UART1) || \ + ((INSTANCE) == UART2) || \ + ((INSTANCE) == UART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5)) + +/****************************** U32K Instances ********************************/ +#define IS_U32K_ALL_INSTANCE(INSTANCE) (((INSTANCE) == U32K0) || \ + ((INSTANCE) == U32K1)) + +/****************************** ISO7816 Instances *****************************/ +#define IS_ISO7816_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ISO78160) || \ + ((INSTANCE) == ISO78161)) + +/****************************** TMR Instances *********************************/ +#define IS_TMR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TMR0) || \ + ((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3)) + +/****************************** PWM Instances *********************************/ +#define IS_PWM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PWM0) || \ + ((INSTANCE) == PWM1) || \ + ((INSTANCE) == PWM2) || \ + ((INSTANCE) == PWM3)) + +#define IS_PWMMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PWMMUX) + +/****************************** LCD Instances *********************************/ +#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD) + +/****************************** SPI Instances *********************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/****************************** I2C Instances *********************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C) + +/****************************** MISC Instances ********************************/ +#define IS_MISC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC) + +#define IS_MISC2_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC2) + +/****************************** CRYPT Instances *******************************/ +#define IS_CRYPT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRYPT) + + + +#ifdef USE_TARGET_DRIVER + #include "lib_conf.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h new file mode 100644 index 0000000000..913c171790 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file type_def.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Typedef file + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __TYPE_DEF_H +#define __TYPE_DEF_H + +#define ENABLE 1 +#define DISABLE 0 +#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE)) + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__GNUC__) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#endif /* __TYPE_DEF_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/system_target.c b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/system_target.c new file mode 100644 index 0000000000..d8dcc96787 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/system_target.c @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file system_target.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief system source file. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "target.h" + +#define NVR_REGINFOCOUNT1 (0x80400) +#define NVR_REGINFOBAKOFFSET (0x100) + +/** + * @brief Setup the microcontroller system + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + uint32_t i,nCount,nValue,nAddress,nChecksum; + + nCount = *(__IO uint32_t *)NVR_REGINFOCOUNT1; + nChecksum = nCount; + nChecksum = ~nChecksum; + if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+4)) + { + nCount = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET); + nChecksum = nCount; + nChecksum = ~nChecksum; + if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+4)) + { + while(1); + } + } + + for(i=0; i=0x40014800) && (nAddress<=0x40015000)) + { + RTC_WriteRegisters(nAddress, &nValue, 1); + } + else + { + *(__IO uint32_t *)(nAddress) = nValue; + } + } +} + +/** + * @brief Initializes registers. + * @param None + * @retval None + */ +void SystemUpdate(void) +{ + +} + + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_compiler.h b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_compiler.h new file mode 100644 index 0000000000..94212eb87a --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_gcc.h b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_gcc.h new file mode 100644 index 0000000000..2d9db15a5d --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_version.h b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_version.h new file mode 100644 index 0000000000..660f612aa3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/core_cm0.h b/bsp/Vango_V85xx/Libraries/CMSIS/core_cm0.h new file mode 100644 index 0000000000..f929bba07b --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/core_cmFunc.h b/bsp/Vango_V85xx/Libraries/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..4a6b5d6683 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/core_cmFunc.h @@ -0,0 +1,616 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return (__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return (__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return (__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return (__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return (__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return (__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return (__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return (__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return (__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return (__regfpscr); +#else + return (0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control" : "=r"(result)); + return (result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile("MSR control, %0" : : "r"(control)); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, ipsr" : "=r"(result)); + return (result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, apsr" : "=r"(result)); + return (result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, xpsr" : "=r"(result)); + return (result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, psp\n" : "=r"(result)); + return (result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack)); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, msp\n" : "=r"(result)); + return (result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack)); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask" : "=r"(result)); + return (result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile("MSR primask, %0" : : "r"(priMask)); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri_max" : "=r"(result)); + return (result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile("MSR basepri, %0" : : "r"(value)); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask" : "=r"(result)); + return (result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask, %0" : : "r"(faultMask)); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile("VMRS %0, fpscr" : "=r"(result)); + return (result); +#else + return (0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr)); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/core_cmInstr.h b/bsp/Vango_V85xx/Libraries/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..1c0b6f6b97 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + + /** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ + #define __RBIT __rbit + + + /** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + + /** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + + /** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + + /** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ + #define __STREXB(value, ptr) __strex(value, ptr) + + + /** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ + #define __STREXH(value, ptr) __strex(value, ptr) + + + /** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ + #define __STREXW(value, ptr) __strex(value, ptr) + + + /** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ + #define __CLREX __clrex + + + /** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ + #define __SSAT __ssat + + + /** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ + #define __USAT __usat + + + /** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ + #define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile("ror %0, %0, %1" : "+r"(op1) : "r"(op2)); + return (op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr)); + return (result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr)); + return (result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr)); + return (result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("strexb %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); + return (result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("strexh %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); + return (result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("strex %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); + return (result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile("clz %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/Vango_V85xx/Libraries/SConscript b/bsp/Vango_V85xx/Libraries/SConscript new file mode 100644 index 0000000000..797ae66cf4 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/SConscript @@ -0,0 +1,25 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Glob('VangoV85xx_standard_peripheral/Source/*.c') +src += [cwd + '/CMSIS/Vango/V85xx/Source/system_target.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += [cwd + '/CMSIS/Vango/V85xx/Source/GCC/startup_target.S'] + +path = [ + cwd + '/CMSIS/Vango/V85xx/Include', + cwd + '/CMSIS', + cwd + '/VangoV85xx_standard_peripheral/Include',] + +CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'V85xx','USE_TARGET_DRIVER'] + +group = DefineGroup('Vango_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc.h new file mode 100644 index 0000000000..1b82cb6b4c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc.h @@ -0,0 +1,249 @@ +/** + ****************************************************************************** + * @file lib_adc.h + * @author Application Team + * @version V4.6.0 + * @date 2019-06-18 + * @brief ADC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_ADC_H +#define __LIB_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t TrigMode; + uint32_t ConvMode; + uint32_t ClockSource; + uint32_t ClockDivider; + uint32_t Channel; +} ADCInitType; + +//TrigMode +#define ADC_TRIGMODE_AUTO 0 +#define ADC_TRIGMODE_MANUAL ANA_ADCCTRL_MTRIG +#define IS_ADC_TRIGMODE(__TRIGMODE__) (((__TRIGMODE__) == ADC_TRIGMODE_AUTO) ||\ + ((__TRIGMODE__) == ADC_TRIGMODE_MANUAL)) + +//ConvMode +#define ADC_CONVMODE_SINGLECHANNEL 0 +#define ADC_CONVMODE_MULTICHANNEL 1 +#define IS_ADC_CONVMODE(__CONVMODE__) (((__CONVMODE__) == ADC_CONVMODE_SINGLECHANNEL) ||\ + ((__CONVMODE__) == ADC_CONVMODE_MULTICHANNEL)) + +//ClockSource +#define ADC_CLKSRC_RCH 0 +#define ADC_CLKSRC_PLLL ANA_ADCCTRL_CLKSEL +#define IS_ADC_CLKSRC(__CLKSRC__) (((__CLKSRC__) == ADC_CLKSRC_RCH) ||\ + ((__CLKSRC__) == ADC_CLKSRC_PLLL)) + +//TrigSource +#define ADC_TRIGSOURCE_OFF ANA_ADCCTRL_AEN_OFF +#define ADC_TRIGSOURCE_TIM0 ANA_ADCCTRL_AEN_TMR0 +#define ADC_TRIGSOURCE_TIM1 ANA_ADCCTRL_AEN_TMR1 +#define ADC_TRIGSOURCE_TIM2 ANA_ADCCTRL_AEN_TMR2 +#define ADC_TRIGSOURCE_TIM3 ANA_ADCCTRL_AEN_TMR3 +#define IS_ADC_TRIGSOURCE(__TRIGSOURCE__) (((__TRIGSOURCE__) == ADC_TRIGSOURCE_OFF) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM0) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM1) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM2) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM3)) + +//ClockDivider +#define ADC_CLKDIV_1 ANA_ADCCTRL_CLKDIV_1 +#define ADC_CLKDIV_2 ANA_ADCCTRL_CLKDIV_2 +#define ADC_CLKDIV_3 ANA_ADCCTRL_CLKDIV_3 +#define ADC_CLKDIV_4 ANA_ADCCTRL_CLKDIV_4 +#define ADC_CLKDIV_5 ANA_ADCCTRL_CLKDIV_5 +#define ADC_CLKDIV_6 ANA_ADCCTRL_CLKDIV_6 +#define ADC_CLKDIV_7 ANA_ADCCTRL_CLKDIV_7 +#define ADC_CLKDIV_8 ANA_ADCCTRL_CLKDIV_8 +#define ADC_CLKDIV_9 ANA_ADCCTRL_CLKDIV_9 +#define ADC_CLKDIV_10 ANA_ADCCTRL_CLKDIV_10 +#define ADC_CLKDIV_11 ANA_ADCCTRL_CLKDIV_11 +#define ADC_CLKDIV_12 ANA_ADCCTRL_CLKDIV_12 +#define ADC_CLKDIV_13 ANA_ADCCTRL_CLKDIV_13 +#define ADC_CLKDIV_14 ANA_ADCCTRL_CLKDIV_14 +#define ADC_CLKDIV_15 ANA_ADCCTRL_CLKDIV_15 +#define ADC_CLKDIV_16 ANA_ADCCTRL_CLKDIV_16 +#define IS_ADC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == ADC_CLKDIV_1) ||\ + ((__CLKDIV__) == ADC_CLKDIV_2) ||\ + ((__CLKDIV__) == ADC_CLKDIV_3) ||\ + ((__CLKDIV__) == ADC_CLKDIV_4) ||\ + ((__CLKDIV__) == ADC_CLKDIV_5) ||\ + ((__CLKDIV__) == ADC_CLKDIV_6) ||\ + ((__CLKDIV__) == ADC_CLKDIV_7) ||\ + ((__CLKDIV__) == ADC_CLKDIV_8) ||\ + ((__CLKDIV__) == ADC_CLKDIV_9) ||\ + ((__CLKDIV__) == ADC_CLKDIV_10) ||\ + ((__CLKDIV__) == ADC_CLKDIV_11) ||\ + ((__CLKDIV__) == ADC_CLKDIV_12) ||\ + ((__CLKDIV__) == ADC_CLKDIV_13) ||\ + ((__CLKDIV__) == ADC_CLKDIV_14) ||\ + ((__CLKDIV__) == ADC_CLKDIV_15) ||\ + ((__CLKDIV__) == ADC_CLKDIV_16)) + +//Channel +#define ADC_CHANNEL0 0 +#define ADC_CHANNEL1 1 +#define ADC_CHANNEL2 2 +#define ADC_CHANNEL3 3 +#define ADC_CHANNEL4 4 +#define ADC_CHANNEL5 5 +#define ADC_CHANNEL6 6 +#define ADC_CHANNEL7 7 +#define ADC_CHANNEL8 8 +#define ADC_CHANNEL9 9 +#define ADC_CHANNEL10 10 +#define ADC_CHANNEL11 11 + +#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL0) ||\ + ((__CHANNEL__) == ADC_CHANNEL1) ||\ + ((__CHANNEL__) == ADC_CHANNEL2) ||\ + ((__CHANNEL__) == ADC_CHANNEL3) ||\ + ((__CHANNEL__) == ADC_CHANNEL4) ||\ + ((__CHANNEL__) == ADC_CHANNEL5) ||\ + ((__CHANNEL__) == ADC_CHANNEL6) ||\ + ((__CHANNEL__) == ADC_CHANNEL7) ||\ + ((__CHANNEL__) == ADC_CHANNEL8) ||\ + ((__CHANNEL__) == ADC_CHANNEL9) ||\ + ((__CHANNEL__) == ADC_CHANNEL10) ||\ + ((__CHANNEL__) == ADC_CHANNEL11)) + +//INTMask +#define ADC_INT_AUTODONE ANA_INTEN_INTEN1 +#define ADC_INT_MANUALDONE ANA_INTEN_INTEN0 +#define ADC_INT_Msk (ADC_INT_AUTODONE | ADC_INT_MANUALDONE) +#define IS_ADC_INT(__INT__) ((((__INT__) & ADC_INT_Msk) != 0U) &&\ + (((__INT__) & ~ADC_INT_Msk) == 0U)) + +//ScaleDown +#define ADC_SCA_NONE 0 +#define ADC_SCA_DIV2 ANA_ADCCTRL_CICSCA +#define IS_ADC_SCA(__SCA__) (((__SCA__) == ADC_SCA_NONE) || ((__SCA__) == ADC_SCA_DIV2)) + +//Skip +#define ADC_SKIP_4 ANA_ADCCTRL_CICSKIP_4 +#define ADC_SKIP_5 ANA_ADCCTRL_CICSKIP_5 +#define ADC_SKIP_6 ANA_ADCCTRL_CICSKIP_6 +#define ADC_SKIP_7 ANA_ADCCTRL_CICSKIP_7 +#define ADC_SKIP_0 ANA_ADCCTRL_CICSKIP_0 +#define ADC_SKIP_1 ANA_ADCCTRL_CICSKIP_1 +#define ADC_SKIP_2 ANA_ADCCTRL_CICSKIP_2 +#define ADC_SKIP_3 ANA_ADCCTRL_CICSKIP_3 +#define IS_ADC_SKIP(__SKIP__) (((__SKIP__) == ADC_SKIP_4) ||\ + ((__SKIP__) == ADC_SKIP_5) ||\ + ((__SKIP__) == ADC_SKIP_6) ||\ + ((__SKIP__) == ADC_SKIP_7) ||\ + ((__SKIP__) == ADC_SKIP_0) ||\ + ((__SKIP__) == ADC_SKIP_1) ||\ + ((__SKIP__) == ADC_SKIP_2) ||\ + ((__SKIP__) == ADC_SKIP_3)) + +//DSRSelection +#define ADC_SDRSEL_DIV512 ANA_ADCCTRL_DSRSEL_512 +#define ADC_SDRSEL_DIV256 ANA_ADCCTRL_DSRSEL_256 +#define ADC_SDRSEL_DIV128 ANA_ADCCTRL_DSRSEL_128 +#define ADC_SDRSEL_DIV64 ANA_ADCCTRL_DSRSEL_64 +#define IS_ADC_SDR(__SDR__) (((__SDR__) == ADC_SDRSEL_DIV512) ||\ + ((__SDR__) == ADC_SDRSEL_DIV256) ||\ + ((__SDR__) == ADC_SDRSEL_DIV128) ||\ + ((__SDR__) == ADC_SDRSEL_DIV64)) + +typedef struct +{ + float VDDVoltage; + float BATRTCVoltage; + float Temperature; +} ADC_CalResType; +//Division +#define ADC_BAT_CAPDIV (ANA_REG1_GDE4) +#define ADC_BAT_RESDIV (ANA_REG1_RESDIV) + +#define IS_ADC_BATDIV(__BATDIV__) (((__BATDIV__) == ADC_BAT_CAPDIV) ||\ + ((__BATDIV__) == ADC_BAT_RESDIV)) + +/* ADC_GetVoltage */ +//Mode +#define ADC_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None +#define ADC_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive +#define ADC_3V_EXTERNAL_CAPDIV (0x002UL) // Power supply: 3.3V; Channel: External; Divider modeL: Capacitive +#define ADC_3V_VDD_RESDIV (0x003UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive +#define ADC_3V_VDD_CAPDIV (0x004UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Capacitive +#define ADC_3V_BATRTC_RESDIV (0x005UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive +#define ADC_3V_BATRTC_CAPDIV (0x006UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Capacitive +#define ADC_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None +#define ADC_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive +#define ADC_5V_EXTERNAL_CAPDIV (0x102UL) // Power supply: 5V; Channel: External; Divider modeL: Capacitive +#define ADC_5V_VDD_RESDIV (0x103UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive +#define ADC_5V_VDD_CAPDIV (0x104UL) // Power supply: 5V; Channel: VDD; Divider modeL: Capacitive +#define ADC_5V_BATRTC_RESDIV (0x105UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive +#define ADC_5V_BATRTC_CAPDIV (0x106UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Capacitive +#define IS_ADCVOL_MODE(__MODE__) (((__MODE__) == ADC_3V_EXTERNAL_NODIV) ||\ + ((__MODE__) == ADC_3V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == ADC_3V_EXTERNAL_CAPDIV) ||\ + ((__MODE__) == ADC_3V_VDD_RESDIV) ||\ + ((__MODE__) == ADC_3V_VDD_CAPDIV) ||\ + ((__MODE__) == ADC_3V_BATRTC_RESDIV) ||\ + ((__MODE__) == ADC_3V_BATRTC_CAPDIV) ||\ + ((__MODE__) == ADC_5V_EXTERNAL_NODIV) ||\ + ((__MODE__) == ADC_5V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == ADC_5V_EXTERNAL_CAPDIV) ||\ + ((__MODE__) == ADC_5V_VDD_RESDIV) ||\ + ((__MODE__) == ADC_5V_VDD_CAPDIV) ||\ + ((__MODE__) == ADC_5V_BATRTC_RESDIV) ||\ + ((__MODE__) == ADC_5V_BATRTC_CAPDIV)) + +/* Exported Functions ------------------------------------------------------- */ +/* ADC Exported Functions Group1: + (De)Initialization -------------------------*/ +void ADC_DeInit(void); +void ADC_StructInit(ADCInitType* ADC_InitStruct); +void ADC_Init(ADCInitType* ADC_InitStruct); +/* ADC Exported Functions Group2: + Get NVR Info, Calculate datas --------------*/ +uint32_t ADC_CalculateVoltage(uint32_t Mode, int16_t adc_data, float *Voltage); +uint32_t ADC_GetVDDVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults); +uint32_t ADC_GetVDDVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults); +uint32_t ADC_GetBATRTCVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults); +uint32_t ADC_GetBATRTCVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults); +uint32_t ADC_GetTemperature(ADC_CalResType *CalResults); +/* ADC Exported Functions Group3: + Interrupt (flag) ---------------------------*/ +int16_t ADC_GetADCConversionValue(uint32_t Channel); +void ADC_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t ADC_GetAutoDoneFlag(void); +uint8_t ADC_GetManualDoneFlag(void); +void ADC_ClearAutoDoneFlag(void); +void ADC_ClearManualDoneFlag(void); +/* ADC Exported Functions Group4: + MISC Configuration -------------------------*/ +uint32_t ADC_Cmd(uint32_t NewState); +void ADC_StartManual(void); +void ADC_WaitForManual(void); +void ADC_TrigSourceConfig(uint32_t TrigSource); +void ADC_RESDivisionCmd(uint32_t NewState); +void ADC_CAPDivisionCmd(uint32_t NewState); +//CIC Control +void ADC_CICAlwaysOnCmd(uint32_t NewState); +void ADC_CICINVCmd(uint32_t NewState); +void ADC_CICScaleDownConfig(uint32_t ScaleDown); +void ADC_CICSkipConfig(uint32_t Skip); +void ADC_CICDownSamRateConfig(uint32_t DSRSelection); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ADC_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc_tiny.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc_tiny.h new file mode 100644 index 0000000000..b9b8da41a3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc_tiny.h @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file lib_adc_tiny.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief ADC_TINY library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_ADC_TINY_H +#define __LIB_ADC_TINY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t SignalSel; + uint32_t ADTREF1; + uint32_t ADTREF2; + uint32_t ADTREF3; +} TADCInitType; + +//SelADT +#define ADCTINY_SIGNALSEL_IOE6 0 +#define ADCTINY_SIGNALSEL_IOE7 ANA_REGF_SELADT +#define IS_ADCTINY_SELADT(__SELADT__) (((__SELADT__) == ADCTINY_SIGNALSEL_IOE6) ||\ + ((__SELADT__) == ADCTINY_SIGNALSEL_IOE7)) + +//ADTREF1 +#define ADCTINY_REF1_0_9 0 +#define ADCTINY_REF1_0_7 ANA_REGF_ADTREF1SEL +#define IS_ADCTINY_ADTREF1(__ADTREF1__) (((__ADTREF1__) == ADCTINY_REF1_0_9) ||\ + ((__ADTREF1__) == ADCTINY_REF1_0_7)) + +//ADTREF2 +#define ADCTINY_REF2_1_8 0 +#define ADCTINY_REF2_1_6 ANA_REGF_ADTREF2SEL +#define IS_ADCTINY_ADTREF2(__ADTREF2__) (((__ADTREF2__) == ADCTINY_REF2_1_8) ||\ + ((__ADTREF2__) == ADCTINY_REF2_1_6)) + +//ADTREF3 +#define ADCTINY_REF3_2_7 0 +#define ADCTINY_REF3_2_5 ANA_REGF_ADTREF3SEL +#define IS_ADCTINY_ADTREF3(__ADTREF3__) (((__ADTREF3__) == ADCTINY_REF3_2_7) ||\ + ((__ADTREF3__) == ADCTINY_REF3_2_5)) + +//THSel +#define ADCTINY_THSEL_0 ANA_MISC_TADCTH_0 +#define ADCTINY_THSEL_1 ANA_MISC_TADCTH_1 +#define ADCTINY_THSEL_2 ANA_MISC_TADCTH_2 +#define ADCTINY_THSEL_3 ANA_MISC_TADCTH_3 +#define IS_ADCTINY_THSEL(__THSEL__) (((__THSEL__) == ADCTINY_THSEL_0) ||\ + ((__THSEL__) == ADCTINY_THSEL_1) ||\ + ((__THSEL__) == ADCTINY_THSEL_2) ||\ + ((__THSEL__) == ADCTINY_THSEL_3)) + +/* Exported Functions ------------------------------------------------------- */ +void TADC_DeInit(void); +void TADC_StructInit(TADCInitType* TADC_InitStruct); +void TADC_Init(TADCInitType* TADC_InitStruct); +void TADC_Cmd(uint32_t NewState); +uint8_t TADC_GetOutput(void); +void TADC_IntTHConfig(uint32_t THSel); +void TADC_INTConfig(uint32_t NewState); +uint8_t TADC_GetINTStatus(void); +void TADC_ClearINTStatus(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ADC_TINY_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_ana.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_ana.h new file mode 100644 index 0000000000..0a3a073074 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_ana.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file lib_ana.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Analog library. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ +#ifndef __LIB_ANA_H +#define __LIB_ANA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/***** StatusMask (ANA_GetStatus) *****/ +#define ANA_STATUS_AVCCLV ANA_COMPOUT_AVCCLV +#define ANA_STATUS_VDCINDROP ANA_COMPOUT_VDCINDROP +#define ANA_STATUS_VDDALARM ANA_COMPOUT_VDDALARM +#define ANA_STATUS_COMP2 ANA_COMPOUT_COMP2 +#define ANA_STATUS_COMP1 ANA_COMPOUT_COMP1 +#define ANA_STATUS_LOCKL ANA_COMPOUT_LOCKL +#define ANA_STATUS_LOCKH ANA_COMPOUT_LOCKH + +/***** IntMask (ANA_GetINTStatus / ANA_ClearINTStatus / ANA_INTConfig) *****/ +#define ANA_INT_TADC_OVER ANA_INTSTS_INTSTS13 +#define ANA_INT_REGERR ANA_INTSTS_INTSTS12 +#define ANA_INT_SME ANA_INTSTS_INTSTS11 +#define ANA_INT_AVCCLV ANA_INTSTS_INTSTS10 +#define ANA_INT_VDCINDROP ANA_INTSTS_INTSTS8 +#define ANA_INT_VDDALARM ANA_INTSTS_INTSTS7 +#define ANA_INT_COMP2 ANA_INTSTS_INTSTS3 +#define ANA_INT_COMP1 ANA_INTSTS_INTSTS2 +#define ANA_INT_ADCA ANA_INTSTS_INTSTS1 +#define ANA_INT_ADCM ANA_INTSTS_INTSTS0 +#define ANA_INT_Msk (0x3DEFUL) + +/* Private macros ------------------------------------------------------------*/ +#define IS_ANA_STATUS(__STATUS__) (((__STATUS__) == ANA_STATUS_AVCCLV) ||\ + ((__STATUS__) == ANA_STATUS_VDCINDROP) ||\ + ((__STATUS__) == ANA_STATUS_VDDALARM) ||\ + ((__STATUS__) == ANA_STATUS_COMP2) ||\ + ((__STATUS__) == ANA_STATUS_COMP1) ||\ + ((__STATUS__) == ANA_STATUS_LOCKL) ||\ + ((__STATUS__) == ANA_STATUS_LOCKH)) + +#define IS_ANA_INTSTSR(__INTSTSR__) (((__INTSTSR__) == ANA_INT_TADC_OVER) ||\ + ((__INTSTSR__) == ANA_INT_REGERR) ||\ + ((__INTSTSR__) == ANA_INT_SME) ||\ + ((__INTSTSR__) == ANA_INT_AVCCLV) ||\ + ((__INTSTSR__) == ANA_INT_VDCINDROP) ||\ + ((__INTSTSR__) == ANA_INT_VDDALARM) ||\ + ((__INTSTSR__) == ANA_INT_COMP2) ||\ + ((__INTSTSR__) == ANA_INT_COMP1) ||\ + ((__INTSTSR__) == ANA_INT_ADCA) ||\ + ((__INTSTSR__) == ANA_INT_ADCM)) + +#define IS_ANA_INTSTSC(__INTSTSC__) ((((__INTSTSC__) & ANA_INT_Msk) != 0U) &&\ + (((__INTSTSC__) & ~ANA_INT_Msk) == 0U)) + +#define IS_ANA_INT(__INT__) IS_ANA_INTSTSC(__INT__) + +/* Exported Functions ------------------------------------------------------- */ +uint8_t ANA_GetStatus(uint32_t StatusMask); +uint8_t ANA_GetINTStatus(uint32_t IntMask); +void ANA_ClearINTStatus(uint32_t IntMask); +void ANA_INTConfig(uint32_t IntMask, uint32_t NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ANA_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_clk.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_clk.h new file mode 100644 index 0000000000..5c0c2d4753 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_clk.h @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file lib_clk.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Clock library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_CLK_H +#define __LIB_CLK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* PLLL Configure */ +typedef struct +{ + uint32_t Source; + uint32_t State; + uint32_t Frequency; +} PLLL_ConfTypeDef; + +/* PLLH Configure */ +typedef struct +{ + uint32_t Source; + uint32_t State; + uint32_t Frequency; +} PLLH_ConfTypeDef; + +/* RCH Configure */ +typedef struct +{ + uint32_t State; +} RCH_ConfTypeDef; + +/* XTALH Configure */ +typedef struct +{ + uint32_t State; +} XTALH_ConfTypeDef; + +/* RTCCLK Configure */ +typedef struct +{ + uint32_t Source; + uint32_t Divider; +} RTCCLK_ConfTypeDef; + +/* HCLK Configure */ +typedef struct +{ + uint32_t Divider; /* 1 ~ 256 */ +} HCLK_ConfTypeDef; + +/* PCLK Configure */ +typedef struct +{ + uint32_t Divider; /* 1 ~ 256 */ +} PCLK_ConfTypeDef; + +/* Clock Configure */ +typedef struct +{ + uint32_t ClockType; /* The clock to be configured */ + + uint32_t AHBSource; + + PLLL_ConfTypeDef PLLL; + + PLLH_ConfTypeDef PLLH; + + XTALH_ConfTypeDef XTALH; + + RTCCLK_ConfTypeDef RTCCLK; + + HCLK_ConfTypeDef HCLK; + + PCLK_ConfTypeDef PCLK; + +} CLK_InitTypeDef; + +/***** ClockType *****/ +#define CLK_TYPE_Msk (0xFFUL) +#define CLK_TYPE_ALL CLK_TYPE_Msk +#define CLK_TYPE_AHBSRC (0x01UL) /* AHB Clock source to configure */ +#define CLK_TYPE_PLLL (0x02UL) /* PLLL to configure */ +#define CLK_TYPE_PLLH (0x04UL) /* PLLH to configure */ +#define CLK_TYPE_XTALH (0x08UL) /* XTALH to configure */ +#define CLK_TYPE_RTCCLK (0x20UL) /* RTCCLK to configure */ +#define CLK_TYPE_HCLK (0x40UL) /* AHB Clock to configure */ +#define CLK_TYPE_PCLK (0x80UL) /* APB Clock to configure */ + +/***** AHBSource *****/ +#define CLK_AHBSEL_6_5MRC MISC2_CLKSEL_CLKSEL_RCOH +#define CLK_AHBSEL_6_5MXTAL MISC2_CLKSEL_CLKSEL_XOH +#define CLK_AHBSEL_HSPLL MISC2_CLKSEL_CLKSEL_PLLH +#define CLK_AHBSEL_RTCCLK MISC2_CLKSEL_CLKSEL_RTCCLK +#define CLK_AHBSEL_LSPLL MISC2_CLKSEL_CLKSEL_PLLL + +/***** PLLL_ConfTypeDef PLLL *****/ +/* PLLL.Source */ +#define CLK_PLLLSRC_RCL PMU_CONTROL_PLLL_SEL +#define CLK_PLLLSRC_XTALL (0) +/* PLLL.State */ +#define CLK_PLLL_ON ANA_REG3_PLLLPDN +#define CLK_PLLL_OFF (0) +/* PLLL.Frequency */ +#define CLK_PLLL_26_2144MHz ANA_REG9_PLLLSEL_26M +#define CLK_PLLL_13_1072MHz ANA_REG9_PLLLSEL_13M +#define CLK_PLLL_6_5536MHz ANA_REG9_PLLLSEL_6_5M +#define CLK_PLLL_3_2768MHz ANA_REG9_PLLLSEL_3_2M +#define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M +#define CLK_PLLL_0_8192MHz ANA_REG9_PLLLSEL_800K +#define CLK_PLLL_0_4096MHz ANA_REG9_PLLLSEL_400K +#define CLK_PLLL_0_2048MHz ANA_REG9_PLLLSEL_200K + +/***** PLLH_ConfTypeDef PLLH *****/ +/* PLLH.Source */ +#define CLK_PLLHSRC_RCH (0) +#define CLK_PLLHSRC_XTALH PMU_CONTROL_PLLH_SEL +/* PLLH.State */ +#define CLK_PLLH_ON ANA_REG3_PLLHPDN +#define CLK_PLLH_OFF (0) +/* PLLH.Frequency */ +#define CLK_PLLH_13_1072MHz ANA_REG9_PLLHSEL_X2 +#define CLK_PLLH_16_384MHz ANA_REG9_PLLHSEL_X2_5 +#define CLK_PLLH_19_6608MHz ANA_REG9_PLLHSEL_X3 +#define CLK_PLLH_22_9376MHz ANA_REG9_PLLHSEL_X3_5 +#define CLK_PLLH_26_2144MHz ANA_REG9_PLLHSEL_X4 +#define CLK_PLLH_29_4912MHz ANA_REG9_PLLHSEL_X4_5 +#define CLK_PLLH_32_768MHz ANA_REG9_PLLHSEL_X5 +#define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5 +#define CLK_PLLH_39_3216MHz ANA_REG9_PLLHSEL_X6 +#define CLK_PLLH_42_5984MHz ANA_REG9_PLLHSEL_X6_5 +#define CLK_PLLH_45_8752MHz ANA_REG9_PLLHSEL_X7 +#define CLK_PLLH_49_152MHz ANA_REG9_PLLHSEL_X7_5 + +/* XTALH_ConfTypeDef XTALH */ +/* XTALH.State */ +#define CLK_XTALH_ON ANA_REG3_XOHPDN +#define CLK_XTALH_OFF (0) + +/* RTCCLK Configure */ +/* RTCCLK.Source */ +#define CLK_RTCCLKSRC_XTALL (0) +#define CLK_RTCCLKSRC_RCL (PMU_CONTROL_RTCLK_SEL) +/* RTCCLK.Divider */ +#define CLK_RTCCLKDIV_1 (RTC_PSCA_PSCA_0) +#define CLK_RTCCLKDIV_4 (RTC_PSCA_PSCA_1) + +//AHB Periphral +#define CLK_AHBPERIPHRAL_DMA MISC2_HCLKEN_DMA +#define CLK_AHBPERIPHRAL_GPIO MISC2_HCLKEN_GPIO +#define CLK_AHBPERIPHRAL_LCD MISC2_HCLKEN_LCD +#define CLK_AHBPERIPHRAL_CRYPT MISC2_HCLKEN_CRYPT +#define CLK_AHBPERIPHRAL_ALL (MISC2_HCLKEN_DMA \ + |MISC2_HCLKEN_GPIO \ + |MISC2_HCLKEN_LCD \ + |MISC2_HCLKEN_CRYPT) + +//APB Periphral +#define CLK_APBPERIPHRAL_DMA MISC2_PCLKEN_DMA +#define CLK_APBPERIPHRAL_I2C MISC2_PCLKEN_I2C +#define CLK_APBPERIPHRAL_SPI1 MISC2_PCLKEN_SPI1 +#define CLK_APBPERIPHRAL_UART0 MISC2_PCLKEN_UART0 +#define CLK_APBPERIPHRAL_UART1 MISC2_PCLKEN_UART1 +#define CLK_APBPERIPHRAL_UART2 MISC2_PCLKEN_UART2 +#define CLK_APBPERIPHRAL_UART3 MISC2_PCLKEN_UART3 +#define CLK_APBPERIPHRAL_UART4 MISC2_PCLKEN_UART4 +#define CLK_APBPERIPHRAL_UART5 MISC2_PCLKEN_UART5 +#define CLK_APBPERIPHRAL_ISO78160 MISC2_PCLKEN_ISO78160 +#define CLK_APBPERIPHRAL_ISO78161 MISC2_PCLKEN_ISO78161 +#define CLK_APBPERIPHRAL_TIMER MISC2_PCLKEN_TIMER +#define CLK_APBPERIPHRAL_MISC MISC2_PCLKEN_MISC +#define CLK_APBPERIPHRAL_MISC2 MISC2_PCLKEN_MISC2 +#define CLK_APBPERIPHRAL_PMU MISC2_PCLKEN_PMU +#define CLK_APBPERIPHRAL_RTC MISC2_PCLKEN_RTC +#define CLK_APBPERIPHRAL_ANA MISC2_PCLKEN_ANA +#define CLK_APBPERIPHRAL_U32K0 MISC2_PCLKEN_U32K0 +#define CLK_APBPERIPHRAL_U32K1 MISC2_PCLKEN_U32K1 +#define CLK_APBPERIPHRAL_SPI2 MISC2_PCLKEN_SPI2 +#define CLK_APBPERIPHRAL_ALL (MISC2_PCLKEN_DMA \ + |MISC2_PCLKEN_I2C \ + |MISC2_PCLKEN_SPI1 \ + |MISC2_PCLKEN_UART0 \ + |MISC2_PCLKEN_UART1 \ + |MISC2_PCLKEN_UART2 \ + |MISC2_PCLKEN_UART3 \ + |MISC2_PCLKEN_UART4 \ + |MISC2_PCLKEN_UART5 \ + |MISC2_PCLKEN_ISO78160 \ + |MISC2_PCLKEN_ISO78161 \ + |MISC2_PCLKEN_TIMER \ + |MISC2_PCLKEN_MISC \ + |MISC2_PCLKEN_MISC2 \ + |MISC2_PCLKEN_PMU \ + |MISC2_PCLKEN_RTC \ + |MISC2_PCLKEN_ANA \ + |MISC2_PCLKEN_U32K0 \ + |MISC2_PCLKEN_U32K1 \ + |MISC2_PCLKEN_SPI2) + +/***** PLLStatus (CLK_GetPLLLockStatus) *****/ +#define CLK_STATUS_LOCKL ANA_COMPOUT_LOCKL +#define CLK_STATUS_LOCKH ANA_COMPOUT_LOCKH + + +/* Private macros ------------------------------------------------------------*/ +#define IS_CLK_TYPE(__TYPE__) ((((__TYPE__) & CLK_TYPE_Msk) != 0UL) &&\ + (((__TYPE__) & ~CLK_TYPE_Msk) == 0UL)) + +#define IS_CLK_AHBSRC(__AHBSRC__) (((__AHBSRC__) == CLK_AHBSEL_6_5MRC) ||\ + ((__AHBSRC__) == CLK_AHBSEL_6_5MXTAL) ||\ + ((__AHBSRC__) == CLK_AHBSEL_HSPLL) ||\ + ((__AHBSRC__) == CLK_AHBSEL_RTCCLK) ||\ + ((__AHBSRC__) == CLK_AHBSEL_LSPLL)) + +#define IS_CLK_PLLLSRC(__PLLLSRC__) (((__PLLLSRC__) == CLK_PLLLSRC_RCL) ||\ + ((__PLLLSRC__) == CLK_PLLLSRC_XTALL)) + +#define IS_CLK_PLLLSTA(__PLLLSTA__) (((__PLLLSTA__) == CLK_PLLL_ON) ||\ + ((__PLLLSTA__) == CLK_PLLL_OFF)) + +#define IS_CLK_PLLLFRQ(__PLLLFRQ__) (((__PLLLFRQ__) == CLK_PLLL_26_2144MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_13_1072MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_6_5536MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_3_2768MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_1_6384MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_0_8192MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_0_4096MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_0_2048MHz)) + +#define IS_CLK_PLLHSRC(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLHSRC_RCH) ||\ + ((__PLLHSRC__) == CLK_PLLHSRC_XTALH)) + +#define IS_CLK_PLLHSTA(__PLLHSTA__) (((__PLLHSTA__) == CLK_PLLH_ON) ||\ + ((__PLLHSTA__) == CLK_PLLH_OFF)) + +#define IS_CLK_PLLHFRQ(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLH_13_1072MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_16_384MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_19_6608MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_22_9376MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_26_2144MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_29_4912MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_32_768MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_36_0448MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_39_3216MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_42_5984MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_45_8752MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_49_152MHz)) + +#define IS_CLK_XTALHSTA(__XTALHSTA__) (((__XTALHSTA__) == CLK_XTALH_ON) ||\ + ((__XTALHSTA__) == CLK_XTALH_OFF)) + +#define IS_CLK_RTCSRC(__RTCSRC__) (((__RTCSRC__) == CLK_RTCCLKSRC_XTALL) ||\ + ((__RTCSRC__) == CLK_RTCCLKSRC_RCL)) + +#define IS_CLK_RTCDIV(__RTCDIV__) (((__RTCDIV__) == CLK_RTCCLKDIV_1) ||\ + ((__RTCDIV__) == CLK_RTCCLKDIV_4)) + +#define IS_CLK_HCLKDIV(__HCLKDIV__) (((__HCLKDIV__) > 0UL) &&\ + ((__HCLKDIV__) < 257UL)) + +#define IS_CLK_PCLKDIV(__PCLKDIV__) (((__PCLKDIV__) > 0UL) &&\ + ((__PCLKDIV__) < 257UL)) + +#define IS_CLK_AHBPERIPHRAL(__AHBPERIPHRAL__) ((((__AHBPERIPHRAL__) & CLK_AHBPERIPHRAL_ALL) != 0UL) &&\ + (((__AHBPERIPHRAL__) & ~CLK_AHBPERIPHRAL_ALL) == 0UL)) + +#define IS_CLK_APBPERIPHRAL(__APBPERIPHRAL__) ((((__APBPERIPHRAL__) & CLK_APBPERIPHRAL_ALL) != 0UL) &&\ + (((__APBPERIPHRAL__) & ~CLK_APBPERIPHRAL_ALL) == 0UL)) + +#define IS_CLK_PLLLOCK(__PLLLOCK__) (((__PLLLOCK__) == ANA_COMPOUT_LOCKL) ||\ + ((__PLLLOCK__) == ANA_COMPOUT_LOCKH)) +/* Exported Functions ------------------------------------------------------- */ +/* CLK Exported Functions Group1: + Initialization and functions ---------------*/ +void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); + +/* CLK Exported Functions Group2: + Peripheral Control -------------------------*/ +void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState); +void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState); +/* CLK Exported Functions Group3: + Get clock/configuration information --------*/ +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLKFreq(void); +void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); +uint8_t CLK_GetXTALHStatus(void); +uint8_t CLK_GetXTALLStatus(void); +uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CLK_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_comp.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_comp.h new file mode 100644 index 0000000000..f99230f91d --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_comp.h @@ -0,0 +1,97 @@ +/** + ****************************************************************************** + * @file lib_comp.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief COMP library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_COMP_H +#define __LIB_COMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* Macros --------------------------------------------------------------------*/ + +/***** COMP_DEBConfig *****/ +//COMPx +#define COMP_1 (0x00U) +#define COMP_2 (0x02U) +#define IS_COMP(__COMP__) (((__COMP__) == COMP_1) || ((__COMP__) == COMP_2)) +//Debounce +#define COMP_DEB_0 ANA_CTRL_CMP1DEB_0 +#define COMP_DEB_1 ANA_CTRL_CMP1DEB_1 +#define COMP_DEB_2 ANA_CTRL_CMP1DEB_2 +#define COMP_DEB_3 ANA_CTRL_CMP1DEB_3 +#define IS_COMP_DEB(__DEB__) (((__DEB__) == COMP_DEB_0) ||\ + ((__DEB__) == COMP_DEB_1) ||\ + ((__DEB__) == COMP_DEB_2) ||\ + ((__DEB__) == COMP_DEB_3)) + +/***** Mode (COMP_ModeConfig) *****/ +#define COMP_MODE_OFF ANA_CTRL_COMP1_SEL_0 +#define COMP_MODE_RISING ANA_CTRL_COMP1_SEL_1 +#define COMP_MODE_FALLING ANA_CTRL_COMP1_SEL_2 +#define COMP_MODE_BOTH ANA_CTRL_COMP1_SEL_3 +#define IS_COMP_MODE(__MODE__) (((__MODE__) == COMP_MODE_OFF) ||\ + ((__MODE__) == COMP_MODE_RISING) ||\ + ((__MODE__) == COMP_MODE_FALLING) ||\ + ((__MODE__) == COMP_MODE_BOTH)) + +/***** SourceSelect (COMP_ConfigSignalSource) *****/ +#define COMP_SIGNALSRC_P_TO_REF ANA_REG2_CMP1_SEL_0 +#define COMP_SIGNALSRC_N_TO_REF ANA_REG2_CMP1_SEL_1 +#define COMP_SIGNALSRC_P_TO_N ANA_REG2_CMP1_SEL_2 +#define IS_COMP_SIGNALSRC(__SIGNALSRC__) (((__SIGNALSRC__) == COMP_SIGNALSRC_P_TO_REF) ||\ + ((__SIGNALSRC__) == COMP_SIGNALSRC_N_TO_REF) ||\ + ((__SIGNALSRC__) == COMP_SIGNALSRC_P_TO_N)) + +/***** REFSelect (COMP_ConfigREF) *****/ +#define COMP_REF_VREF (0) +#define COMP_REF_BGPREF ANA_REG2_REFSEL_CMP1 +#define IS_COMP_REF(__REF__) (((__REF__) == COMP_REF_VREF) ||\ + ((__REF__) == COMP_REF_BGPREF)) + +/***** BiasSel (COMP_BiasConfig) *****/ +#define COMP_BIAS_20nA ANA_REG5_IT_CMP1_0 +#define COMP_BIAS_100nA ANA_REG5_IT_CMP1_1 +#define COMP_BIAS_500nA ANA_REG5_IT_CMP1_2 +#define IS_COMP_BIAS(__BIAS__) (((__BIAS__) == COMP_BIAS_20nA) ||\ + ((__BIAS__) == COMP_BIAS_100nA)||\ + ((__BIAS__) == COMP_BIAS_500nA)) + +/* Exported Functions ------------------------------------------------------- */ + +void COMP_DEBConfig(uint32_t COMPx, uint32_t Debounce); +void COMP_ModeConfig(uint32_t COMPx, uint32_t Mode); +void COMP_SignalSourceConfig(uint32_t COMPx, uint32_t SourceSelect); +void COMP_REFConfig(uint32_t COMPx, uint32_t REFSelect); +void COMP_BiasConfig(uint32_t COMPx, uint32_t BiasSel); + +void COMP_INTConfig(uint32_t COMPx, uint32_t NewState); +uint8_t COMP_GetINTStatus(uint32_t COMPx); +void COMP_ClearINTStatus(uint32_t COMPx); + +void COMP_Output_Cmd(uint32_t COMPx, uint32_t NewState); +void COMP_Cmd(uint32_t COMPx, uint32_t NewState); + +uint32_t COMP_GetCNTValue(uint32_t COMPx); +void COMP_ClearCNTValue(uint32_t COMPx); +uint8_t COMP1_GetOutputLevel(void); +uint8_t COMP2_GetOutputLevel(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_COMP_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_crypt.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_crypt.h new file mode 100644 index 0000000000..071f098ccf --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_crypt.h @@ -0,0 +1,85 @@ +/** + ****************************************************************************** + * @file lib_crypt.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief CRYPT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_CRYPT_H +#define __LIB_CRYPT_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//Length +#define CRYPT_LENGTH_32 CRYPT_CTRL_LENGTH_32 +#define CRYPT_LENGTH_64 CRYPT_CTRL_LENGTH_64 +#define CRYPT_LENGTH_96 CRYPT_CTRL_LENGTH_96 +#define CRYPT_LENGTH_128 CRYPT_CTRL_LENGTH_128 +#define CRYPT_LENGTH_160 CRYPT_CTRL_LENGTH_160 +#define CRYPT_LENGTH_192 CRYPT_CTRL_LENGTH_192 +#define CRYPT_LENGTH_224 CRYPT_CTRL_LENGTH_224 +#define CRYPT_LENGTH_256 CRYPT_CTRL_LENGTH_256 +#define CRYPT_LENGTH_288 CRYPT_CTRL_LENGTH_288 +#define CRYPT_LENGTH_320 CRYPT_CTRL_LENGTH_320 +#define CRYPT_LENGTH_352 CRYPT_CTRL_LENGTH_352 +#define CRYPT_LENGTH_384 CRYPT_CTRL_LENGTH_384 +#define CRYPT_LENGTH_416 CRYPT_CTRL_LENGTH_416 +#define CRYPT_LENGTH_448 CRYPT_CTRL_LENGTH_448 +#define CRYPT_LENGTH_480 CRYPT_CTRL_LENGTH_480 +#define CRYPT_LENGTH_512 CRYPT_CTRL_LENGTH_512 +//Nostop +#define CRYPT_STOPCPU (0) +#define CRYPT_NOSTOPCPU CRYPT_CTRL_NOSTOP + +/* Private macros ------------------------------------------------------------*/ +#define IS_CRYPT_ADDR(__ADDR__) (((__ADDR__) < 0x8000) &&\ + (((__ADDR__) & 0x3U) == 0U)) + +#define IS_CRYPT_LENGTH(__LENGTH__) (((__LENGTH__) == CRYPT_LENGTH_32) ||\ + ((__LENGTH__) == CRYPT_LENGTH_64) ||\ + ((__LENGTH__) == CRYPT_LENGTH_32) ||\ + ((__LENGTH__) == CRYPT_LENGTH_96) ||\ + ((__LENGTH__) == CRYPT_LENGTH_128) ||\ + ((__LENGTH__) == CRYPT_LENGTH_160) ||\ + ((__LENGTH__) == CRYPT_LENGTH_192) ||\ + ((__LENGTH__) == CRYPT_LENGTH_224) ||\ + ((__LENGTH__) == CRYPT_LENGTH_256) ||\ + ((__LENGTH__) == CRYPT_LENGTH_288) ||\ + ((__LENGTH__) == CRYPT_LENGTH_320) ||\ + ((__LENGTH__) == CRYPT_LENGTH_352) ||\ + ((__LENGTH__) == CRYPT_LENGTH_384) ||\ + ((__LENGTH__) == CRYPT_LENGTH_416) ||\ + ((__LENGTH__) == CRYPT_LENGTH_448) ||\ + ((__LENGTH__) == CRYPT_LENGTH_480) ||\ + ((__LENGTH__) == CRYPT_LENGTH_512)) + +#define IS_CRYPT_NOSTOP(__NOSTOP__) (((__NOSTOP__) == CRYPT_STOPCPU) || ((__NOSTOP__) == CRYPT_NOSTOPCPU)) + +/* Exported Functions ------------------------------------------------------- */ +void CRYPT_AddressAConfig(uint16_t AddrA); +void CRYPT_AddressBConfig(uint16_t AddrB); +void CRYPT_AddressOConfig(uint16_t AddrO); +uint8_t CRYPT_GetCarryBorrowBit(void); +void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop); +void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop); +void CRYPT_StartSub(uint32_t Length, uint32_t Nostop); +void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop); +void CRYPT_WaitForLastOperation(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CRYPT_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_dma.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_dma.h new file mode 100644 index 0000000000..1ecfbf0126 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_dma.h @@ -0,0 +1,253 @@ +/** + ****************************************************************************** + * @file lib_dma.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief DMA library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_DMA_H +#define __LIB_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//Channel +#define DMA_CHANNEL_0 0 +#define DMA_CHANNEL_1 1 +#define DMA_CHANNEL_2 2 +#define DMA_CHANNEL_3 3 + +typedef struct +{ + uint32_t DestAddr; /* destination address */ + uint32_t SrcAddr; /* source address */ + uint8_t FrameLen; /* Frame length */ + uint8_t PackLen; /* Package length */ + uint32_t ContMode; /* Continuous mode */ + uint32_t TransMode; /* Transfer mode */ + uint32_t ReqSrc; /* DMA request source */ + uint32_t DestAddrMode; /* Destination address mode */ + uint32_t SrcAddrMode; /* Source address mode */ + uint32_t TransSize; /* Transfer size mode */ +} DMA_InitType; +//ContMode +#define DMA_CONTMODE_ENABLE DMA_CTL_CONT +#define DMA_CONTMODE_DISABLE 0 +//TransMode +#define DMA_TRANSMODE_SINGLE 0 +#define DMA_TRANSMODE_PACK DMA_CTL_TMODE +//ReqSrc +#define DMA_REQSRC_SOFT DMA_CTL_DMASEL_SOFT +#define DMA_REQSRC_UART0TX DMA_CTL_DMASEL_UART0TX +#define DMA_REQSRC_UART0RX DMA_CTL_DMASEL_UART0RX +#define DMA_REQSRC_UART1TX DMA_CTL_DMASEL_UART1TX +#define DMA_REQSRC_UART1RX DMA_CTL_DMASEL_UART1RX +#define DMA_REQSRC_UART2TX DMA_CTL_DMASEL_UART2TX +#define DMA_REQSRC_UART2RX DMA_CTL_DMASEL_UART2RX +#define DMA_REQSRC_UART3TX DMA_CTL_DMASEL_UART3TX +#define DMA_REQSRC_UART3RX DMA_CTL_DMASEL_UART3RX +#define DMA_REQSRC_UART4TX DMA_CTL_DMASEL_UART4TX +#define DMA_REQSRC_UART4RX DMA_CTL_DMASEL_UART4RX +#define DMA_REQSRC_UART5TX DMA_CTL_DMASEL_UART5TX +#define DMA_REQSRC_UART5RX DMA_CTL_DMASEL_UART5RX +#define DMA_REQSRC_ISO78160TX DMA_CTL_DMASEL_ISO78160TX +#define DMA_REQSRC_ISO78160RX DMA_CTL_DMASEL_ISO78160RX +#define DMA_REQSRC_ISO78161TX DMA_CTL_DMASEL_ISO78161TX +#define DMA_REQSRC_ISO78161RX DMA_CTL_DMASEL_ISO78161RX +#define DMA_REQSRC_TIMER0 DMA_CTL_DMASEL_TIMER0 +#define DMA_REQSRC_TIMER1 DMA_CTL_DMASEL_TIMER1 +#define DMA_REQSRC_TIMER2 DMA_CTL_DMASEL_TIMER2 +#define DMA_REQSRC_TIMER3 DMA_CTL_DMASEL_TIMER3 +#define DMA_REQSRC_SPI1TX DMA_CTL_DMASEL_SPI1TX +#define DMA_REQSRC_SPI1RX DMA_CTL_DMASEL_SPI1RX +#define DMA_REQSRC_U32K0 DMA_CTL_DMASEL_U32K0 +#define DMA_REQSRC_U32K1 DMA_CTL_DMASEL_U32K1 +#define DMA_REQSRC_CMP1 DMA_CTL_DMASEL_CMP1 +#define DMA_REQSRC_CMP2 DMA_CTL_DMASEL_CMP2 +#define DMA_REQSRC_SPI2TX DMA_CTL_DMASEL_SPI2TX +#define DMA_REQSRC_SPI2RX DMA_CTL_DMASEL_SPI2RX +//DestAddrMode +#define DMA_DESTADDRMODE_FIX DMA_CxCTL_DMODE_FIX +#define DMA_DESTADDRMODE_PEND DMA_CxCTL_DMODE_PEND +#define DMA_DESTADDRMODE_FEND DMA_CxCTL_DMODE_FEND +//SrcAddrMode +#define DMA_SRCADDRMODE_FIX DMA_CxCTL_SMODE_FIX +#define DMA_SRCADDRMODE_PEND DMA_CxCTL_SMODE_PEND +#define DMA_SRCADDRMODE_FEND DMA_CxCTL_SMODE_FEND +//TransSize +#define DMA_TRANSSIZE_BYTE DMA_CxCTL_SIZE_BYTE +#define DMA_TRANSSIZE_HWORD DMA_CxCTL_SIZE_HWORD +#define DMA_TRANSSIZE_WORD DMA_CxCTL_SIZE_WORD + +typedef struct +{ + uint32_t Mode; /* AES mode */ + uint32_t Direction; /* Direction */ + uint32_t *KeyStr; /* AES key */ +} DMA_AESInitType; +//AES MODE +#define DMA_AESMODE_128 DMA_AESCTL_MODE_AES128 +#define DMA_AESMODE_192 DMA_AESCTL_MODE_AES192 +#define DMA_AESMODE_256 DMA_AESCTL_MODE_AES256 +//AES Direction +#define DMA_AESDIRECTION_ENCODE DMA_AESCTL_ENC +#define DMA_AESDIRECTION_DECODE 0 + +//INT +#define DMA_INT_C3DA DMA_IE_C3DAIE +#define DMA_INT_C2DA DMA_IE_C2DAIE +#define DMA_INT_C1DA DMA_IE_C1DAIE +#define DMA_INT_C0DA DMA_IE_C0DAIE +#define DMA_INT_C3FE DMA_IE_C3FEIE +#define DMA_INT_C2FE DMA_IE_C2FEIE +#define DMA_INT_C1FE DMA_IE_C1FEIE +#define DMA_INT_C0FE DMA_IE_C0FEIE +#define DMA_INT_C3PE DMA_IE_C3PEIE +#define DMA_INT_C2PE DMA_IE_C2PEIE +#define DMA_INT_C1PE DMA_IE_C1PEIE +#define DMA_INT_C0PE DMA_IE_C0PEIE +#define DMA_INT_Msk (0xFFFUL) + +//INTSTS +#define DMA_INTSTS_C3DA DMA_STS_C3DA +#define DMA_INTSTS_C2DA DMA_STS_C2DA +#define DMA_INTSTS_C1DA DMA_STS_C1DA +#define DMA_INTSTS_C0DA DMA_STS_C0DA +#define DMA_INTSTS_C3FE DMA_STS_C3FE +#define DMA_INTSTS_C2FE DMA_STS_C2FE +#define DMA_INTSTS_C1FE DMA_STS_C1FE +#define DMA_INTSTS_C0FE DMA_STS_C0FE +#define DMA_INTSTS_C3PE DMA_STS_C3PE +#define DMA_INTSTS_C2PE DMA_STS_C2PE +#define DMA_INTSTS_C1PE DMA_STS_C1PE +#define DMA_INTSTS_C0PE DMA_STS_C0PE +#define DMA_INTSTS_C3BUSY DMA_STS_C3BUSY +#define DMA_INTSTS_C2BUSY DMA_STS_C2BUSY +#define DMA_INTSTS_C1BUSY DMA_STS_C1BUSY +#define DMA_INTSTS_C0BUSY DMA_STS_C0BUSY +#define DMA_INTSTS_Msk (0xFFF0UL) + +/* Private macros ------------------------------------------------------------*/ +#define IS_DMA_CHANNEL(__CH__) (((__CH__) == DMA_CHANNEL_0) ||\ + ((__CH__) == DMA_CHANNEL_1) ||\ + ((__CH__) == DMA_CHANNEL_2) ||\ + ((__CH__) == DMA_CHANNEL_3)) + +#define IS_DMA_ALIGNEDADDR_WORD(__ADDRW__) (((__ADDRW__) & 0x3U) == 0U) + +#define IS_DMA_ALIGNEDADDR_HWORD(__ADDRHW__) (((__ADDRHW__) & 0x1U) == 0U) + +#define IS_DMA_CONTMOD(__CONTMOD__) (((__CONTMOD__) == DMA_CONTMODE_ENABLE) ||\ + ((__CONTMOD__) == DMA_CONTMODE_DISABLE)) + +#define IS_DMA_TRANSMOD(__TRANSMOD__) (((__TRANSMOD__) == DMA_TRANSMODE_SINGLE) ||\ + ((__TRANSMOD__) == DMA_TRANSMODE_PACK)) + +#define IS_DMA_REQSRC(__REQSRC__) (((__REQSRC__) == DMA_REQSRC_SOFT) ||\ + ((__REQSRC__) == DMA_REQSRC_UART0TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART0RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART1TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART1RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART2TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART2RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART3TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART3RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART4TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART4RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART5TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART5RX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78160TX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78160RX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78161TX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78161RX) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER0) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER1) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER2) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER3) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI1TX) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI1RX) ||\ + ((__REQSRC__) == DMA_REQSRC_U32K0) ||\ + ((__REQSRC__) == DMA_REQSRC_U32K1) ||\ + ((__REQSRC__) == DMA_REQSRC_CMP1) ||\ + ((__REQSRC__) == DMA_REQSRC_CMP2) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI2TX) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI2RX)) + +#define IS_DMA_DESTADDRMOD(__DAM__) (((__DAM__) == DMA_DESTADDRMODE_FIX) ||\ + ((__DAM__) == DMA_DESTADDRMODE_PEND) ||\ + ((__DAM__) == DMA_DESTADDRMODE_FEND)) + +#define IS_DMA_SRCADDRMOD(__SAM__) (((__SAM__) == DMA_SRCADDRMODE_FIX) ||\ + ((__SAM__) == DMA_SRCADDRMODE_PEND) ||\ + ((__SAM__) == DMA_SRCADDRMODE_FEND)) + +#define IS_DMA_TRANSSIZE(__TSIZE__) (((__TSIZE__) == DMA_TRANSSIZE_BYTE) ||\ + ((__TSIZE__) == DMA_TRANSSIZE_HWORD) ||\ + ((__TSIZE__) == DMA_TRANSSIZE_WORD)) + +#define IS_DMA_AESMOD(__AESMOD__) (((__AESMOD__) == DMA_AESMODE_128) ||\ + ((__AESMOD__) == DMA_AESMODE_192) ||\ + ((__AESMOD__) == DMA_AESMODE_256)) + +#define IS_DMA_AESDIR(__AESDIR__) (((__AESDIR__) == DMA_AESDIRECTION_ENCODE) ||\ + ((__AESDIR__) == DMA_AESDIRECTION_DECODE)) + +#define IS_DMA_INT(__INT__) ((((__INT__) & DMA_INT_Msk) != 0U) &&\ + (((__INT__) & ~DMA_INT_Msk) == 0U)) + +#define IS_DMA_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == DMA_INTSTS_C3DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C3FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C3PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C3BUSY) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2BUSY) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1BUSY) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0BUSY)) + +#define IS_DMA_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & DMA_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~DMA_INTSTS_Msk) == 0U)) + +/* Exported Functions ------------------------------------------------------- */ +/* DMA Exported Functions Group1: + (De)Initialization ------------------------*/ +void DMA_DeInit(uint32_t Channel); +void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel); +void DMA_AESDeInit(void); +void DMA_AESInit(DMA_AESInitType *InitStruct); +/* DMA Exported Functions Group2: + Interrupt (flag) --------------------------*/ +void DMA_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t DMA_GetINTStatus(uint32_t INTMask); +void DMA_ClearINTStatus(uint32_t INTMask); +/* DMA Exported Functions Group3: + MISC Configuration ------------------------*/ +void DMA_Cmd(uint32_t Channel, uint32_t NewState); +void DMA_AESCmd(uint32_t NewState); +void DMA_StopTransmit(uint32_t Channel, uint32_t NewState); +uint8_t DMA_GetFrameLenTransferred(uint32_t Channel); +uint8_t DMA_GetPackLenTransferred(uint32_t Channel); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_DMA_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_flash.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_flash.h new file mode 100644 index 0000000000..dc1304b4b3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_flash.h @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file lib_flash.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief FLASH library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_FLASH_H +#define __LIB_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//CSMode +#define FLASH_CSMODE_DISABLE FLASH_CTRL_CSMODE_DISABLE +#define FLASH_CSMODE_ALWAYSON FLASH_CTRL_CSMODE_ALWAYSON +#define FLASH_CSMODE_TIM2OF FLASH_CTRL_CSMODE_TIM2OV +#define FLASH_CSMODE_RTC FLASH_CTRL_CSMODE_RTC +#define IS_FLASH_CSMODE(__CSMODE__) (((__CSMODE__) == FLASH_CSMODE_DISABLE) ||\ + ((__CSMODE__) == FLASH_CSMODE_ALWAYSON) ||\ + ((__CSMODE__) == FLASH_CSMODE_TIM2OF) ||\ + ((__CSMODE__) == FLASH_CSMODE_RTC)) + +//INT +#define FLASH_INT_CS FLASH_CTRL_CSINTEN +#define IS_FLASH_INT(__INT__) ((__INT__) == FLASH_INT_CS) + +//WriteStatus +#define FLASH_WSTA_BUSY 0 +#define FLASH_WRITE_FINISH 1 +#define FLASH_WSTA_FINISH FLASH_WRITE_FINISH + +#define IS_FLASH_ADDRESS(__ADDRESS__) ((__ADDRESS__) < 0x40000UL) + +#define IS_FLASH_ADRRW(__ADDRW__) (((__ADDRW__) < 0x40000UL) &&\ + (((__ADDRW__) & 0x3U) == 0U)) + +#define IS_FLASH_ADRRHW(__ADDRHW__) (((__ADDRHW__) < 0x40000UL) &&\ + (((__ADDRHW__) & 0x1U) == 0U)) + +#define IS_FLASH_CHECKSUMADDR(__ADDRESS1__,__ADDRESS2__) (((__ADDRESS1__) < 0x40000) && ((__ADDRESS2__) < 0x40000) && ((__ADDRESS1__) < (__ADDRESS2__))) + +/* Exported Functions ------------------------------------------------------- */ + +void FLASH_Init(uint32_t CSMode); +void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState); +void FLASH_CycleInit(void); +void FLASH_SectorErase(uint32_t SectorAddr); +void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length); +void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length); +void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length); +uint32_t FLASH_GetWriteStatus(void); +void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd); +void FLASH_SetCheckSumCompValue(uint32_t Checksum); +uint32_t FLASH_GetCheckSum(void); +uint8_t FLASH_GetINTStatus(uint32_t IntMask); +void FLASH_ClearINTStatus(uint32_t IntMask); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_FLASH_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_gpio.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_gpio.h new file mode 100644 index 0000000000..985a788d0b --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_gpio.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file lib_gpio.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief GPIO library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_GPIO_H +#define __LIB_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t GPIO_Pin; + uint32_t GPIO_Mode; +} GPIO_InitType; + +/** + * @brief Bit_State_enumeration + */ +typedef enum { + Bit_RESET = 0, + Bit_SET +} BitState; + +//GPIO_Pin +#define GPIO_Pin_0 ((uint16_t)0x0001) +#define GPIO_Pin_1 ((uint16_t)0x0002) +#define GPIO_Pin_2 ((uint16_t)0x0004) +#define GPIO_Pin_3 ((uint16_t)0x0008) +#define GPIO_Pin_4 ((uint16_t)0x0010) +#define GPIO_Pin_5 ((uint16_t)0x0020) +#define GPIO_Pin_6 ((uint16_t)0x0040) +#define GPIO_Pin_7 ((uint16_t)0x0080) +#define GPIO_Pin_8 ((uint16_t)0x0100) +#define GPIO_Pin_9 ((uint16_t)0x0200) +#define GPIO_Pin_10 ((uint16_t)0x0400) +#define GPIO_Pin_11 ((uint16_t)0x0800) +#define GPIO_Pin_12 ((uint16_t)0x1000) +#define GPIO_Pin_13 ((uint16_t)0x2000) +#define GPIO_Pin_14 ((uint16_t)0x4000) +#define GPIO_Pin_15 ((uint16_t)0x8000) +#define GPIO_Pin_All ((uint16_t)0xFFFF) +//GPIO_Mode +#define GPIO_Mode_INPUT (0xCU) +#define GPIO_Mode_OUTPUT_CMOS (0x2U) +#define GPIO_Mode_OUTPUT_OD (0x3U) +#define GPIO_Mode_INOUT_OD (0xBU) +#define GPIO_Mode_INOUT_CMOS (0xAU) +#define GPIO_Mode_FORBIDDEN (0x4U) + +//GPIO AF +#define GPIOB_AF_PLLHDIV IOB_SEL_SEL1 +#define GPIOB_AF_OSC IOB_SEL_SEL6 +#define GPIOB_AF_PLLLOUT IOB_SEL_SEL2 +#define GPIOE_AF_CMP1O IOE_SEL_SEL7 + +//PMUIO AF +#define PMUIO7_AF_PLLDIV PMU_IOASEL_SEL7 +#define PMUIO_AF_CMP2O PMU_IOASEL_SEL6 +#define PMUIO3_AF_PLLDIV PMU_IOASEL_SEL3 +#define PMUIO_AF_Msk (PMUIO7_AF_PLLDIV | PMUIO_AF_CMP2O | PMUIO3_AF_PLLDIV) + +//GPIO pin remap +#define GPIO_REMAP_I2C IO_MISC_I2CIOC + +//PLLDIV +#define GPIO_PLLDIV_1 IO_MISC_PLLHDIV_1 +#define GPIO_PLLDIV_2 IO_MISC_PLLHDIV_2 +#define GPIO_PLLDIV_4 IO_MISC_PLLHDIV_4 +#define GPIO_PLLDIV_8 IO_MISC_PLLHDIV_8 +#define GPIO_PLLDIV_16 IO_MISC_PLLHDIV_16 + +/* Private macros ------------------------------------------------------------*/ +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_Pin_All) != 0UL) &&\ + (((__PIN__) & ~GPIO_Pin_All) == 0UL)) + +#define IS_GPIO_PINR(__PINR__) (((__PINR__) == GPIO_Pin_0) ||\ + ((__PINR__) == GPIO_Pin_1) ||\ + ((__PINR__) == GPIO_Pin_2) ||\ + ((__PINR__) == GPIO_Pin_3) ||\ + ((__PINR__) == GPIO_Pin_4) ||\ + ((__PINR__) == GPIO_Pin_5) ||\ + ((__PINR__) == GPIO_Pin_6) ||\ + ((__PINR__) == GPIO_Pin_7) ||\ + ((__PINR__) == GPIO_Pin_8) ||\ + ((__PINR__) == GPIO_Pin_9) ||\ + ((__PINR__) == GPIO_Pin_10) ||\ + ((__PINR__) == GPIO_Pin_11) ||\ + ((__PINR__) == GPIO_Pin_12) ||\ + ((__PINR__) == GPIO_Pin_13) ||\ + ((__PINR__) == GPIO_Pin_14) ||\ + ((__PINR__) == GPIO_Pin_15)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_INPUT) ||\ + ((__MODE__) == GPIO_Mode_OUTPUT_CMOS) ||\ + ((__MODE__) == GPIO_Mode_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_Mode_INOUT_OD) ||\ + ((__MODE__) == GPIO_Mode_INOUT_CMOS) ||\ + ((__MODE__) == GPIO_Mode_FORBIDDEN)) + +#define IS_GPIO_BITVAL(__BITVAL__) (((__BITVAL__) == 1U) || ((__BITVAL__) == 0U)) + +#define IS_GPIO_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\ + ((__GPIOAF__) == GPIOB_AF_OSC) ||\ + ((__GPIOAF__) == GPIOE_AF_CMP1O) ||\ + ((__GPIOAF__) == GPIOB_AF_PLLLOUT)) + +#define IS_GPIO_PMUIOAF(__PMUIOAF__) ((((__PMUIOAF__) & PMUIO_AF_Msk) != 0U) &&\ + (((__PMUIOAF__) & ~PMUIO_AF_Msk) == 0U)) + +#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C) + +#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_2) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_4) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_8) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_16)) + +/* Exported Functions ------------------------------------------------------- */ +/* GPIO Exported Functions Group1: + Initialization and functions --------------*/ +void GPIOBToF_Init(GPIO_TypeDef *GPIOx, GPIO_InitType *InitStruct); +void GPIOA_Init(GPIOA_TypeDef *GPIOx, GPIO_InitType *InitStruct); +/* GPIO Exported Functions Group2: + Read input data ---------------------------*/ +uint8_t GPIOBToF_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint8_t GPIOA_ReadInputDataBit(GPIOA_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIOBToF_ReadInputData(GPIO_TypeDef* GPIOx); +uint16_t GPIOA_ReadInputData(GPIOA_TypeDef* GPIOx); +/* GPIO Exported Functions Group3: + Read output data --------------------------*/ +uint8_t GPIOBToF_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint8_t GPIOA_ReadOutputDataBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIOBToF_ReadOutputData(GPIO_TypeDef* GPIOx); +uint16_t GPIOA_ReadOutputData(GPIOA_TypeDef* GPIOx); +/* GPIO Exported Functions Group4: + Write output data -------------------------*/ +void GPIOBToF_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIOA_SetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIOBToF_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIOA_ResetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIOBToF_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val); +void GPIOA_WriteBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val); +void GPIOBToF_Write(GPIO_TypeDef* GPIOx, uint16_t val); +void GPIOA_Write(GPIOA_TypeDef* GPIOx, uint16_t val); +/* GPIO Exported Functions Group5: + IO AF configure ---------------------------*/ +void GPIOBToF_AFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_AFx, uint8_t NewState); +void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState); +/* GPIO Exported Functions Group6: + IO Remap configure ------------------------*/ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState); +/* GPIO Exported Functions Group7: + Others ------------------------------------*/ +void GPIO_PLLDIV_Config(uint32_t Divider); +void GPIOA_NoDeg_Cmd( uint16_t GPIO_Pin, uint8_t NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_GPIO_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_i2c.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_i2c.h new file mode 100644 index 0000000000..4976a68e91 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_i2c.h @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file lib_i2c.h + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief IIC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_I2C_H +#define __LIB_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t SlaveAddr; + uint32_t GeneralCallAck; + uint32_t AssertAcknowledge; + uint32_t ClockSource; +} I2C_InitType; +//GeneralCallAck +#define I2C_GENERALCALLACK_ENABLE I2C_ADDR_GC +#define I2C_GENERALCALLACK_DISABLE 0 +//AssertAcknowledge +#define I2C_ASSERTACKNOWLEDGE_ENABLE I2C_CTRL_AA +#define I2C_ASSERTACKNOWLEDGE_DISABLE 0 +//ClockSource +#define I2C_CLOCKSOURCE_APBD256 I2C_CTRL_CR_0 +#define I2C_CLOCKSOURCE_APBD224 I2C_CTRL_CR_1 +#define I2C_CLOCKSOURCE_APBD192 I2C_CTRL_CR_2 +#define I2C_CLOCKSOURCE_APBD160 I2C_CTRL_CR_3 +#define I2C_CLOCKSOURCE_APBD960 I2C_CTRL_CR_4 +#define I2C_CLOCKSOURCE_APBD120 I2C_CTRL_CR_5 +#define I2C_CLOCKSOURCE_APBD60 I2C_CTRL_CR_6 +#define I2C_CLOCKSOURCE_TIM3OFD8 I2C_CTRL_CR_7 + +typedef struct +{ + uint16_t SlaveAddr; + uint8_t SubAddrType; + uint32_t PageRange; + uint32_t SubAddress; + uint8_t *pBuffer; + uint32_t Length; +} I2C_WRType; +//SubAddrType +#define I2C_SUBADDR_1BYTE 1 +#define I2C_SUBADDR_2BYTE 2 +#define I2C_SUBADDR_OTHER 3 + +//remap +#define I2C_REMAP_ENABLE 1 +#define I2C_REMAP_DISABLE 0 + +/* Private macros ------------------------------------------------------------*/ + +#define IS_I2C_GC(__GC__) (((__GC__) == I2C_GENERALCALLACK_ENABLE) ||\ + ((__GC__) == I2C_GENERALCALLACK_DISABLE)) + +#define IS_I2C_AA(__AA__) (((__AA__) == I2C_ASSERTACKNOWLEDGE_ENABLE) ||\ + ((__AA__) == I2C_ASSERTACKNOWLEDGE_DISABLE)) + +#define IS_I2C_CLKSRC(__CLKSRC__) (((__CLKSRC__) == I2C_CLOCKSOURCE_APBD256) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD224) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD192) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD160) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD960) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD120) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD60) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_TIM3OFD8)) + +#define I2C_SUBADDR_TYPE(__TYPE__) (((__TYPE__) == I2C_SUBADDR_1BYTE) ||\ + ((__TYPE__) == I2C_SUBADDR_2BYTE) ||\ + ((__TYPE__) == I2C_SUBADDR_OTHER)) + +/* Exported Functions ------------------------------------------------------- */ +/* I2C Exported Functions Group1: + (De)Initialization ------------------------*/ +void I2C_DeInit(uint32_t remap); +void I2C_StructInit(I2C_InitType *InitStruct); +void I2C_Init(I2C_InitType *InitStruct); +/* I2C Exported Functions Group2: + Interrupt ---------------------------------*/ +void I2C_INTConfig(uint32_t NewState); +uint8_t I2C_GetINTStatus(void); +void I2C_ClearINTStatus(void); +/* I2C Exported Functions Group3: + Transfer datas ----------------------------*/ +uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct); +uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct); +/* I2C Exported Functions Group4: + MISC Configuration ------------------------*/ +void I2C_Cmd(uint32_t NewState); + +/* I2C Exported Functions Group5: + Others ------------------------------------*/ +void I2C_AssertAcknowledgeConfig(uint32_t NewState); +uint8_t I2C_ReceiveData(void); +void I2C_SendData(uint8_t Dat); +void I2C_GenerateSTART(uint32_t NewState); +void I2C_GenerateSTOP(uint32_t NewState); +uint8_t I2C_GetStatusCode(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_I2C_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_iso7816.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_iso7816.h new file mode 100644 index 0000000000..fb77f3084a --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_iso7816.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file lib_iso7816.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief ISO7816 library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_ISO7816_H +#define __LIB_ISO7816_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t FirstBit; + uint32_t ACKLen; + uint32_t Parity; + uint32_t Baudrate; +} ISO7816_InitType; + +//FirstBit +#define ISO7816_FIRSTBIT_LSB ISO7816_INFO_LSB +#define ISO7816_FIRSTBIT_MSB 0 +#define IS_ISO7816_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == ISO7816_FIRSTBIT_LSB) ||\ + ((__FIRSTBIT__) == ISO7816_FIRSTBIT_MSB)) +//ACKLen +#define ISO7816_ACKLEN_1 0 +#define ISO7816_ACKLEN_2 ISO7816_CFG_ACKLEN +#define IS_ISO7816_ACKLEN(__ACKLEN__) (((__ACKLEN__) == ISO7816_ACKLEN_1) ||\ + ((__ACKLEN__) == ISO7816_ACKLEN_2)) +//Parity +#define ISO7816_PARITY_EVEN 0 +#define ISO7816_PARITY_ODD ISO7816_CFG_CHKP +#define IS_ISO7816_PARITY(__PARITY__) (((__PARITY__) == ISO7816_PARITY_EVEN) || ((__PARITY__) == ISO7816_PARITY_ODD)) + +#define IS_ISO7816_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) > 299UL) +#define IS_ISO7816_PRESCALER(__PRESCALER__) (((__PRESCALER__) <= 0x80) && ((__PRESCALER__) > 0U)) + +//interrupt +#define ISO7816_INT_RXOV ISO7816_CFG_OVIE +#define ISO7816_INT_TX ISO7816_CFG_SDIE +#define ISO7816_INT_RX ISO7816_CFG_RCIE +#define ISO7816_INT_Msk (ISO7816_INT_RXOV \ + |ISO7816_INT_TX \ + |ISO7816_INT_RX) +#define IS_ISO7816_INT(__INT__) ((((__INT__) & ISO7816_INT_Msk) != 0U) &&\ + (((__INT__) & ~ISO7816_INT_Msk) == 0U)) + +//INTStatus +#define ISO7816_INTSTS_RXOV ISO7816_INFO_OVIF +#define ISO7816_INTSTS_TX ISO7816_INFO_SDIF +#define ISO7816_INTSTS_RX ISO7816_INFO_RCIF +#define ISO7816_INTSTS_Msk (ISO7816_INTSTS_RXOV \ + |ISO7816_INTSTS_TX \ + |ISO7816_INTSTS_RX) +#define IS_ISO7816_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == ISO7816_INTSTS_RXOV) ||\ + ((__INTFLAG__) == ISO7816_INTSTS_TX) ||\ + ((__INTFLAG__) == ISO7816_INTSTS_RX)) + +#define IS_ISO7816_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&ISO7816_INTSTS_Msk) != 0U) &&\ + (((__INTFLAG__)&(~ISO7816_INTSTS_Msk)) == 0U)) +//status +#define ISO7816_FLAG_SDERR ISO7816_INFO_SDERR +#define ISO7816_FLAG_RCERR ISO7816_INFO_RCERR +#define ISO7816_FLAG_Msk (ISO7816_FLAG_SDERR|ISO7816_FLAG_RCERR) +#define IS_ISO7816_FLAGR(__FLAG__) (((__FLAG__) == ISO7816_FLAG_SDERR) || ((__FLAG__) == ISO7816_FLAG_RCERR)) +#define IS_ISO7816_FLAGC(__FLAG__) ((((__FLAG__) & ISO7816_FLAG_Msk) != 0U) &&\ + (((__FLAG__) & (~ISO7816_FLAG_Msk)) == 0U)) + +/* Exported Functions ------------------------------------------------------- */ +void ISO7816_DeInit(ISO7816_TypeDef *ISO7816x); +void ISO7816_StructInit(ISO7816_InitType *InitStruct); +void ISO7816_Init(ISO7816_TypeDef *ISO7816x, ISO7816_InitType *Init_Struct); +void ISO7816_Cmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState); +void ISO7816_BaudrateConfig(ISO7816_TypeDef *ISO7816x, uint32_t BaudRate); +void ISO7816_CLKDIVConfig(ISO7816_TypeDef *ISO7816x, uint32_t Prescaler); +void ISO7816_CLKOutputCmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState); +void ISO7816_SendData(ISO7816_TypeDef *ISO7816x, uint8_t ch); +uint8_t ISO7816_ReceiveData(ISO7816_TypeDef *ISO7816x); +void ISO7816_INTConfig(ISO7816_TypeDef *ISO7816x, uint32_t INTMask, uint8_t NewState); +uint8_t ISO7816_GetINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask); +void ISO7816_ClearINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask); +uint8_t ISO7816_GetFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask); +void ISO7816_ClearFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask); +uint8_t ISO7816_GetLastTransmitACK(ISO7816_TypeDef *ISO7816x); +uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_TypeDef *ISO7816x); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ISO7816_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_lcd.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_lcd.h new file mode 100644 index 0000000000..785330619f --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_lcd.h @@ -0,0 +1,162 @@ +/** + ****************************************************************************** + * @file lib_lcd.h + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief LCD library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_LCD_H +#define __LIB_LCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* LCD SEGx IO typedef */ +typedef struct +{ + __IO uint32_t *GPIO; + uint16_t Pin; +}LCD_SEGIO; + +/* LCD COMx IO typedef */ +typedef struct +{ + __IO uint32_t *GPIO; + uint16_t Pin; +}LCD_COMIO; + +typedef struct +{ + uint32_t Type; + uint32_t Drv; + uint32_t FRQ; + uint32_t SWPR; + uint32_t FBMODE; + uint32_t BKFILL; +} LCD_InitType; +//Type +#define LCD_TYPE_4COM LCD_CTRL_TYPE_4COM +#define LCD_TYPE_6COM LCD_CTRL_TYPE_6COM +#define LCD_TYPE_8COM LCD_CTRL_TYPE_8COM +//DrivingRes +#define LCD_DRV_300 LCD_CTRL_DRV_300KOHM +#define LCD_DRV_600 LCD_CTRL_DRV_600KOHM +#define LCD_DRV_150 LCD_CTRL_DRV_150KOHM +#define LCD_DRV_200 LCD_CTRL_DRV_200KOHM +//ScanFRQ +#define LCD_FRQ_64H LCD_CTRL_FRQ_64HZ +#define LCD_FRQ_128H LCD_CTRL_FRQ_128HZ +#define LCD_FRQ_256H LCD_CTRL_FRQ_256HZ +#define LCD_FRQ_512H LCD_CTRL_FRQ_512HZ +//SwitchMode +#define LCD_FBMODE_BUFA LCD_CTRL2_FBMODE_BUFA +#define LCD_FBMODE_BUFAB LCD_CTRL2_FBMODE_BUFAANDBUFB +#define LCD_FBMODE_BUFABLANK LCD_CTRL2_FBMODE_BUFAANDBLANK +//BlankFill +#define LCD_BKFILL_1 LCD_CTRL2_BKFILL +#define LCD_BKFILL_0 0 + +//ComMode +#define LCD_COMMOD_4COM 1 +#define LCD_COMMOD_6COM 3 +#define LCD_COMMOD_8COM 7 + +//BiasSelection +#define LCD_BMODE_DIV3 0 +#define LCD_BMODE_DIV4 ANA_REG6_LCD_BMODE + +//VLCDSelection +#define LCD_VLCD_0 0 +#define LCD_VLCD_INC60MV 1 +#define LCD_VLCD_INC120MV 2 +#define LCD_VLCD_INC180MV 3 +#define LCD_VLCD_INC240MV 4 +#define LCD_VLCD_INC300MV 5 +#define LCD_VLCD_DEC60MV 6 +#define LCD_VLCD_DEC120MV 7 +#define LCD_VLCD_DEC180MV 8 +#define LCD_VLCD_DEC240MV 9 +#define LCD_VLCD_DEC300MV 10 +#define LCD_VLCD_DEC360MV 11 +#define LCD_VLCD_DEC420MV 12 +#define LCD_VLCD_DEC480MV 13 +#define LCD_VLCD_DEC540MV 14 +#define LCD_VLCD_DEC600MV 15 + +/* Private macros ------------------------------------------------------------*/ +#define IS_LCD_TYPE(__TYPE__) (((__TYPE__) == LCD_TYPE_4COM) ||\ + ((__TYPE__) == LCD_TYPE_6COM) ||\ + ((__TYPE__) == LCD_TYPE_8COM)) + +#define IS_LCD_DRV(__DRV__) (((__DRV__) == LCD_DRV_300) ||\ + ((__DRV__) == LCD_DRV_600) ||\ + ((__DRV__) == LCD_DRV_150) ||\ + ((__DRV__) == LCD_DRV_200)) + +#define IS_LCD_FRQ(__FRQ__) (((__FRQ__) == LCD_FRQ_64H) ||\ + ((__FRQ__) == LCD_FRQ_128H) ||\ + ((__FRQ__) == LCD_FRQ_256H) ||\ + ((__FRQ__) == LCD_FRQ_512H)) + +#define IS_LCD_SWPR(__SWPR__) ((__SWPR__) <= 0xFFUL) + +#define IS_LCD_FBMODE(__FBMODE__) (((__FBMODE__) == LCD_FBMODE_BUFA) ||\ + ((__FBMODE__) == LCD_FBMODE_BUFAB) ||\ + ((__FBMODE__) == LCD_FBMODE_BUFABLANK)) + +#define IS_LCD_BKFILL(__BKFILL__) (((__BKFILL__) == LCD_BKFILL_1) || ((__BKFILL__) == LCD_BKFILL_0)) + +#define IS_LCD_BMODE(__BMODE__) (((__BMODE__) == LCD_BMODE_DIV3) ||\ + ((__BMODE__) == LCD_BMODE_DIV4)) + +#define IS_LCD_COMMOD(__COMMOD__) (((__COMMOD__) == LCD_COMMOD_4COM) ||\ + ((__COMMOD__) == LCD_COMMOD_6COM) ||\ + ((__COMMOD__) == LCD_COMMOD_8COM)) + +#define IS_LCD_VLCD(__VLCD__) (((__VLCD__) == LCD_VLCD_0) ||\ + ((__VLCD__) == LCD_VLCD_INC60MV) ||\ + ((__VLCD__) == LCD_VLCD_INC120MV) ||\ + ((__VLCD__) == LCD_VLCD_INC180MV) ||\ + ((__VLCD__) == LCD_VLCD_INC240MV) ||\ + ((__VLCD__) == LCD_VLCD_INC300MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC60MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC120MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC180MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC240MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC300MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC360MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC420MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC480MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC540MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC600MV)) + +/* Exported Functions ------------------------------------------------------- */ +/* LCD Exported Functions Group1: + (De)Initialization -------------------------*/ +void LCD_DeInit(void); +void LCD_StructInit(LCD_InitType *LCD_InitStruct); +void LCD_Init(LCD_InitType *InitStruct); +/* LCD Exported Functions Group1: + MISC Configuration -------------------------*/ +void LCD_Cmd(uint32_t NewState); +void LCD_IOConfig(uint32_t ComMode, uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2, uint32_t NewState); +void LCD_SetSEG(uint32_t SegCtrl0, uint32_t SegCtrl1, uint16_t SegCtrl2); +void LCD_BiasModeConfig(uint32_t BiasSelection); +uint32_t LCD_VoltageConfig(uint32_t VLCDSelection); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_LCD_H */ + +/*********************************** END OF FILE ******************************/ + diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_misc.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_misc.h new file mode 100644 index 0000000000..50585d58a1 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_misc.h @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * @file lib_misc.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief MISC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_MISC_H +#define __LIB_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//FlagMask +#define MISC_FLAG_LOCKUP MISC_SRAMINT_LOCKUP +#define MISC_FLAG_PIAC MISC_SRAMINT_PIAC +#define MISC_FLAG_HIAC MISC_SRAMINT_HIAC +#define MISC_FLAG_PERR MISC_SRAMINT_PERR +#define MISC_FLAG_Msk (MISC_FLAG_LOCKUP | MISC_FLAG_PIAC | MISC_FLAG_HIAC | MISC_FLAG_PERR) + +//MISC interrupt +#define MISC_INT_LOCK MISC_SRAMINIT_LOCKIE +#define MISC_INT_PIAC MISC_SRAMINIT_PIACIE +#define MISC_INT_HIAC MISC_SRAMINIT_HIACIE +#define MISC_INT_PERR MISC_SRAMINIT_PERRIE +#define MISC_INT_Msk (MISC_INT_LOCK | MISC_INT_PIAC | MISC_INT_HIAC | MISC_INT_PERR) + +//IR +#define MISC_IREN_TX0 MISC_IREN_UART0 +#define MISC_IREN_TX1 MISC_IREN_UART1 +#define MISC_IREN_TX2 MISC_IREN_UART2 +#define MISC_IREN_TX3 MISC_IREN_UART3 +#define MISC_IREN_TX4 MISC_IREN_UART4 +#define MISC_IREN_TX5 MISC_IREN_UART5 +#define MISC_IREN_Msk (0x3FUL) + +/* Private macros ------------------------------------------------------------*/ +#define IS_MISC_FLAGR(__FLAGR__) (((__FLAGR__) == MISC_FLAG_LOCKUP) ||\ + ((__FLAGR__) == MISC_FLAG_PIAC) ||\ + ((__FLAGR__) == MISC_FLAG_HIAC) ||\ + ((__FLAGR__) == MISC_FLAG_PERR)) + +#define IS_MISC_FLAGC(__FLAGC__) ((((__FLAGC__) & MISC_FLAG_Msk) != 0U) &&\ + (((__FLAGC__) & ~MISC_FLAG_Msk) == 0U)) + +#define IS_MISC_INT(__INT__) ((((__INT__) & MISC_INT_Msk) != 0U) &&\ + (((__INT__) &~MISC_INT_Msk) == 0U)) + +#define IS_MISC_IREN(__IREN__) ((((__IREN__) & MISC_IREN_Msk) != 0U) &&\ + (((__IREN__) & ~MISC_IREN_Msk) == 0U)) + +/* Exported Functions ------------------------------------------------------- */ +uint8_t MISC_GetFlag(uint32_t FlagMask); +void MISC_ClearFlag(uint32_t FlagMask); +void MISC_INTConfig(uint32_t INTMask, uint32_t NewState); +void MISC_SRAMParityCmd(uint32_t NewState); +uint32_t MISC_GetSRAMPEAddr(void); +uint32_t MISC_GetAPBErrAddr(void); +uint32_t MISC_GetAHBErrAddr(void); +void MISC_IRCmd(uint32_t IRx, uint32_t NewState); +void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow); +void MISC_HardFaultCmd(uint32_t NewState); +void MISC_LockResetCmd(uint32_t NewState); +void MISC_IRQLATConfig(uint8_t Latency); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_MISC_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pmu.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pmu.h new file mode 100644 index 0000000000..a8b7524773 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pmu.h @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file lib_pmu.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief PMU library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_PMU_H +#define __LIB_PMU_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/** + * Deep-sleep low-power configuration +*/ +typedef struct +{ + uint32_t COMP1Power; /* Comparator 1 power control */ + uint32_t COMP2Power; /* Comparator 2 power control */ + uint32_t TADCPower; /* Tiny ADC power control */ + uint32_t BGPPower; /* BGP power control */ + uint32_t AVCCPower; /* AVCC power control */ + uint32_t LCDPower; /* LCD controller power control */ + uint32_t VDCINDetector; /* VDCIN detector control */ + uint32_t VDDDetector; /* VDD detector control */ + uint32_t AHBPeriphralDisable; /* AHB Periphral clock disable selection */ + uint32_t APBPeriphralDisable; /* APB Periphral clock disable selection */ +} PMU_LowPWRTypeDef; + + +/* COMP1Power */ +#define PMU_COMP1PWR_ON (ANA_REG3_CMP1PDN) +#define PMU_COMP1PWR_OFF (0) +#define IS_PMU_COMP1PWR(__COMP1PWR__) (((__COMP1PWR__) == PMU_COMP1PWR_ON) ||\ + ((__COMP1PWR__) == PMU_COMP1PWR_OFF)) +/* COMP2Power */ +#define PMU_COMP2PWR_ON (ANA_REG3_CMP2PDN) +#define PMU_COMP2PWR_OFF (0) +#define IS_PMU_COMP2PWR(__COMP2PWR__) (((__COMP2PWR__) == PMU_COMP2PWR_ON) ||\ + ((__COMP2PWR__) == PMU_COMP2PWR_OFF)) +/* TADCPower */ +#define PMU_TADCPWR_ON (ANA_REGF_PDNADT) +#define PMU_TADCPWR_OFF (0) +#define IS_PMU_TADCPWR(__TADCPWR__) (((__TADCPWR__) == PMU_TADCPWR_ON) ||\ + ((__TADCPWR__) == PMU_TADCPWR_OFF)) +/* BGPPower */ +#define PMU_BGPPWR_ON (0) +#define PMU_BGPPWR_OFF (ANA_REG3_BGPPD) +#define IS_PMU_BGPPWR(__BGPPWR__) (((__BGPPWR__) == PMU_BGPPWR_ON) ||\ + ((__BGPPWR__) == PMU_BGPPWR_OFF)) +/* AVCCPower */ +#define PMU_AVCCPWR_ON (0) +#define PMU_AVCCPWR_OFF (ANA_REG8_PD_AVCCLDO) +#define IS_PMU_AVCCPWR(__AVCCPWR__) (((__AVCCPWR__) == PMU_AVCCPWR_ON) ||\ + ((__AVCCPWR__) == PMU_AVCCPWR_OFF)) +/* LCDPower */ +#define PMU_LCDPWER_ON (LCD_CTRL_EN) +#define PMU_LCDPWER_OFF (0) +#define IS_PMU_LCDPWER(__LCDPWER__) (((__LCDPWER__) == PMU_LCDPWER_ON) ||\ + ((__LCDPWER__) == PMU_LCDPWER_OFF)) +/* VDCINDetector */ +#define PMU_VDCINDET_ENABLE (0) +#define PMU_VDCINDET_DISABLE (ANA_REGA_PD_VDCINDET) +#define IS_PMU_VDCINDET(__VDCINDET__) (((__VDCINDET__) == PMU_VDCINDET_ENABLE) ||\ + ((__VDCINDET__) == PMU_VDCINDET_DISABLE)) + +/* VDDDetector */ +#define PMU_VDDDET_ENABLE (0) +#define PMU_VDDDET_DISABLE (ANA_REG9_PDDET) +#define IS_PMU_VDDDET(__VDDDET__) (((__VDDDET__) == PMU_VDDDET_ENABLE) ||\ + ((__VDDDET__) == PMU_VDDDET_DISABLE)) + +/* APBPeriphralDisable */ +#define PMU_APB_ALL (MISC2_PCLKEN_DMA \ + |MISC2_PCLKEN_I2C \ + |MISC2_PCLKEN_SPI1 \ + |MISC2_PCLKEN_UART0 \ + |MISC2_PCLKEN_UART1 \ + |MISC2_PCLKEN_UART2 \ + |MISC2_PCLKEN_UART3 \ + |MISC2_PCLKEN_UART4 \ + |MISC2_PCLKEN_UART5 \ + |MISC2_PCLKEN_ISO78160\ + |MISC2_PCLKEN_ISO78161\ + |MISC2_PCLKEN_TIMER \ + |MISC2_PCLKEN_MISC \ + |MISC2_PCLKEN_U32K0 \ + |MISC2_PCLKEN_U32K1 \ + |MISC2_PCLKEN_SPI2) +#define PMU_APB_DMA MISC2_PCLKEN_DMA +#define PMU_APB_I2C MISC2_PCLKEN_I2C +#define PMU_APB_SPI1 MISC2_PCLKEN_SPI1 +#define PMU_APB_UART0 MISC2_PCLKEN_UART0 +#define PMU_APB_UART1 MISC2_PCLKEN_UART1 +#define PMU_APB_UART2 MISC2_PCLKEN_UART2 +#define PMU_APB_UART3 MISC2_PCLKEN_UART3 +#define PMU_APB_UART4 MISC2_PCLKEN_UART4 +#define PMU_APB_UART5 MISC2_PCLKEN_UART5 +#define PMU_APB_ISO78160 MISC2_PCLKEN_ISO78160 +#define PMU_APB_ISO78161 MISC2_PCLKEN_ISO78161 +#define PMU_APB_TIMER MISC2_PCLKEN_TIMER +#define PMU_APB_MISC MISC2_PCLKEN_MISC +#define PMU_APB_U32K0 MISC2_PCLKEN_U32K0 +#define PMU_APB_U32K1 MISC2_PCLKEN_U32K1 +#define PMU_APB_SPI2 MISC2_PCLKEN_SPI2 +/* AHBPeriphralDisable */ +#define PMU_AHB_ALL (MISC2_HCLKEN_DMA \ + |MISC2_HCLKEN_GPIO \ + |MISC2_HCLKEN_LCD \ + |MISC2_HCLKEN_CRYPT) +#define PMU_AHB_DMA MISC2_HCLKEN_DMA +#define PMU_AHB_GPIO MISC2_HCLKEN_GPIO +#define PMU_AHB_LCD MISC2_HCLKEN_LCD +#define PMU_AHB_CRYPT MISC2_HCLKEN_CRYPT + +//PMU interrupt +#define PMU_INT_IOAEN PMU_CONTROL_INT_IOA_EN +#define PMU_INT_32K PMU_CONTROL_INT_32K_EN +#define PMU_INT_6M PMU_CONTROL_INT_6M_EN +#define PMU_INT_Msk (PMU_INT_IOAEN \ + |PMU_INT_32K \ + |PMU_INT_6M) +#define IS_PMU_INT(__INT__) ((((__INT__)&PMU_INT_Msk) != 0U) &&\ + (((__INT__)&(~PMU_INT_Msk)) == 0U)) + +//INTStatus +#define PMU_INTSTS_32K PMU_STS_INT_32K +#define PMU_INTSTS_6M PMU_STS_INT_6M +#define PMU_INTSTS_EXTRST PMU_STS_EXTRST +#define PMU_INTSTS_PORST PMU_STS_PORST +#define PMU_INTSTS_DPORST PMU_STS_DPORST +#define PMU_INTSTS_Msk (PMU_INTSTS_32K \ + |PMU_INTSTS_6M \ + |PMU_INTSTS_EXTRST \ + |PMU_INTSTS_PORST \ + |PMU_INTSTS_DPORST) +#define IS_PMU_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == PMU_INTSTS_32K) ||\ + ((__INTFLAG__) == PMU_INTSTS_6M) ||\ + ((__INTFLAG__) == PMU_INTSTS_EXTRST) ||\ + ((__INTFLAG__) == PMU_INTSTS_PORST) ||\ + ((__INTFLAG__) == PMU_INTSTS_DPORST)) + +#define IS_PMU_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&PMU_INTSTS_Msk) != 0U) &&\ + (((__INTFLAG__)&(~PMU_INTSTS_Msk)) == 0U)) + + + +//Status +#define PMU_STS_32K PMU_STS_EXIST_32K +#define PMU_STS_6M PMU_STS_EXIST_6M +#define IS_PMU_FLAG(__FLAG__) (((__FLAG__) == PMU_STS_32K) || ((__FLAG__) == PMU_STS_6M)) + +//Wakeup_Event +#define IOA_DISABLE (0) +#define IOA_RISING (1) +#define IOA_FALLING (2) +#define IOA_HIGH (3) +#define IOA_LOW (4) +#define IOA_EDGEBOTH (5) +#define IS_PMU_WAKEUP(__WAKEUP__) (((__WAKEUP__) == IOA_DISABLE) ||\ + ((__WAKEUP__) == IOA_RISING) ||\ + ((__WAKEUP__) == IOA_FALLING) ||\ + ((__WAKEUP__) == IOA_HIGH) ||\ + ((__WAKEUP__) == IOA_LOW) ||\ + ((__WAKEUP__) == IOA_EDGEBOTH)) + +/***** Wakeup_Event (PMU_SleepWKUSRC_Config_RTC) *****/ +#define PMU_RTCEVT_ACDONE RTC_INTSTS_INTSTS7 +#define PMU_RTCEVT_WKUCNT RTC_INTSTS_INTSTS6 +#define PMU_RTCEVT_MIDNIGHT RTC_INTSTS_INTSTS5 +#define PMU_RTCEVT_WKUHOUR RTC_INTSTS_INTSTS4 +#define PMU_RTCEVT_WKUMIN RTC_INTSTS_INTSTS3 +#define PMU_RTCEVT_WKUSEC RTC_INTSTS_INTSTS2 +#define PMU_RTCEVT_TIMEILLE RTC_INTSTS_INTSTS1 +#define PMU_RTCEVT_Msk (PMU_RTCEVT_ACDONE \ + |PMU_RTCEVT_WKUCNT \ + |PMU_RTCEVT_MIDNIGHT \ + |PMU_RTCEVT_WKUHOUR \ + |PMU_RTCEVT_WKUMIN \ + |PMU_RTCEVT_WKUSEC \ + |PMU_RTCEVT_TIMEILLE) +#define IS_PMU_RTCEVT(__RTCEVT__) ((((__RTCEVT__)&PMU_RTCEVT_Msk) != 0U) &&\ + (((__RTCEVT__)&(~PMU_RTCEVT_Msk)) == 0U)) + + +/***** BATDisc (PMU_BATDischargeConfig) *****/ +#define PMU_BATRTC_DISC ANA_REG6_BATRTCDISC +#define IS_PMU_BATRTCDISC(__BATRTCDISC__) ((__BATRTCDISC__) == PMU_BATRTC_DISC) + +/***** PowerThreshold (PMU_PowerAlarmTHConfig) *****/ +#define PMU_PWTH_4_5 ANA_REG8_VDDPVDSEL_0 +#define PMU_PWTH_4_2 ANA_REG8_VDDPVDSEL_1 +#define PMU_PWTH_3_9 ANA_REG8_VDDPVDSEL_2 +#define PMU_PWTH_3_6 ANA_REG8_VDDPVDSEL_3 +#define PMU_PWTH_3_2 ANA_REG8_VDDPVDSEL_4 +#define PMU_PWTH_2_9 ANA_REG8_VDDPVDSEL_5 +#define PMU_PWTH_2_6 ANA_REG8_VDDPVDSEL_6 +#define PMU_PWTH_2_3 ANA_REG8_VDDPVDSEL_7 + +#define IS_PMU_PWTH(__PWTH__) (((__PWTH__) == PMU_PWTH_4_5) ||\ + ((__PWTH__) == PMU_PWTH_4_2) ||\ + ((__PWTH__) == PMU_PWTH_3_9) ||\ + ((__PWTH__) == PMU_PWTH_3_6) ||\ + ((__PWTH__) == PMU_PWTH_3_2) ||\ + ((__PWTH__) == PMU_PWTH_2_9) ||\ + ((__PWTH__) == PMU_PWTH_2_6) ||\ + ((__PWTH__) == PMU_PWTH_2_3)) + +/***** RTCLDOSel (PMU_RTCLDOConfig) *****/ +#define PMU_RTCLDO_1_5 (0) +#define PMU_RTCLDO_1_2 ANA_REGA_RTCVSEL + +/***** StatusMask (PMU_GetPowerStatus) *****/ +#define PMU_PWRSTS_AVCCLV ANA_COMPOUT_AVCCLV +#define PMU_PWRSTS_VDCINDROP ANA_COMPOUT_VDCINDROP +#define PMU_PWRSTS_VDDALARM ANA_COMPOUT_VDDALARM + +/***** Debounce (PMU_PWRDropDEBConfig) *****/ +#define PMU_PWRDROP_DEB_0 ANA_CTRL_PWRDROPDEB_0 +#define PMU_PWRDROP_DEB_1 ANA_CTRL_PWRDROPDEB_1 +#define PMU_PWRDROP_DEB_2 ANA_CTRL_PWRDROPDEB_2 +#define PMU_PWRDROP_DEB_3 ANA_CTRL_PWRDROPDEB_3 +#define IS_PMU_PWRDROP_DEB(__DEB__) (((__DEB__) == PMU_PWRDROP_DEB_0) ||\ + ((__DEB__) == PMU_PWRDROP_DEB_1) ||\ + ((__DEB__) == PMU_PWRDROP_DEB_2) ||\ + ((__DEB__) == PMU_PWRDROP_DEB_3)) + +/***** RSTSource (PMU_GetRSTSource) *****/ +#define PMU_RSTSRC_EXTRST PMU_STS_EXTRST +#define PMU_RSTSRC_PORST PMU_STS_PORST +#define PMU_RSTSRC_DPORST PMU_STS_DPORST +//#define PMU_RSTSRC_WDTRST PMU_WDTSTS_WDTSTS +#define IS_PMU_RSTSRC(__RSTSRC__) (((__RSTSRC__) == PMU_RSTSRC_EXTRST) ||\ + ((__RSTSRC__) == PMU_RSTSRC_PORST) ||\ + ((__RSTSRC__) == PMU_RSTSRC_DPORST) ) + +/***** PMU_PDNDSleepConfig *****/ +//VDCIN_PDNS +#define PMU_VDCINPDNS_0 (0) +#define PMU_VDCINPDNS_1 (ANA_CTRL_PDNS) +#define IS_PMU_VDCINPDNS(__VDCINPDNS__) (((__VDCINPDNS__) == PMU_VDCINPDNS_0) ||\ + ((__VDCINPDNS__) == PMU_VDCINPDNS_1)) +//VDD_PDNS +#define PMU_VDDPDNS_0 (0) +#define PMU_VDDPDNS_1 (ANA_CTRL_PDNS2) +#define IS_PMU_VDDPDNS(__VDDPDNS__) (((__VDDPDNS__) == PMU_VDDPDNS_0) ||\ + ((__VDDPDNS__) == PMU_VDDPDNS_1)) + +/* Exported Functions ------------------------------------------------------- */ + +uint32_t PMU_EnterDSleepMode(void); +void PMU_EnterIdleMode(void); +uint32_t PMU_EnterSleepMode(void); + +void PMU_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t PMU_GetINTStatus(uint32_t INTMask); +void PMU_ClearINTStatus(uint32_t INTMask); + +uint8_t PMU_GetStatus(uint32_t Mask); +uint16_t PMU_GetIOAAllINTStatus(void); +uint16_t PMU_GetIOAINTStatus(uint16_t INTMask); +void PMU_ClearIOAINTStatus(uint16_t INTMask); + +void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event); + +uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); +uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); +#ifndef __GNUC__ +void PMU_EnterIdle_LowPower(void); +#endif +void PMU_SleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority); +void PMU_SleepWKUSRC_Config_RTC(uint32_t Wakeup_Event, uint32_t Priority); +void PMU_DeepSleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event); +void PMU_DeepSleepWKUSRC_Config_RTC(uint32_t Wakeup_Event); +void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS); + +/***** BGP functions *****/ +void PMU_BGP_Cmd(uint32_t NewState); + +/***** VDD functions *****/ +void PMU_VDDAlarmTHConfig(uint32_t PowerThreshold); +uint8_t PMU_GetVDDALARMStatus(void); +void PMU_VDDDetectorCmd(uint32_t NewState); + +/***** AVCC functions *****/ +void PMU_AVCC_Cmd(uint32_t NewState); +void PMU_AVCCOutput_Cmd(uint32_t NewState); +void PMU_AVCCLVDetector_Cmd(uint32_t NewState); +uint8_t PMU_GetAVCCLVStatus(void); + +/***** VDCIN functions *****/ +void PMU_VDCINDetector_Cmd(uint32_t NewState); +uint8_t PMU_GetVDCINDropStatus(void); + +/***** BAT functions *****/ +void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState); + +/***** Other functions *****/ +uint8_t PMU_GetModeStatus(void); +uint8_t PMU_GetPowerStatus(uint32_t StatusMask); +void PMU_PWRDropDEBConfig(uint32_t Debounce); +uint8_t PMU_GetRSTSource(uint32_t RSTSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_PMU_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pwm.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pwm.h new file mode 100644 index 0000000000..ce78befcd1 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pwm.h @@ -0,0 +1,178 @@ +/** + ****************************************************************************** + * @file lib_pwm.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief PWM library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_PWM_H +#define __LIB_PWM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t ClockDivision; + uint32_t Mode; + uint32_t ClockSource; +} PWM_BaseInitType; +//ClockDivision +#define PWM_CLKDIV_2 PWM_CTL_ID_DIV2 +#define PWM_CLKDIV_4 PWM_CTL_ID_DIV4 +#define PWM_CLKDIV_8 PWM_CTL_ID_DIV8 +#define PWM_CLKDIV_16 PWM_CTL_ID_DIV16 +//Mode +#define PWM_MODE_STOP PWM_CTL_MC_STOP +#define PWM_MODE_UPCOUNT PWM_CTL_MC_UP +#define PWM_MODE_CONTINUOUS PWM_CTL_MC_CONTINUE +#define PWM_MODE_UPDOWN PWM_CTL_MC_UPDOWN +//ClockSource +#define PWM_CLKSRC_APB PWM_CTL_TESL_APBDIV1 +#define PWM_CLKSRC_APBD128 PWM_CTL_TESL_APBDIV128 + +typedef struct +{ + uint32_t Period; + uint32_t OutMode; +} PWM_OCInitType; +//OUTMOD +#define PWM_OUTMOD_CONST PWM_CCTL_OUTMOD_CONST +#define PWM_OUTMOD_SET PWM_CCTL_OUTMOD_SET +#define PWM_OUTMOD_TOGGLE_RESET PWM_CCTL_OUTMOD_TOGGLE_RESET +#define PWM_OUTMOD_SET_RESET PWM_CCTL_OUTMOD_SET_RESET +#define PWM_OUTMOD_TOGGLE PWM_CCTL_OUTMOD_TOGGLE +#define PWM_OUTMOD_RESET PWM_CCTL_OUTMOD_RESET +#define PWM_OUTMOD_TOGGLE_SET PWM_CCTL_OUTMOD_TOGGLE_SET +#define PWM_OUTMOD_RESET_SET PWM_CCTL_OUTMOD_RESET_SET + +//PWM CHANNEL +#define PWM_CHANNEL_0 0 +#define PWM_CHANNEL_1 1 +#define PWM_CHANNEL_2 2 + +#define PWM_OSEL0_T0O0 (0<<0) +#define PWM_OSEL0_T0O1 (1<<0) +#define PWM_OSEL0_T0O2 (2<<0) +#define PWM_OSEL0_T1O0 (4<<0) +#define PWM_OSEL0_T1O1 (5<<0) +#define PWM_OSEL0_T1O2 (6<<0) +#define PWM_OSEL0_T2O0 (8<<0) +#define PWM_OSEL0_T2O1 (9<<0) +#define PWM_OSEL0_T2O2 (10<<0) +#define PWM_OSEL0_T3O0 (12<<0) +#define PWM_OSEL0_T3O1 (13<<0) +#define PWM_OSEL0_T3O2 (14<<0) +//outline +#define PWM_OLINE_0 1 +#define PWM_OLINE_1 2 +#define PWM_OLINE_2 4 +#define PWM_OLINE_3 8 +#define PWM_OLINE_Msk 0xF +//PWM output selection +#define PWM0_OUT0 PWM_OSEL0_T0O0 +#define PWM0_OUT1 PWM_OSEL0_T0O1 +#define PWM0_OUT2 PWM_OSEL0_T0O2 +#define PWM1_OUT0 PWM_OSEL0_T1O0 +#define PWM1_OUT1 PWM_OSEL0_T1O1 +#define PWM1_OUT2 PWM_OSEL0_T1O2 +#define PWM2_OUT0 PWM_OSEL0_T2O0 +#define PWM2_OUT1 PWM_OSEL0_T2O1 +#define PWM2_OUT2 PWM_OSEL0_T2O2 +#define PWM3_OUT0 PWM_OSEL0_T3O0 +#define PWM3_OUT1 PWM_OSEL0_T3O1 +#define PWM3_OUT2 PWM_OSEL0_T3O2 + +//Level +#define PWM_LEVEL_HIGH PWM_CCTL_OUT +#define PWM_LEVEL_LOW 0 + +/* Private macros ------------------------------------------------------------*/ +#define IS_PWM_CLKDIV(__CLKDIV__) (((__CLKDIV__) == PWM_CLKDIV_2) ||\ + ((__CLKDIV__) == PWM_CLKDIV_4) ||\ + ((__CLKDIV__) == PWM_CLKDIV_8) ||\ + ((__CLKDIV__) == PWM_CLKDIV_16)) + +#define IS_PWM_CNTMODE(__CNTMODE__) (((__CNTMODE__) == PWM_MODE_STOP) ||\ + ((__CNTMODE__) == PWM_MODE_UPCOUNT) ||\ + ((__CNTMODE__) == PWM_MODE_CONTINUOUS) ||\ + ((__CNTMODE__) == PWM_MODE_UPDOWN)) + +#define IS_PWM_CLKSRC(__CLKSRC__) (((__CLKSRC__) == PWM_CLKSRC_APB) ||\ + ((__CLKSRC__) == PWM_CLKSRC_APBD128)) + +#define IS_PWM_OUTMODE(__OUTMODE__) (((__OUTMODE__) == PWM_OUTMOD_CONST) ||\ + ((__OUTMODE__) == PWM_OUTMOD_SET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_TOGGLE_RESET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_SET_RESET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_TOGGLE) ||\ + ((__OUTMODE__) == PWM_OUTMOD_RESET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_TOGGLE_SET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_RESET_SET)) + +#define IS_PWM_CCR(__CCR__) ((__CCR__) < 0x10000U) + +#define IS_PWM_CHANNEL(__CHANNEL__) (((__CHANNEL__) == PWM_CHANNEL_0) ||\ + ((__CHANNEL__) == PWM_CHANNEL_1) ||\ + ((__CHANNEL__) == PWM_CHANNEL_2)) + +#define IS_PWM_OUTLINE(__OUTLINE__) ((((__OUTLINE__) & PWM_OLINE_Msk) != 0U) &&\ + (((__OUTLINE__) & ~PWM_OLINE_Msk) == 0U)) + +#define IS_PWM_OUTSEL(__OUTSEL__) (((__OUTSEL__) == PWM0_OUT0) ||\ + ((__OUTSEL__) == PWM0_OUT1) ||\ + ((__OUTSEL__) == PWM0_OUT2) ||\ + ((__OUTSEL__) == PWM1_OUT0) ||\ + ((__OUTSEL__) == PWM1_OUT1) ||\ + ((__OUTSEL__) == PWM1_OUT2) ||\ + ((__OUTSEL__) == PWM2_OUT0) ||\ + ((__OUTSEL__) == PWM2_OUT1) ||\ + ((__OUTSEL__) == PWM2_OUT2) ||\ + ((__OUTSEL__) == PWM3_OUT0) ||\ + ((__OUTSEL__) == PWM3_OUT1) ||\ + ((__OUTSEL__) == PWM3_OUT2)) + +#define IS_PWM_OUTLVL(__OUTLVL__) (((__OUTLVL__) == PWM_LEVEL_HIGH) ||\ + ((__OUTLVL__) == PWM_LEVEL_LOW)) + +/* Exported Functions ------------------------------------------------------- */ +/* PWM Exported Functions Group1: + Initialization ----------------------------*/ +void PWM_BaseInit(PWM_TypeDef *PWMx, PWM_BaseInitType *InitStruct); +void PWM_BaseStructInit(PWM_BaseInitType *InitStruct); +void PWM_OC0Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType); +void PWM_OC1Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType); +void PWM_OC2Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType); +void PWM_OCStructInit(PWM_OCInitType *OCInitType); +/* PWM Exported Functions Group2: + Interrupt ---------------------------------*/ +void PWM_BaseINTConfig(PWM_TypeDef *PWMx, uint32_t NewState); +uint8_t PWM_GetBaseINTStatus(PWM_TypeDef *PWMx); +void PWM_ClearBaseINTStatus(PWM_TypeDef *PWMx); +void PWM_ChannelINTConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState); +uint8_t PWM_GetChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel); +void PWM_ClearChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel); +/* PWM Exported Functions Group3: + MISC --------------------------------------*/ +void PWM_ClearCounter(PWM_TypeDef *PWMx); +void PWM_CCRConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint16_t Period); +//Compare output +void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine); +void PWM_OutputCmd(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState); +void PWM_SetOutLevel(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t Level); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_PWM_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_rtc.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_rtc.h new file mode 100644 index 0000000000..fff229bb2c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_rtc.h @@ -0,0 +1,198 @@ +/** + ****************************************************************************** + * @file lib_rtc.h + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief RTC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_RTC_H +#define __LIB_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* RTC Time struct */ +typedef struct +{ + uint32_t Year; + uint32_t Month; + uint32_t Date; + uint32_t WeekDay; + uint32_t Hours; + uint32_t Minutes; + uint32_t Seconds; +} RTC_TimeTypeDef; + +//INT +#define RTC_INT_CEILLE RTC_INTEN_INTEN8 +#define RTC_INT_ACDONE RTC_INTEN_INTEN7 +#define RTC_INT_WKUCNT RTC_INTEN_INTEN6 +#define RTC_INT_MIDNIGHT RTC_INTEN_INTEN5 +#define RTC_INT_WKUHOUR RTC_INTEN_INTEN4 +#define RTC_INT_WKUMIN RTC_INTEN_INTEN3 +#define RTC_INT_WKUSEC RTC_INTEN_INTEN2 +#define RTC_INT_TIMEILLE RTC_INTEN_INTEN1 +#define RTC_INT_Msk (0x1FEUL) + +//INTSTS +#define RTC_INTSTS_CEILLE RTC_INTSTS_INTSTS8 +#define RTC_INTSTS_ACDONE RTC_INTSTS_INTSTS7 +#define RTC_INTSTS_WKUCNT RTC_INTSTS_INTSTS6 +#define RTC_INTSTS_MIDNIGHT RTC_INTSTS_INTSTS5 +#define RTC_INTSTS_WKUHOUR RTC_INTSTS_INTSTS4 +#define RTC_INTSTS_WKUMIN RTC_INTSTS_INTSTS3 +#define RTC_INTSTS_WKUSEC RTC_INTSTS_INTSTS2 +#define RTC_INTSTS_TIMEILLE RTC_INTSTS_INTSTS1 +#define RTC_INTSTS_Msk (0x1FEUL) + +/* RTC AutoCal struct */ +typedef struct +{ + uint32_t Period; + uint32_t ATDelay; + uint32_t ATClockSource; + uint32_t ADCSource; +} RTC_AutCalType; +//ATDelay +#define RTC_ATDELAY_15MS RTC_ACCTRL_ACDEL_0 +#define RTC_ATDELAY_31MS RTC_ACCTRL_ACDEL_1 +#define RTC_ATDELAY_62MS RTC_ACCTRL_ACDEL_2 +#define RTC_ATDELAY_125MS RTC_ACCTRL_ACDEL_3 +//ATClockSource +#define RTC_ATCS_DISABLE RTC_ACCTRL_ACCLK_0 +#define RTC_ATCS_SEC RTC_ACCTRL_ACCLK_1 +#define RTC_ATCS_MIN RTC_ACCTRL_ACCLK_2 +#define RTC_ATCS_HOUR RTC_ACCTRL_ACCLK_3 +//ADCSource +#define RTC_ADCS_DATA (0) +#define RTC_ADCS_PORT RTC_ACCTRL_ADCSEL + +//CNTCLK +#define RTC_WKUCNT_RTCCLK RTC_WKUCNT_CNTSEL_0 +#define RTC_WKUCNT_2048 RTC_WKUCNT_CNTSEL_1 +#define RTC_WKUCNT_512 RTC_WKUCNT_CNTSEL_2 +#define RTC_WKUCNT_128 RTC_WKUCNT_CNTSEL_3 + +//Prescaler +#define RTC_CLKDIV_1 RTC_PSCA_PSCA_0 +#define RTC_CLKDIV_4 RTC_PSCA_PSCA_1 + +/* Private macros ------------------------------------------------------------*/ +#define IS_RTC_REGOP_STARTADDR(__STARTADDR__) (((__STARTADDR__) & 0x3U) == 0U) +/* Year 0 ~ 99 */ +#define IS_RTC_TIME_YEAR(__YEAR__) ((__YEAR__) < 0x9AU) +/* Month 1 ~ 12 */ +#define IS_RTC_TIME_MONTH(__MONTH__) (((__MONTH__) > 0x0U) && ((__MONTH__) < 0x13U)) +/* Date 1 ~ 31 */ +#define IS_RTC_TIME_DATE(__DATE__) (((__DATE__) > 0x0U) && ((__DATE__) < 0x32)) +/* Weekday 0 ~ 6 */ +#define IS_RTC_TIME_WEEKDAY(__WEEKDAY__) ((__WEEKDAY__) < 0x7U) +/* Hours 0 ~ 23 */ +#define IS_RTC_TIME_HOURS(__HOURS__) ((__HOURS__) < 0x24) +/* Minutes 0 ~ 59 */ +#define IS_RTC_TIME_MINS(__MINS__) ((__MINS__) < 0x5A) +/* Seconds 0 ~ 59 */ +#define IS_RTC_TIME_SECS(__SECS__) ((__SECS__) < 0x5A) + +#define IS_RTC_INT(__INT__) ((((__INT__) & RTC_INT_Msk) != 0U) &&\ + (((__INT__) & ~RTC_INT_Msk) == 0U)) + +#define IS_RTC_INTFLAGR(__INTFLAGR_) (((__INTFLAGR_) == RTC_INTSTS_CEILLE) ||\ + ((__INTFLAGR_) == RTC_INTSTS_ACDONE) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUCNT) ||\ + ((__INTFLAGR_) == RTC_INTSTS_MIDNIGHT) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUHOUR) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUMIN) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUSEC) ||\ + ((__INTFLAGR_) == RTC_INTSTS_TIMEILLE)) + +#define IS_RTC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & RTC_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~RTC_INTSTS_Msk) == 0U)) + +#define IS_RTC_AUTOCAL_RELOAD(__RELOAD__) (((__RELOAD__) == RTC_AUTORELOAD_DISABLE) ||\ + ((__RELOAD__) == RTC_AUTORELOAD_ENABLE)) + +#define IS_RTC_AUTOCAL_ATDLY(__ATDLY__) (((__ATDLY__) == RTC_ATDELAY_15MS) ||\ + ((__ATDLY__) == RTC_ATDELAY_31MS) ||\ + ((__ATDLY__) == RTC_ATDELAY_62MS) ||\ + ((__ATDLY__) == RTC_ATDELAY_125MS)) + +#define IS_RTC_AUTOCAL_ATCS(__ATCS__) (((__ATCS__) == RTC_ATCS_DISABLE) ||\ + ((__ATCS__) == RTC_ATCS_SEC) ||\ + ((__ATCS__) == RTC_ATCS_MIN) ||\ + ((__ATCS__) == RTC_ATCS_HOUR)) + +#define IS_RTC_AUTOCAL_ADCSRC(__ADCSRC__) (((__ADCSRC__) == RTC_ADCS_DATA) ||\ + ((__ADCSRC__) == RTC_ADCS_PORT)) + +#define IS_RTC_AUTOCAL_PERIOD(__PERIOD__) ((__PERIOD__) < 64U) + +#define IS_RTC_WKUSEC_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUMIN_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUHOUR_PERIOD(__PERIOD__) (((__PERIOD__) < 0x21U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUCNT_PERIOD(__PERIOD__) (((__PERIOD__) < 0x1000001U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUCNT_CNTSEL(__CNTSEL__) (((__CNTSEL__) == RTC_WKUCNT_RTCCLK) ||\ + ((__CNTSEL__) == RTC_WKUCNT_2048) ||\ + ((__CNTSEL__) == RTC_WKUCNT_512) ||\ + ((__CNTSEL__) == RTC_WKUCNT_128)) + +#define IS_RTC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == RTC_CLKDIV_1) ||\ + ((__CLKDIV__) == RTC_CLKDIV_4)) + +/* Exported Functions ------------------------------------------------------- */ +/* RTC Exported Functions Group1: + Time functions -----------------------------*/ +void RTC_SetTime(RTC_TimeTypeDef *sTime); +void RTC_GetTime(RTC_TimeTypeDef *gTime); +/* RTC Exported Functions Group2: + Registers operation functions --------------*/ +void RTC_WriteProtection(uint32_t NewState); +void RTC_WaitForSynchro(void); +void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len); +void RTC_ReadRegisters(uint32_t StartAddr, uint32_t *rBuffer, uint8_t Len); +/* RTC Exported Functions Group3: + Interrupt functions ------------------------*/ +void RTC_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t RTC_GetINTStatus(uint32_t FlagMask); +void RTC_ClearINTStatus(uint32_t FlagMask); +/* RTC Exported Functions Group4: + AutoCal functions --------------------------*/ +void RTC_AutoCalStructInit(RTC_AutCalType *RTCAC_InitStruct); +void RTC_AutoCalInit(RTC_AutCalType *InitStruct); +void RTC_TrigSourceConfig(uint32_t TrigSource, uint32_t Period); +uint32_t RTC_AutoCalCmd(uint32_t NewState); +void RTC_StartAutoCalManual(void); +void RTC_WaitForAutoCalManual(void); +uint8_t RTC_GetACBusyFlag(void); +/* RTC Exported Functions Group5: + Wake-up functions --------------------------*/ +void RTC_WKUSecondsConfig(uint8_t nPeriod); +void RTC_WKUMinutesConfig(uint8_t nPeriod); +void RTC_WKUHoursConfig(uint8_t nPeriod); +void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK); +uint32_t RTC_GetWKUCounterValue(void); +/* RTC Exported Functions Group6: + MISC functions -----------------------------*/ +void RTC_PrescalerConfig(uint32_t Prescaler); +void RTC_PLLDIVConfig(uint32_t nfrequency); +void RTC_PLLDIVOutputCmd(uint8_t NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_RTC_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_spi.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_spi.h new file mode 100644 index 0000000000..89c3568c6c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_spi.h @@ -0,0 +1,180 @@ +/** + ****************************************************************************** + * @file lib_spi.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief SPI library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_SPI_H +#define __LIB_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Mode; + uint32_t SPH; + uint32_t SPO; + uint32_t ClockDivision; + uint32_t CSNSoft; + uint32_t SWAP; +} SPI_InitType; +//Mode +#define SPI_MODE_MASTER 0 +#define SPI_MODE_SLAVE SPI_CTRL_MOD +//SPH +#define SPI_SPH_0 0 +#define SPI_SPH_1 SPI_CTRL_SCKPHA +//SPO +#define SPI_SPO_0 0 +#define SPI_SPO_1 SPI_CTRL_SCKPOL +//ClockDivision +#define SPI_CLKDIV_2 (0) +#define SPI_CLKDIV_4 (SPI_CTRL_SCKSEL_0) +#define SPI_CLKDIV_8 (SPI_CTRL_SCKSEL_1) +#define SPI_CLKDIV_16 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_1) +#define SPI_CLKDIV_32 (SPI_CTRL_SCKSEL_2) +#define SPI_CLKDIV_64 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_2) +#define SPI_CLKDIV_128 (SPI_CTRL_SCKSEL_1 | SPI_CTRL_SCKSEL_2) +//CSNSoft +#define SPI_CSNSOFT_ENABLE SPI_CTRL_CSGPIO +#define SPI_CSNSOFT_DISABLE 0 +//SWAP +#define SPI_SWAP_ENABLE SPI_CTRL_SWAP +#define SPI_SWAP_DISABLE 0 + +//INT +#define SPI_INT_TX (0x80000000|SPI_TXSTS_TXIEN) +#define SPI_INT_RX (0x40000000|SPI_RXSTS_RXIEN) + +//status +#define SPI_STS_TXIF (0x80000000|SPI_TXSTS_TXIF) +#define SPI_STS_TXEMPTY (0x80000000|SPI_TXSTS_TXEMPTY) +#define SPI_STS_TXFUR (0x80000000|SPI_TXSTS_TXFUR) +#define SPI_STS_RXIF (0x40000000|SPI_RXSTS_RXIF) +#define SPI_STS_RXFULL (0x40000000|SPI_RXSTS_RXFULL) +#define SPI_STS_RXFOV (0x40000000|SPI_RXSTS_RXFOV) +#define SPI_STS_BSY (0x20000000|SPI_MISC_BSY) +#define SPI_STS_RFF (0x20000000|SPI_MISC_RFF) +#define SPI_STS_RNE (0x20000000|SPI_MISC_RNE) +#define SPI_STS_TNF (0x20000000|SPI_MISC_TNF) +#define SPI_STS_TFE (0x20000000|SPI_MISC_TFE) + +//TXFLEV +#define SPI_TXFLEV_0 (0) +#define SPI_TXFLEV_1 (SPI_TXSTS_TXFLEV_0) +#define SPI_TXFLEV_2 (SPI_TXSTS_TXFLEV_1) +#define SPI_TXFLEV_3 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1) +#define SPI_TXFLEV_4 (SPI_TXSTS_TXFLEV_2) +#define SPI_TXFLEV_5 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_2) +#define SPI_TXFLEV_6 (SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2) +#define SPI_TXFLEV_7 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2) + +//RXFLEV +#define SPI_RXFLEV_0 (0) +#define SPI_RXFLEV_1 (SPI_RXSTS_RXFLEV_0) +#define SPI_RXFLEV_2 (SPI_RXSTS_RXFLEV_1) +#define SPI_RXFLEV_3 (SPI_RXSTS_RXFLEV_0 | SPI_RXSTS_RXFLEV_1) +#define SPI_RXFLEV_4 (SPI_RXSTS_RXFLEV_2) +#define SPI_RXFLEV_5 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_0) +#define SPI_RXFLEV_6 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1) +#define SPI_RXFLEV_7 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1 | SPI_RXSTS_RXFLEV_0) + + +/* Private macros ------------------------------------------------------------*/ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_MASTER) || ((__MODE__) == SPI_MODE_SLAVE)) + +#define IS_SPI_SPH(__SPH__) (((__SPH__) == SPI_SPH_0) || ((__SPH__) == SPI_SPH_1)) + +#define IS_SPI_SPO(__SPO__) (((__SPO__) == SPI_SPO_0) || ((__SPO__) == SPI_SPO_1)) + +#define IS_SPI_CLKDIV(__CLKDIV__) (((__CLKDIV__) == SPI_CLKDIV_2) ||\ + ((__CLKDIV__) == SPI_CLKDIV_4) ||\ + ((__CLKDIV__) == SPI_CLKDIV_8) ||\ + ((__CLKDIV__) == SPI_CLKDIV_16) ||\ + ((__CLKDIV__) == SPI_CLKDIV_32) ||\ + ((__CLKDIV__) == SPI_CLKDIV_64) ||\ + ((__CLKDIV__) == SPI_CLKDIV_128)) + +#define IS_SPI_CSN(__CSN__) (((__CSN__) == SPI_CSNSOFT_ENABLE) || ((__CSN__) == SPI_CSNSOFT_DISABLE)) + +#define IS_SPI_SWAP(__SWAP__) (((__SWAP__) == SPI_SWAP_ENABLE) || ((__SWAP__) == SPI_SWAP_DISABLE)) + +#define IS_SPI_INT(__INT__) ((((__INT__) & (SPI_INT_TX | SPI_INT_RX)) != 0U) &&\ + (((__INT__) & ~(SPI_INT_TX | SPI_INT_RX)) == 0U)) + +#define IS_SPI_STSR(__STSR__) (((__STSR__) == SPI_STS_TXIF) ||\ + ((__STSR__) == SPI_STS_TXEMPTY) ||\ + ((__STSR__) == SPI_STS_TXFUR) ||\ + ((__STSR__) == SPI_STS_RXFULL) ||\ + ((__STSR__) == SPI_STS_RXFOV) ||\ + ((__STSR__) == SPI_STS_BSY) ||\ + ((__STSR__) == SPI_STS_RFF) ||\ + ((__STSR__) == SPI_STS_RNE) ||\ + ((__STSR__) == SPI_STS_TNF) ||\ + ((__STSR__) == SPI_STS_TFE) ||\ + ((__STSR__) == SPI_STS_RXIF)) + +#define IS_SPI_STSC(__STSC__) ((((__STSC__) & (SPI_STS_TXIF | SPI_STS_RXIF)) != 0U) &&\ + (((__STSC__) & ~(SPI_STS_TXIF | SPI_STS_RXIF)) == 0U)) + +#define IS_SPI_TXFLEV(__TXFLEV__) (((__TXFLEV__) == SPI_TXFLEV_0) ||\ + ((__TXFLEV__) == SPI_TXFLEV_1) ||\ + ((__TXFLEV__) == SPI_TXFLEV_2) ||\ + ((__TXFLEV__) == SPI_TXFLEV_3) ||\ + ((__TXFLEV__) == SPI_TXFLEV_4) ||\ + ((__TXFLEV__) == SPI_TXFLEV_5) ||\ + ((__TXFLEV__) == SPI_TXFLEV_6) ||\ + ((__TXFLEV__) == SPI_TXFLEV_7)) + +#define IS_SPI_RXFLEV(__RXFLEV__) (((__RXFLEV__) == SPI_RXFLEV_0) ||\ + ((__RXFLEV__) == SPI_RXFLEV_1) ||\ + ((__RXFLEV__) == SPI_RXFLEV_2) ||\ + ((__RXFLEV__) == SPI_RXFLEV_3) ||\ + ((__RXFLEV__) == SPI_RXFLEV_4) ||\ + ((__RXFLEV__) == SPI_RXFLEV_5) ||\ + ((__RXFLEV__) == SPI_RXFLEV_6) ||\ + ((__RXFLEV__) == SPI_RXFLEV_7)) + +/* Exported Functions ------------------------------------------------------- */ +/* SPI Exported Functions Group1: + (De)Initialization -------------------------*/ +void SPI_DeviceInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitType *InitStruct); +void SPI_StructInit(SPI_InitType *InitStruct); +/* SPI Exported Functions Group2: + Interrupt (flag) ---------------------------*/ +void SPI_INTConfig(SPI_TypeDef *SPIx, uint32_t INTMask, uint32_t NewState); +uint8_t SPI_GetStatus(SPI_TypeDef *SPIx, uint32_t Status); +void SPI_ClearStatus(SPI_TypeDef *SPIx, uint32_t Status); +/* SPI Exported Functions Group3: + Transfer datas -----------------------------*/ +void SPI_SendData(SPI_TypeDef *SPIx, uint8_t ch); +uint8_t SPI_ReceiveData(SPI_TypeDef *SPIx); +/* SPI Exported Functions Group4: + MISC Configuration -------------------------*/ +void SPI_Cmd(SPI_TypeDef *SPIx, uint32_t NewState); +void SPI_TransmitFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel); +void SPI_ReceiveFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel); +uint8_t SPI_GetTransmitFIFOLevel(SPI_TypeDef *SPIx); +uint8_t SPI_GetReceiveFIFOLevel(SPI_TypeDef *SPIx); +void SPI_SmartModeCmd(SPI_TypeDef *SPIx, uint32_t NewState); +void SPI_OverWriteModeCmd(SPI_TypeDef *SPIx, uint32_t NewState); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_SPI_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_tmr.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_tmr.h new file mode 100644 index 0000000000..f377ae1746 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_tmr.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file lib_tmr.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Timer library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_TMR_H +#define __LIB_TMR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Period; + uint32_t ClockSource; + uint32_t EXTGT; +} TMR_InitType; +//ClockSource +#define TMR_CLKSRC_INTERNAL 0 +#define TMR_CLKSRC_EXTERNAL TMR_CTRL_EXTCLK +//ClockGate +#define TMR_EXTGT_DISABLE 0 +#define TMR_EXTGT_ENABLE TMR_CTRL_EXTEN + +/* Private macros ------------------------------------------------------------*/ +#define IS_TMR_CLKSRC(__CLKSRC__) (((__CLKSRC__) == TMR_CLKSRC_INTERNAL) || ((__CLKSRC__) == TMR_CLKSRC_EXTERNAL)) + +#define IS_TMR_EXTGT(__EXTGT__) (((__EXTGT__) == TMR_EXTGT_DISABLE) || ((__EXTGT__) == TMR_EXTGT_ENABLE)) + + +/* Exported Functions ------------------------------------------------------- */ +/* Timer Exported Functions Group1: + (De)Initialization ----------------------*/ +void TMR_DeInit(TMR_TypeDef *TMRx); +void TMR_Init(TMR_TypeDef *TMRx, TMR_InitType *InitStruct); +void TMR_StructInit(TMR_InitType *InitStruct); +/* Timer Exported Functions Group2: + Interrupt (flag) -------------------------*/ +void TMR_INTConfig(TMR_TypeDef *TMRx, uint32_t NewState); +uint8_t TMR_GetINTStatus(TMR_TypeDef *TMRx); +void TMR_ClearINTStatus(TMR_TypeDef *TMRx); +/* Timer Exported Functions Group3: + MISC Configuration -----------------------*/ +void TMR_Cmd(TMR_TypeDef *TMRx, uint32_t NewState); +uint32_t TMR_GetCurrentValue(TMR_TypeDef *TMRx); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_TMR_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_u32k.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_u32k.h new file mode 100644 index 0000000000..c396da28ed --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_u32k.h @@ -0,0 +1,142 @@ +/** + ****************************************************************************** + * @file lib_u32k.h + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief UART 32K library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_U32K_H +#define __LIB_U32K_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Debsel; + uint32_t Parity; + uint32_t WordLen; + uint32_t FirstBit; + uint32_t AutoCal; + uint32_t Baudrate; + uint32_t LineSel; +} U32K_InitType; +//Debsel +#define U32K_DEBSEL_0 U32K_CTRL0_DEBSEL_0 +#define U32K_DEBSEL_1 U32K_CTRL0_DEBSEL_1 +#define U32K_DEBSEL_2 U32K_CTRL0_DEBSEL_2 +#define U32K_DEBSEL_3 U32K_CTRL0_DEBSEL_3 +//Parity +#define U32K_PARITY_EVEN U32K_CTRL0_PMODE_EVEN +#define U32K_PARITY_ODD U32K_CTRL0_PMODE_ODD +#define U32K_PARITY_0 U32K_CTRL0_PMODE_0 +#define U32K_PARITY_1 U32K_CTRL0_PMODE_1 +#define U32K_PARITY_NONE 0 +//WordLen +#define U32K_WORDLEN_8B 0 +#define U32K_WORDLEN_9B U32K_CTRL0_MODE +//FirstBit +#define U32K_FIRSTBIT_LSB 0 +#define U32K_FIRSTBIT_MSB U32K_CTRL0_MSB +//AutoCal +#define U32K_AUTOCAL_ON 0 +#define U32K_AUTOCAL_OFF U32K_CTRL0_ACOFF +//Line +#define U32K_LINE_RX0 U32K_CTRL1_RXSEL_RX0 +#define U32K_LINE_RX1 U32K_CTRL1_RXSEL_RX1 +#define U32K_LINE_RX2 U32K_CTRL1_RXSEL_RX2 +#define U32K_LINE_RX3 U32K_CTRL1_RXSEL_RX3 + +//INT +#define U32K_INT_RXOV U32K_CTRL1_RXOVIE +#define U32K_INT_RXPE U32K_CTRL1_RXPEIE +#define U32K_INT_RX U32K_CTRL1_RXIE +#define U32K_INT_Msk (U32K_INT_RXOV \ + |U32K_INT_RXPE \ + |U32K_INT_RX) + +//INT Status +#define U32K_INTSTS_RXOV U32K_STS_RXOV +#define U32K_INTSTS_RXPE U32K_STS_RXPE +#define U32K_INTSTS_RX U32K_STS_RXIF +#define U32K_INTSTS_Msk (U32K_INTSTS_RXOV \ + |U32K_INTSTS_RXPE \ + |U32K_INTSTS_RX) + +//WKUMode +#define U32K_WKUMOD_RX 0 // Wake-up when receive data +#define U32K_WKUMOD_PC U32K_CTRL0_WKUMODE // Wake-up when receive data and parity/stop bit correct + +/* Private macros ------------------------------------------------------------*/ +#define IS_U32K_DEBSEL(__DEBSEL__) (((__DEBSEL__) == U32K_DEBSEL_0) ||\ + ((__DEBSEL__) == U32K_DEBSEL_1) ||\ + ((__DEBSEL__) == U32K_DEBSEL_2) ||\ + ((__DEBSEL__) == U32K_DEBSEL_3)) + +#define IS_U32K_PARITY(__PARITY__) (((__PARITY__) == U32K_PARITY_EVEN) ||\ + ((__PARITY__) == U32K_PARITY_ODD) ||\ + ((__PARITY__) == U32K_PARITY_0) ||\ + ((__PARITY__) == U32K_PARITY_1) ||\ + ((__PARITY__) == U32K_PARITY_NONE)) + +#define IS_U32K_WORDLEN(__WORDLEN__) (((__WORDLEN__) == U32K_WORDLEN_8B) || ((__WORDLEN__) == U32K_WORDLEN_9B)) + +#define IS_U32K_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == U32K_FIRSTBIT_LSB) || ((__FIRSTBIT__) == U32K_FIRSTBIT_MSB)) + +#define IS_U32K_AUTOCAL(__AUTOCAL__) (((__AUTOCAL__) == U32K_AUTOCAL_ON) || ((__AUTOCAL__) == U32K_AUTOCAL_OFF)) + +#define IS_U32K_LINE(__LINE__) (((__LINE__) == U32K_LINE_RX0) ||\ + ((__LINE__) == U32K_LINE_RX1) ||\ + ((__LINE__) == U32K_LINE_RX2) ||\ + ((__LINE__) == U32K_LINE_RX3)) + +#define IS_U32K_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9601UL) + +#define IS_U32K_INT(__INT__) ((((__INT__) & U32K_INT_Msk) != 0U) &&\ + (((__INT__) & ~U32K_INT_Msk) == 0U)) + +#define IS_U32K_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == U32K_INTSTS_RXOV) ||\ + ((__INTFLAGR__) == U32K_INTSTS_RXPE) ||\ + ((__INTFLAGR__) == U32K_INTSTS_RX)) + +#define IS_U32K_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & U32K_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~U32K_INTSTS_Msk) == 0U)) + +#define IS_U32K_WKUMODE(__WKUMODE__) (((__WKUMODE__) == U32K_WKUMOD_RX) || ((__WKUMODE__) == U32K_WKUMOD_PC)) + +/* Exported Functions ------------------------------------------------------- */ +/* U32K Exported Functions Group1: + (De)Initialization -----------------------*/ +void U32K_DeInit(U32K_TypeDef *U32Kx); +void U32K_Init(U32K_TypeDef *U32Kx, U32K_InitType *InitStruct); +void U32K_StructInit(U32K_InitType *InitStruct); +/* U32K Exported Functions Group2: + Interrupt (flag) configure ---------------*/ +void U32K_INTConfig(U32K_TypeDef *U32Kx, uint32_t INTMask, uint8_t NewState); +uint8_t U32K_GetINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask); +void U32K_ClearINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask); +/* U32K Exported Functions Group3: + Receive datas -----------------------------*/ +uint8_t U32K_ReceiveData(U32K_TypeDef *U32Kx); +/* U32K Exported Functions Group4: + MISC Configuration -------- ---------------*/ +void U32K_BaudrateConfig(U32K_TypeDef *U32Kx, uint32_t BaudRate); +void U32K_Cmd(U32K_TypeDef *U32Kx, uint32_t NewState); +void U32K_LineConfig(U32K_TypeDef *U32Kx, uint32_t Line); +void U32K_WKUModeConfig(U32K_TypeDef *U32Kx, uint32_t WKUMode); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_U32K_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_uart.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_uart.h new file mode 100644 index 0000000000..3839c2e67f --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_uart.h @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file lib_uart.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief UART library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_UART_H +#define __LIB_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//UART Init struct +typedef struct +{ + uint32_t Mode; + uint32_t Parity; + uint32_t WordLen; + uint32_t FirstBit; + uint32_t Baudrate; +} UART_InitType; +//Mode +#define UART_MODE_RX UART_CTRL_RXEN +#define UART_MODE_TX UART_CTRL_TXEN +#define UART_MODE_OFF 0 +#define UART_MODE_Msk (UART_CTRL_RXEN | UART_CTRL_TXEN) +//Parity +#define UART_PARITY_EVEN UART_CTRL2_PMODE_EVEN +#define UART_PARITY_ODD UART_CTRL2_PMODE_ODD +#define UART_PARITY_0 UART_CTRL2_PMODE_0 +#define UART_PARITY_1 UART_CTRL2_PMODE_1 +#define UART_PARITY_NONE 0 +//WordLen +#define UART_WORDLEN_8B 0 +#define UART_WORDLEN_9B UART_CTRL2_MODE +//FirstBit +#define UART_FIRSTBIT_LSB 0 +#define UART_FIRSTBIT_MSB UART_CTRL2_MSB + +//UART Configration Information struct +typedef struct +{ + uint32_t Mode_Transmit :1; //1: TX Enable; 0: TX Disable + uint32_t Mode_Receive :1; //1: RX Enable; 0: RX Disable + uint32_t Baudrate; //The value of current budrate + uint8_t Parity; //0: parity bit=0; 1: parity bit=1; 2: Even parity; 3:Odd parity + uint8_t WordLen; //8: data bits=8; 9: data bits=9 + uint8_t FirstBit; //0: LSB transmit first; 1: MSB transmit first +} UART_ConfigINFOType; + +//status +#define UART_FLAG_RXPARITY UART_STATE_RXPSTS +#define UART_FLAG_TXDONE UART_STATE_TXDONE +#define UART_FLAG_RXPE UART_STATE_RXPE +#define UART_FLAG_RXOV UART_STATE_RXOV +#define UART_FLAG_TXOV UART_STATE_TXOV +#define UART_FLAG_RXFULL UART_STATE_RXFULL +#define UART_FLAG_RCMsk (UART_FLAG_TXDONE \ + |UART_FLAG_RXPE \ + |UART_FLAG_RXOV \ + |UART_STATE_RXFULL\ + |UART_FLAG_TXOV) + +//interrupt +#define UART_INT_TXDONE UART_CTRL_TXDONEIE +#define UART_INT_RXPE UART_CTRL_RXPEIE +#define UART_INT_RXOV UART_CTRL_RXOVIE +#define UART_INT_TXOV UART_CTRL_TXOVIE +#define UART_INT_RX UART_CTRL_RXIE +#define UART_INT_Msk (UART_INT_TXDONE \ + |UART_INT_RXPE \ + |UART_INT_RXOV \ + |UART_INT_TXOV \ + |UART_INT_RX) + +//INTStatus +#define UART_INTSTS_TXDONE UART_INTSTS_TXDONEIF +#define UART_INTSTS_RXPE UART_INTSTS_RXPEIF +#define UART_INTSTS_RXOV UART_INTSTS_RXOVIF +#define UART_INTSTS_TXOV UART_INTSTS_TXOVIF +#define UART_INTSTS_RX UART_INTSTS_RXIF +#define UART_INTSTS_Msk (UART_INTSTS_TXDONE \ + |UART_INTSTS_RXPE \ + |UART_INTSTS_RXOV \ + |UART_INTSTS_TXOV \ + |UART_INTSTS_RX) + +/* Private macros ------------------------------------------------------------*/ +#define IS_UART_MODE(__MODE__) (((((__MODE__) & UART_MODE_Msk) != 0U) && (((__MODE__) & ~UART_MODE_Msk) == 0U)) ||\ + ((__MODE__) == UART_MODE_OFF)) + +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_EVEN) ||\ + ((__PARITY__) == UART_PARITY_ODD) ||\ + ((__PARITY__) == UART_PARITY_0) ||\ + ((__PARITY__) == UART_PARITY_1) ||\ + ((__PARITY__) == UART_PARITY_NONE)) + +#define IS_UART_WORDLEN(__WORDLEN__) (((__WORDLEN__) == UART_WORDLEN_8B) ||\ + ((__WORDLEN__) == UART_WORDLEN_9B)) + +#define IS_UART_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == UART_FIRSTBIT_LSB) ||\ + ((__FIRSTBIT__) == UART_FIRSTBIT_MSB)) + +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 0x100000UL) + +#define IS_UART_FLAGR(__FLAGR__) (((__FLAGR__) == UART_FLAG_RXPARITY) ||\ + ((__FLAGR__) == UART_FLAG_TXDONE) ||\ + ((__FLAGR__) == UART_FLAG_RXPE) ||\ + ((__FLAGR__) == UART_FLAG_RXOV) ||\ + ((__FLAGR__) == UART_FLAG_TXOV) ||\ + ((__FLAGR__) == UART_FLAG_RXFULL)) + +#define IS_UART_FLAGC(__FLAGC__) ((((__FLAGC__) & UART_FLAG_RCMsk) != 0U) &&\ + (((__FLAGC__) & ~UART_FLAG_RCMsk) == 0U)) + +#define IS_UART_INT(__INT__) ((((__INT__) & UART_INT_Msk) != 0U) &&\ + (((__INT__) & ~UART_INT_Msk) == 0U)) + +#define IS_UART_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == UART_INTSTS_TXDONE) ||\ + ((__INTFLAGR__) == UART_INTSTS_RXPE) ||\ + ((__INTFLAGR__) == UART_INTSTS_RXOV) ||\ + ((__INTFLAGR__) == UART_INTSTS_TXOV) ||\ + ((__INTFLAGR__) == UART_INTSTS_RX)) + +#define IS_UART_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & UART_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~UART_INTSTS_Msk) == 0U)) + +/* Exported Functions ------------------------------------------------------- */ +/* UART Exported Functions Group1: + Initialization and functions --------------*/ +void UART_DeInit(UART_TypeDef *UARTx); +void UART_Init(UART_TypeDef *UARTx, UART_InitType *InitStruct); +void UART_StructInit(UART_InitType *InitStruct); +/* UART Exported Functions Group2: + (Interrupt) Flag --------------------------*/ +uint8_t UART_GetFlag(UART_TypeDef *UARTx, uint32_t FlagMask); +void UART_ClearFlag(UART_TypeDef *UARTx, uint32_t FlagMask); +void UART_INTConfig(UART_TypeDef *UARTx, uint32_t INTMask, uint8_t NewState); +uint8_t UART_GetINTStatus(UART_TypeDef *UARTx, uint32_t INTMask); +void UART_ClearINTStatus(UART_TypeDef *UARTx, uint32_t INTMask); +/* UART Exported Functions Group3: + Transfer datas ----------------------------*/ +void UART_SendData(UART_TypeDef *UARTx, uint8_t ch); +uint8_t UART_ReceiveData(UART_TypeDef *UARTx); +/* UART Exported Functions Group4: + MISC Configuration ------------------------*/ +void UART_BaudrateConfig(UART_TypeDef *UARTx, uint32_t BaudRate); +void UART_Cmd(UART_TypeDef *UARTx, uint32_t Mode, uint32_t NewState); +void UART_GetConfigINFO(UART_TypeDef *UARTx, UART_ConfigINFOType *ConfigInfo); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_UART_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_version.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_version.h new file mode 100644 index 0000000000..0bc51b303d --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_version.h @@ -0,0 +1,36 @@ +/** +******************************************************************************* +* @file lib_version.h +* @author Application Team +* @version V4.5.0 +* @date 2019-05-14 +* @brief Version library. +*******************************************************************************/ + +#ifndef __LIB_VERSION_H +#define __LIB_VERSION_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +#define DRIVER_VERSION(major,minor) (((major) << 8) | (minor)) + +/* Exported Functions ------------------------------------------------------- */ + +/** + * @brief Read receive data register. + * @param None + * @retval Version value + */ +uint16_t Target_GetDriveVersion(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_VERSION_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_wdt.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_wdt.h new file mode 100644 index 0000000000..ab02db6473 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_wdt.h @@ -0,0 +1,46 @@ +/** + ****************************************************************************** + * @file lib_wdt.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief WDT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_WDT_H +#define __LIB_WDT_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +#define WDT_2_SECS PMU_WDTEN_WDTSEL_0 +#define WDT_1_SECS PMU_WDTEN_WDTSEL_1 +#define WDT_0_5_SECS PMU_WDTEN_WDTSEL_2 +#define WDT_0_25_SECS PMU_WDTEN_WDTSEL_3 + +/* Private macros ------------------------------------------------------------*/ +#define IS_WDT_PERIOD(__PERIOD__) (((__PERIOD__) == WDT_2_SECS) ||\ + ((__PERIOD__) == WDT_1_SECS) ||\ + ((__PERIOD__) == WDT_0_5_SECS) ||\ + ((__PERIOD__) == WDT_0_25_SECS)) + +/* Exported Functions ------------------------------------------------------- */ +void WDT_Enable(void); +void WDT_Disable(void); +void WDT_Clear(void); +void WDT_SetPeriod(uint32_t period); +uint16_t WDT_GetCounterValue(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_WDT_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc.c new file mode 100644 index 0000000000..c37213d70c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc.c @@ -0,0 +1,977 @@ +/** + ****************************************************************************** + * @file lib_adc.c + * @author Application Team + * @version V4.6.0 + * @date 2019-06-18 + * @brief ADC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_adc.h" + +extern __IO uint32_t ana_reg3_tmp; +#define ANA_REG1_RSTValue (0U) +#define ANA_ADCCTRL_RSTValue (0U) + +/** + * @brief Initializes ADC peripheral registers to their default reset values. + * @note 1. Disable ADC + 2. Disable ADC overall bias current trim + 3. Disable resistor/cap division. + 4. Disable ADC auto/manual done interrupt + 5. ANA_ADCCTRL(register) write default value. + * @param None + * @retval None + */ +void ADC_DeInit(void) +{ + /* Power down ADC */ + ana_reg3_tmp &= ~ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + /* Disable resistor/cap division. */ + ANA->REG1 = ANA_REG1_RSTValue; + /* Disable interrupt, Clear interrupt flag */ + ANA->INTEN &= ~(ANA_INTEN_INTEN0 | ANA_INTEN_INTEN1); + ANA->INTSTS = (ANA_INTSTS_INTSTS0 | ANA_INTSTS_INTSTS1); + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = ANA_ADCCTRL_RSTValue; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct: pointer to an ADCInitType structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADCInitType* ADC_InitStruct) +{ + /*--------------- Reset ADC init structure parameters values ---------------*/ + /* Initialize the ClockSource member */ + ADC_InitStruct->ClockSource = ADC_CLKSRC_RCH; + /* Initialize the Channel member */ + ADC_InitStruct->Channel = ADC_CHANNEL0; + /* Initialize the ClockDivider member */ + ADC_InitStruct->ClockDivider = ADC_CLKDIV_1; + /* Initialize the ConvMode member */ + ADC_InitStruct->ConvMode = ADC_CONVMODE_SINGLECHANNEL; + /* Initialize the TrigMode member */ + ADC_InitStruct->TrigMode = ADC_TRIGMODE_MANUAL; +} + +/** + * @brief ADC initialization. + * @param ADC_InitStruct: + TrigMode: + ADC_TRIGMODE_AUTO + ADC_TRIGMODE_MANUAL + ConvMode: + ADC_CONVMODE_SINGLECHANNEL + ADC_CONVMODE_MULTICHANNEL + ClockSource: + ADC_CLKSRC_RCH + ADC_CLKSRC_PLLL + ClockDivider: + ADC_CLKDIV_1 + ADC_CLKDIV_2 + ADC_CLKDIV_3 + ADC_CLKDIV_4 + ADC_CLKDIV_5 + ADC_CLKDIV_6 + ADC_CLKDIV_7 + ADC_CLKDIV_8 + ADC_CLKDIV_9 + ADC_CLKDIV_10 + ADC_CLKDIV_11 + ADC_CLKDIV_12 + ADC_CLKDIV_13 + ADC_CLKDIV_14 + ADC_CLKDIV_15 + ADC_CLKDIV_16 + Channel:(be valid when ConvMode is ADC_CONVMODE_SINGLECHANNEL) + ADC_CHANNEL0 + ADC_CHANNEL1 + ADC_CHANNEL2 + ADC_CHANNEL3 + ADC_CHANNEL4 + ADC_CHANNEL5 + ADC_CHANNEL6 + ADC_CHANNEL7 + ADC_CHANNEL8 + ADC_CHANNEL9 + ADC_CHANNEL10 + ADC_CHANNEL11 + + * @retval None + */ +void ADC_Init(ADCInitType* ADC_InitStruct) +{ + uint32_t tmp = 0; + + /* Check parameters */ + assert_parameters(IS_ADC_TRIGMODE(ADC_InitStruct->TrigMode)); + assert_parameters(IS_ADC_CONVMODE(ADC_InitStruct->ConvMode)); + assert_parameters(IS_ADC_CLKDIV(ADC_InitStruct->ClockDivider)); + assert_parameters(IS_ADC_CLKSRC(ADC_InitStruct->ClockSource)); + + tmp = ANA->ADCCTRL; + tmp &= ~(ANA_ADCCTRL_AMODE \ + |ANA_ADCCTRL_MMODE \ + |ANA_ADCCTRL_CLKSEL \ + |ANA_ADCCTRL_CLKDIV \ + |ANA_ADCCTRL_AEN \ + |ANA_ADCCTRL_MCH \ + |ANA_ADCCTRL_ACH); + tmp |= (ADC_InitStruct->ClockDivider | ADC_InitStruct->ClockSource); + + if(ADC_InitStruct->TrigMode == ADC_TRIGMODE_AUTO) //Auto mode + { + if(ADC_InitStruct->ConvMode == ADC_CONVMODE_SINGLECHANNEL) //signal channel + { + assert_parameters(IS_ADC_CHANNEL(ADC_InitStruct->Channel)); + tmp &= (~ANA_ADCCTRL_ACH); + tmp |= (ADC_InitStruct->Channel << ANA_ADCCTRL_ACH_Pos); + } + else //multi channels + { + tmp |= ANA_ADCCTRL_AMODE; + } + } + else // Manual mode + { + if(ADC_InitStruct->ConvMode == ADC_CONVMODE_SINGLECHANNEL) //signal channel + { + assert_parameters(IS_ADC_CHANNEL(ADC_InitStruct->Channel)); + tmp &= (~ANA_ADCCTRL_MCH); + tmp |= (ADC_InitStruct->Channel << ANA_ADCCTRL_MCH_Pos); + } + else //multi channels + { + tmp |= ANA_ADCCTRL_MMODE; + } + } + + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief Calculate ADC voltage value(uint:V) via ADC original data. + * @param [in]Mode: + * ADC_3V_EXTERNAL_NODIV + * ADC_3V_EXTERNAL_RESDIV + * ADC_3V_EXTERNAL_CAPDIV + * ADC_3V_VDD_RESDIV + * ADC_3V_VDD_CAPDIV + * ADC_3V_BATRTC_RESDIV + * ADC_3V_BATRTC_CAPDIV + * ADC_5V_EXTERNAL_NODIV + * ADC_5V_EXTERNAL_RESDIV + * ADC_5V_EXTERNAL_CAPDIV + * ADC_5V_VDD_RESDIV + * ADC_5V_VDD_CAPDIV + * ADC_5V_BATRTC_RESDIV + * ADC_5V_BATRTC_CAPDIV + * @param [in]adc_data: The ADC original data + * @param [out]Voltage: The pointer of voltage value calculated by this function + * @retval 1 NVR checksum error. + 0 Function successed. + */ +uint32_t ADC_CalculateVoltage(uint32_t Mode, int16_t adc_data, float *Voltage) +{ + NVR_ADCVOLPARA parameter; + NVR_BATMEARES BAT_OffsetInfo; + + /* Check parameters */ + assert_parameters(IS_ADCVOL_MODE(Mode)); + + if (NVR_GetADCVoltageParameter(Mode, ¶meter)) + { + if ((Mode&0xFUL) > 2UL) /* VDD or BATRTC channel */ + { + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return 1; + } + else + { + if (((Mode&0xFUL) == 3UL) || ((Mode&0xFUL) == 5UL)) /* VDD/BATRTC, Resistive */ + { + *Voltage = (float)(0.00015392*(float)adc_data + 0.06667986) + BAT_OffsetInfo.BATRESResult; + } + else /* VDD/BATRTC, Capacitive */ + { + *Voltage = (float)(0.00014107*(float)adc_data - 0.00699515) + BAT_OffsetInfo.BATCAPResult; + } + } + } + else /* External channel */ + { + if (Mode & 0x100UL) /* Power supply: 5V */ + { + if ((Mode&0xFUL) == 0UL) /* No divider */ + { + *Voltage = (float)(0.00003678*(float)adc_data + 0.00235783); + } + else if ((Mode&0xFUL) == 1UL) /* Resistive */ + { + *Voltage = (float)(0.00016129*(float)adc_data + 0.00673599); + } + else /* Capacitive */ + { + *Voltage = (float)(0.00014076*(float)adc_data - 0.00753319); + } + } + else /* Power supply: 3.3V */ + { + if ((Mode&0xFUL) == 0UL) /* No divider */ + { + *Voltage = (float)(0.00003680*(float)adc_data + 0.00205011); + } + else if ((Mode&0xFUL) == 1UL) /* Resistive */ + { + *Voltage = (float)(0.00016425*(float)adc_data + 0.03739179); + } + else /* Capacitive */ + { + *Voltage = (float)(0.00014051*(float)adc_data - 0.00023322); + } + } + } + } + else + { + *Voltage = (float)(parameter.aParameter*(float)adc_data + parameter.bParameter); + } + + return 0; +} + +/** + * @brief Get VDD Voltage(takes 244us). + * @note This function costs about 170us when SystemClock is 26M. + * ADC data refresh time is 117us. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(VDD channel 1) + * - ADC clock: 3.2M + * - Skip samples: Skip 2 samples + * - Down sampling rate: 1/64 + * @param [in]Division + ADC_BAT_CAPDIV (Cap division 1/4) + ADC_BAT_RESDIV (Resistance division 1/4) + [out]CalResults.VDDVoltage The value of VDD Voltage + [out]CalResults.BATRTCVoltage is ignored + [out]CalResults.Temperature is ignored + * @retval 1 NVR BAT-offset information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetVDDVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults) +{ + float Vbatcap; + float Vbatres; + NVR_BATMEARES BAT_OffsetInfo; + int16_t data; + + assert_parameters(IS_ADC_BATDIV(Division)); + + /* Get NVR BAT offset information */ + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return (1); + } + else + { + Vbatcap = BAT_OffsetInfo.BATCAPResult; + Vbatres = BAT_OffsetInfo.BATRESResult; + } + + /* ADC initialization */ + ADC_DeInit(); + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = 0x06C00101; + + /* Enable division */ + ANA->REG1 |= Division; + /* Enable ADC */ + ana_reg3_tmp |= ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Start a manual ADC conversion */ + ADC_StartManual(); + /* Waiting last operation done */ + ADC_WaitForManual(); + + data = ANA->ADCDATA1; + + /* Calculate the voltage of VDD */ + if (Division & ADC_BAT_CAPDIV) + { + CalResults->VDDVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap; + } + else + { + CalResults->VDDVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres; + } + + /* ADC resource release */ + ADC_DeInit(); + + return (0); +} + +/** + * @brief Get VDD Voltage(takes 3.3ms). + * @note This function costs about 3.3ms when SystemClock is 26M. + * ADC data refresh time is about 3.2ms. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(VDD channel 1) + * - ADC clock: 1.6M + * - Skip samples: Skip first 4 samples + * - Down sampling rate: 1/512 + * @param [in]Division + ADC_BAT_CAPDIV (Cap division 1/4) + ADC_BAT_RESDIV (Resistance division 1/4) + [out]CalResults.VDDVoltage The value of VDD Voltage + [out]CalResults.BATRTCVoltage is ignored + [out]CalResults.Temperature is ignored + * @retval 1 NVR BAT-offset information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetVDDVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults) +{ + float Vbatcap; + float Vbatres; + NVR_BATMEARES BAT_OffsetInfo; + ADCInitType ADC_InitStruct; + int16_t data; + + assert_parameters(IS_ADC_BATDIV(Division)); + + /* Get NVR BAT offset information */ + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return (1); + } + else + { + Vbatcap = BAT_OffsetInfo.BATCAPResult; + Vbatres = BAT_OffsetInfo.BATRESResult; + } + + /* ADC initialization */ + ADC_DeInit(); + ADC_InitStruct.TrigMode = ADC_TRIGMODE_MANUAL; + ADC_InitStruct.ConvMode = ADC_CONVMODE_SINGLECHANNEL; + ADC_InitStruct.Channel = ADC_CHANNEL1; + ADC_InitStruct.ClockDivider = ADC_CLKDIV_4; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_Init(&ADC_InitStruct); + + /* Enable division */ + ANA->REG1 |= Division; + /* Enable ADC */ + ana_reg3_tmp |= ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Start a manual ADC conversion */ + ADC_StartManual(); + /* Waiting last operation done */ + ADC_WaitForManual(); + + + data = ANA->ADCDATA1; + + /* Calculate the voltage of VDD */ + if (Division & ADC_BAT_CAPDIV) + { + CalResults->VDDVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap; + } + else + { + CalResults->VDDVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres; + } + + /* ADC resource release */ + ADC_DeInit(); + + return (0); +} + +/** + * @brief Get BATRTC Voltage(takes 244us). + * @note This function takes about 244us when SystemClock is 26M. + * ADC data refresh time is 117us. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(BATRTC channel 2) + * - ADC clock: 3.2M + * - Skip samples: Skip 2 samples + * - Down sampling rate: 1/64 + * @param [in]Division + ADC_BAT_CAPDIV (Cap division 1/4) + ADC_BAT_RESDIV (Resistance division 1/4) + [out]CalResults.VDDVoltage is ignored + [out]CalResults.BATRTCVoltage The value of BATRTC Voltage + [out]CalResults.Temperature is ignored + * @retval 1 NVR BAT-offset or BGP-gain information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetBATRTCVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults) +{ + float Vbatcap; + float Vbatres; + + NVR_BATMEARES BAT_OffsetInfo; + int16_t data; + + assert_parameters(IS_ADC_BATDIV(Division)); + + /* Get NVR BAT offset information */ + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return (1); + } + else + { + Vbatcap = BAT_OffsetInfo.BATCAPResult; + Vbatres = BAT_OffsetInfo.BATRESResult; + } + + /* ADC initialization */ + ADC_DeInit(); + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = 0x06C00102; + /* Enable division */ + ANA->REG1 |= Division; + /* Enable ADC */ + ana_reg3_tmp |= ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Start a manual ADC conversion */ + ADC_StartManual(); + /* Waiting last operation done */ + ADC_WaitForManual(); + + data = ANA->ADCDATA2; + + /* Calculate the voltage of BAT1 */ + if (Division & ADC_BAT_CAPDIV) + { + CalResults->BATRTCVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap; + } + else + { + CalResults->BATRTCVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres; + } + /* ADC resource release */ + ADC_DeInit(); + + return (0); +} + +/** + * @brief Get BATRTC Voltage(takes 3.3ms). + * @note This function takes about 3.3ms when SystemClock is 26M. + * ADC data refresh time is about 3.2ms. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(BATRTC channel 2) + * - ADC clock: 1.6M + * - Skip samples: Skip first 4 samples + * - Down sampling rate: 1/512 + * @param [in]Division + ADC_BAT_CAPDIV (Capacitance division 1/4) + ADC_BAT_RESDIV (Resistance division 1/4) + [out]CalResults.VDDVoltage is ignored + [out]CalResults.BATRTCVoltage The value of BATRTC Voltage + [out]CalResults.Temperature is ignored + * @retval 1 NVR BAT-offset information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetBATRTCVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults) +{ + float Vbatcap; + float Vbatres; + NVR_BATMEARES BAT_OffsetInfo; + ADCInitType ADC_InitStruct; + int16_t data; + + assert_parameters(IS_ADC_BATDIV(Division)); + + /* Get NVR BAT offset information */ + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return (1); + } + else + { + Vbatcap = BAT_OffsetInfo.BATCAPResult; + Vbatres = BAT_OffsetInfo.BATRESResult; + } + + /* ADC initialization */ + ADC_DeInit(); + ADC_InitStruct.TrigMode = ADC_TRIGMODE_MANUAL; + ADC_InitStruct.ConvMode = ADC_CONVMODE_SINGLECHANNEL; + ADC_InitStruct.Channel = ADC_CHANNEL2; + ADC_InitStruct.ClockDivider = ADC_CLKDIV_4; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_Init(&ADC_InitStruct); + + /* Enable division */ + ANA->REG1 |= Division; + /* Enable ADC */ + ana_reg3_tmp |= ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Start a manual ADC conversion */ + ADC_StartManual(); + /* Waiting last operation done */ + ADC_WaitForManual(); + + data = ANA->ADCDATA2; + + /* Calculate the voltage of BAT1 */ + if (Division & ADC_BAT_CAPDIV) + { + CalResults->BATRTCVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap; + } + else + { + CalResults->BATRTCVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres; + } + + /* ADC resource release */ + ADC_DeInit(); + + return (0); +} + +/** + * @brief Get Temperature(takes 6.5ms). + * @note This function costs about 6.5ms when SystemClock is 26M. + * ADC data refresh time is about 3.2ms. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(Temperature channel 10) + * - ADC clock: 1.6M + * - Skip samples: Skip first 4 samples + * - Down sampling rate: 1/512 + * @param [out]CalResults.VDDVoltage is ignored + [out]CalResults.BATRTCVoltage is ignored + [out]CalResults.Temperature The value of Temperature + * @retval 1 Temperature delta information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetTemperature(ADC_CalResType *CalResults) +{ + int32_t P2; + int16_t P1, P0; + int16_t adc_data; + uint32_t retval; + NVR_RTCINFO RTC_DataStruct; + ADCInitType ADC_InitStruct; + + /* Get RTC Px parameters */ + retval = NVR_GetInfo_LoadRTCData(&RTC_DataStruct); + if (retval & 0x1U) + { + return (1); + } + else + { + P0 = RTC_DataStruct.RTCTempP0; + P1 = RTC_DataStruct.RTCTempP1; + P2 = RTC_DataStruct.RTCTempP2; + } + + /* ADC initialization */ + ADC_DeInit(); + ADC_InitStruct.TrigMode = ADC_TRIGMODE_MANUAL; + ADC_InitStruct.ConvMode = ADC_CONVMODE_SINGLECHANNEL; + ADC_InitStruct.Channel = ADC_CHANNEL10; + ADC_InitStruct.ClockDivider = ADC_CLKDIV_4; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_Init(&ADC_InitStruct); + + /* Configure 1/512 down-sampling rate */ + ADC_CICDownSamRateConfig(ADC_SDRSEL_DIV512); + /* Enable ADC */ + ADC_Cmd(ENABLE); + + /*---------- Get ADC data1 ----------*/ + /* Starts a manual ADC conversion */ + ADC_StartManual(); + /* Waiting Manual ADC conversion done */ + ADC_WaitForManual(); + adc_data = (int16_t)ADC_GetADCConversionValue(ADC_CHANNEL10); + + /* ADC resource release */ + ADC_DeInit(); + + /* Calculate temperature */ + CalResults->Temperature = (float)((((P0 * ((adc_data*adc_data)>>16)) + P1*adc_data + P2) >> 8) / 256.0); + + return (0); +} + +/** + * @brief ADC power control. + * @note When DISABLE is selected, the automatic triggering of the ADC must be turned off by calling + * ADC_TrigSourceConfig(ADC_TRIGSOURCE_OFF) before using this function. + * @param NewState + ENABLE + DISABLE + * @retval 0: Function succeeded + * 1: Function failded, the automatic triggering be enabled when DISABLE selected + */ +uint32_t ADC_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + if (ANA->ADCCTRL & ANA_ADCCTRL_AEN) + { + return 1; + } + else + { + ana_reg3_tmp &= ~ANA_REG3_ADCPDN; + } + } + else + { + ana_reg3_tmp |= ANA_REG3_ADCPDN; + } + + ANA->REG3 = ana_reg3_tmp; + + return 0; +} + +/** + * @brief Manual ADC trigger + * @param None + * @retval None + */ +void ADC_StartManual(void) +{ + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL |= ANA_ADCCTRL_MTRIG; +} + +/** + * @brief Wait for the last Manual ADC conversion done. + * @param None + * @retval None + */ +void ADC_WaitForManual(void) +{ + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG) + { + } +} + +/** + * @brief ADC auto mode trigger source configure. + * @param TrigSource: + ADC_TRIGSOURCE_OFF + ADC_TRIGSOURCE_TIM0 + ADC_TRIGSOURCE_TIM1 + ADC_TRIGSOURCE_TIM2 + ADC_TRIGSOURCE_TIM3 + * @retval None + */ +void ADC_TrigSourceConfig(uint32_t TrigSource) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADC_TRIGSOURCE(TrigSource)); + + tmp = ANA->ADCCTRL; + tmp &= ~ANA_ADCCTRL_AEN; + tmp |= TrigSource; + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief Resistance division enable control. + * @param NewState + ENABLE (x1/4) + DISABLE (x1) + * @retval None + */ +void ADC_RESDivisionCmd(uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = ANA->REG1; + if (NewState == ENABLE) + { + tmp &= ~ANA_REG1_GDE4; + tmp |=ANA_REG1_RESDIV; + } + else + { + tmp &= ~ANA_REG1_RESDIV; + } + ANA->REG1 = tmp; +} + +/** + * @brief Capacitance division enable control. + * @param NewState + ENABLE (x1/4) + DISABLE (x1) + * @retval None + */ +void ADC_CAPDivisionCmd(uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = ANA->REG1; + if (NewState == ENABLE) + { + tmp &= ~ANA_REG1_RESDIV; + tmp |=ANA_REG1_GDE4; + } + else + { + tmp &= ~ANA_REG1_GDE4; + } + ANA->REG1 = tmp; +} + +/** + * @brief CIC filter always on control. + * @param NewState + ENABLE (CIC filter always on) + DISABLE (CIC filter will be disabled when no ADC sample process is ongoing.) + * @retval None + */ +void ADC_CICAlwaysOnCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + + if (NewState == ENABLE) + ANA->ADCCTRL |= ANA_ADCCTRL_CICAON; + else + ANA->ADCCTRL &= ~ANA_ADCCTRL_CICAON; +} + +/** + * @brief CIC filter input inversion control. + * @param NewState + ENABLE + DISABLE + * @retval None + */ +void ADC_CICINVCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + + if (NewState == ENABLE) + ANA->ADCCTRL |= ANA_ADCCTRL_CICINV; + else + ANA->ADCCTRL &= ~ANA_ADCCTRL_CICINV; +} + +/** + * @brief CIC output scale-down configure. + * @param ScaleDown: + ADC_SCA_NONE + ADC_SCA_DIV2 + * @retval None + */ +void ADC_CICScaleDownConfig(uint32_t ScaleDown) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADC_SCA(ScaleDown)); + + tmp = ANA->ADCCTRL; + tmp &= ~ANA_ADCCTRL_CICSCA; + tmp |= ScaleDown; + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief CIC output skip control. + * @param Skip: + ADC_SKIP_4 + ADC_SKIP_5 + ADC_SKIP_6 + ADC_SKIP_7 + ADC_SKIP_0 + ADC_SKIP_1 + ADC_SKIP_2 + ADC_SKIP_3 + * @retval None + */ +void ADC_CICSkipConfig(uint32_t Skip) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADC_SKIP(Skip)); + + tmp = ANA->ADCCTRL; + tmp &= ~ANA_ADCCTRL_CICSKIP; + tmp |= Skip; + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief CIC down sampling rate control. + * @param DSRSelection: + ADC_SDRSEL_DIV512 + ADC_SDRSEL_DIV256 + ADC_SDRSEL_DIV128 + ADC_SDRSEL_DIV64 + * @retval None + */ +void ADC_CICDownSamRateConfig(uint32_t DSRSelection) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADC_SDR(DSRSelection)); + tmp = ANA->ADCCTRL; + tmp &= ~ANA_ADCCTRL_DSRSEL; + tmp |= DSRSelection; + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief Get ADC vonversion value. + * @param Channel: + ADC_CHANNEL0 + ADC_CHANNEL1 + ADC_CHANNEL2 + ADC_CHANNEL3 + ADC_CHANNEL4 + ADC_CHANNEL5 + ADC_CHANNEL6 + ADC_CHANNEL7 + ADC_CHANNEL8 + ADC_CHANNEL9 + ADC_CHANNEL10 + ADC_CHANNEL11 + * @retval ADC conversion value. + */ +int16_t ADC_GetADCConversionValue(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_ADC_CHANNEL(Channel)); + + addr = &ANA->ADCDATA0 + Channel; + + return *addr; +} + +/** + * @brief ADC interrupt control. + * @param INTMask: + ADC_INT_AUTODONE + ADC_INT_MANUALDONE + NewState + ENABLE + DISABLE + * @retval None + */ +void ADC_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + assert_parameters(IS_ADC_INT(INTMask)); + + if (NewState == ENABLE) + ANA->INTEN |= INTMask; + else + ANA->INTEN &= ~INTMask; +} + +/** + * @brief Get auto done flag + * @param None + * @retval 1 flag set + * 0 flag reset. + */ +uint8_t ADC_GetAutoDoneFlag(void) +{ + if(ANA->INTSTS & ANA_INTSTS_INTSTS1) + return 1; + else + return 0; +} + +/** + * @brief Get manual done flag + * @param None + * @retval 1 flag set + * 0 flag reset. + */ +uint8_t ADC_GetManualDoneFlag(void) +{ + if(ANA->INTSTS & ANA_INTSTS_INTSTS0) + return 1; + else + return 0; +} + +/** + * @brief Clear auto done flag + * @param None + * @retval None + */ +void ADC_ClearAutoDoneFlag(void) +{ + ANA->INTSTS = ANA_INTSTS_INTSTS1; +} + +/** + * @brief Clear manual done flag + * @param None + * @retval None + */ +void ADC_ClearManualDoneFlag(void) +{ + ANA->INTSTS = ANA_INTSTS_INTSTS0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc_tiny.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc_tiny.c new file mode 100644 index 0000000000..6a50c20075 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc_tiny.c @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file lib_adc_tiny.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief ADC_TINY library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_adc_tiny.h" + +#define ANA_REGF_RSTValue (0U) + +/** + * @brief Initializes the Tiny ADC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void TADC_DeInit(void) +{ + ANA->REGF = ANA_REGF_RSTValue; + ANA->INTSTS = ANA_INTSTS_INTSTS13; + ANA->MISC_A &= ~ANA_MISC_TADCTH; +} + +/** + * @brief Fills each TADC_InitStruct member with its default value. + * @param TADC_InitStruct: pointer to an TADCInitType structure which will be initialized. + * @retval None + */ +void TADC_StructInit(TADCInitType* TADC_InitStruct) +{ + /*--------------- Reset TADC init structure parameters values ---------------*/ + /* Initialize the SignalSel member */ + TADC_InitStruct->SignalSel = ADCTINY_SIGNALSEL_IOE6; + /* Initialize the ADTREF1 member */ + TADC_InitStruct->ADTREF1 = ADCTINY_REF1_0_9; + /* Initialize the ADTREF2 member */ + TADC_InitStruct->ADTREF2 = ADCTINY_REF2_1_8; + /* Initialize the ADTREF3 member */ + TADC_InitStruct->ADTREF3 = ADCTINY_REF3_2_7; +} + +/** + * @brief Tiny ADC initialization. + * @param TADC_InitStruct + SelADT: + ADCTINY_SIGNALSEL_IOE6 + ADCTINY_SIGNALSEL_IOE7 + ADTREF1: + ADCTINY_REF1_0_9 + ADCTINY_REF1_0_7 + ADTREF2: + ADCTINY_REF2_1_8 + ADCTINY_REF2_1_6 + ADTREF3: + ADCTINY_REF3_2_7 + ADCTINY_REF3_2_5 + * @retval None + */ +void TADC_Init(TADCInitType* TADC_InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADCTINY_SELADT(TADC_InitStruct->SignalSel)); + assert_parameters(IS_ADCTINY_ADTREF1(TADC_InitStruct->ADTREF1)); + assert_parameters(IS_ADCTINY_ADTREF2(TADC_InitStruct->ADTREF2)); + assert_parameters(IS_ADCTINY_ADTREF3(TADC_InitStruct->ADTREF3)); + + tmp = ANA->REGF; + tmp &= ~(ANA_REGF_SELADT \ + |ANA_REGF_ADTREF1SEL\ + |ANA_REGF_ADTREF2SEL\ + |ANA_REGF_ADTREF3SEL); + tmp |= (TADC_InitStruct->SignalSel \ + |TADC_InitStruct->ADTREF1\ + |TADC_InitStruct->ADTREF2\ + |TADC_InitStruct->ADTREF3); + ANA->REGF = tmp; +} + +/** + * @brief TADC enable control. + * @param NewState + ENABLE + DISABLE + * @retval None + */ +void TADC_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == ENABLE) + ANA->REGF |= ANA_REGF_PDNADT; + else + ANA->REGF &= ~ANA_REGF_PDNADT; +} + +/** + * @brief Get TADC output. + * @param None + * @retval Output of Tiny ADC(0 ~ 3). + */ +uint8_t TADC_GetOutput(void) +{ + return ((ANA->COMPOUT & ANA_COMPOUT_TADCO) >> ANA_COMPOUT_TADCO_Pos); +} + +/** + * @brief Configure Tiny ADC interrupt threshold. + * @param THSel: + ADCTINY_THSEL_0 + ADCTINY_THSEL_1 + ADCTINY_THSEL_2 + ADCTINY_THSEL_3 + * @retval None. + */ +void TADC_IntTHConfig(uint32_t THSel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADCTINY_THSEL(THSel)); + + tmp = ANA->MISC_A; + tmp &= ~ANA_MISC_TADCTH; + tmp |= THSel; + ANA->MISC_A = tmp; +} + +/** + * @brief TADC interrupt enable control. + * @param NewState + ENABLE + DISABLE + * @retval None + */ +void TADC_INTConfig(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == ENABLE) + ANA->INTEN |= ANA_INTEN_INTEN13; + else + ANA->INTEN &= ~ANA_INTEN_INTEN13; +} + +/** + * @brief Get Tiny ADC interrupt status. + * @param None + * @retval Interrupt status. + */ +uint8_t TADC_GetINTStatus(void) +{ + if (ANA->INTSTS & ANA_INTSTS_INTSTS13) + return 1; + else + return 0; +} + +/** + * @brief Clear Tiny ADC interrupt status. + * @param None + * @retval None + */ +void TADC_ClearINTStatus(void) +{ + ANA->INTSTS = ANA_INTSTS_INTSTS13; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_ana.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_ana.c new file mode 100644 index 0000000000..614e7f9621 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_ana.c @@ -0,0 +1,136 @@ +/** + ****************************************************************************** + * @file lib_ana.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Analog library. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_ana.h" + + +/** + * @brief Get analog status. + * @param StatusMask: + ANA_STATUS_AVCCLV + ANA_STATUS_VDCINDROP + ANA_STATUS_VDDALARM + ANA_STATUS_COMP2 + ANA_STATUS_COMP1 + ANA_STATUS_LOCKL + ANA_STATUS_LOCKH + * @retval Analog status + */ +uint8_t ANA_GetStatus(uint32_t StatusMask) +{ + /* Check parameters */ + assert_parameters(IS_ANA_STATUS(StatusMask)); + + if (ANA->COMPOUT & StatusMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Get interrupt status. + * @param IntMask: + ANA_INT_TADC_OVER + ANA_INT_REGERR + ANA_INT_SME + ANA_INT_AVCCLV + ANA_INT_VDCINDROP + ANA_INT_VDDALARM + ANA_INT_COMP2 + ANA_INT_COMP1 + ANA_INT_ADCA + ANA_INT_ADCM + * @retval interrupt status. + */ +uint8_t ANA_GetINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_ANA_INTSTSR(IntMask)); + + if (ANA->INTSTS&IntMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt status. + * @param IntMask: + ANA_INT_TADC_OVER + ANA_INT_REGERR + ANA_INT_SME + ANA_INT_AVCCLV + ANA_INT_VDCINDROP + ANA_INT_VDDALARM + ANA_INT_COMP2 + ANA_INT_COMP1 + ANA_INT_ADCA + ANA_INT_ADCM + * @retval None + */ +void ANA_ClearINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_ANA_INTSTSC(IntMask)); + + ANA->INTSTS = IntMask; +} + +/** + * @brief ANA interrupt configure. + * @param IntMask: + ANA_INT_REGERR + ANA_INT_SME + ANA_INT_AVCCLV + ANA_INT_VDCINDROP + ANA_INT_VDDALARM + ANA_INT_COMP2 + ANA_INT_COMP1 + ANA_INT_ADCA + ANA_INT_ADCM + NewState: + ENABLE + DISABLE + * @retval None + */ +void ANA_INTConfig(uint32_t IntMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ANA_INT(IntMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = ANA->INTEN; + if (NewState == ENABLE) + { + tmp |= IntMask; + } + else + { + tmp &= ~IntMask; + } + ANA->INTEN = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_clk.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_clk.c new file mode 100644 index 0000000000..cf42a2899b --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_clk.c @@ -0,0 +1,635 @@ +/** + ****************************************************************************** + * @file lib_clk.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Clock library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_clk.h" + +__IO uint32_t ana_reg3_tmp; +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the CLK_ClkInitStruct. + * + * @note This function performs the following: + * 1. If want to switch AHB clock source, enable BGP, enable 6.5M RC, + * AHB clock source switch to RCH first. + * 2. configure clock (except AHB clock source configuration). - optional + * 3. configure AHB clock source. - optional + * 4. HCLK/PCLK divider configuration. - optional + * + * @note CLK_InitTypeDef *CLK_ClkInitStruct + * [in]CLK_ClkInitStruct->ClockType, can use the | operator, the selection of parameters is as follows + * CLK_TYPE_ALL + * CLK_TYPE_AHBSRC + * CLK_TYPE_PLLL + * CLK_TYPE_PLLH + * CLK_TYPE_XTALH + * CLK_TYPE_RTCCLK + * CLK_TYPE_HCLK + * CLK_TYPE_PCLK + * + * CLK_TYPE_ALL All clocks' configurations is valid + * CLK_TYPE_AHBSRC CLK_ClkInitStruct->AHBSource(AHB Clock source configuration) is valid + * [in]CLK_ClkInitStruct->AHBSource: + * CLK_AHBSEL_6_5MRC + * CLK_AHBSEL_6_5MXTAL + * CLK_AHBSEL_HSPLL + * CLK_AHBSEL_RTCCLK + * CLK_AHBSEL_LSPLL + * CLK_TYPE_PLLL CLK_ClkInitStruct->PLLL(PLLL configuration) is valid + * [in]CLK_ClkInitStruct->PLLL.State: + * CLK_PLLL_ON (PLLL.Source/Frequency configuration is valid) + * CLK_PLLL_OFF (PLLL.Source/Frequency configuration is not valid) + * [in]CLK_ClkInitStruct->PLLL.Source: + * CLK_PLLLSRC_RCL + * CLK_PLLLSRC_XTALL + * [in]CLK_ClkInitStruct->PLLL.Frequency: + * CLK_PLLL_26_2144MHz + * CLK_PLLL_13_1072MHz + * CLK_PLLL_6_5536MHz + * CLK_PLLL_3_2768MHz + * CLK_PLLL_1_6384MHz + * CLK_PLLL_0_8192MHz + * CLK_PLLL_0_4096MHz + * CLK_PLLL_0_2048MHz + * CLK_TYPE_PLLH CLK_ClkInitStruct->PLLH(PLLH configuration) is valid + * [in]CLK_ClkInitStruct->PLLH.State: + * CLK_PLLH_ON (PLLH.Source/Frequency configuration is valid) + * CLK_PLLH_OFF (PLLH.Source/Frequency configuration is not valid) + * [in]CLK_ClkInitStruct->PLLH.Source: + * CLK_PLLHSRC_RCH + * CLK_PLLHSRC_XTALH + * [in]CLK_ClkInitStruct->PLLH.Frequency: + * CLK_PLLH_13_1072MHz + * CLK_PLLH_16_384MHz + * CLK_PLLH_19_6608MHz + * CLK_PLLH_22_9376MHz + * CLK_PLLH_26_2144MHz + * CLK_PLLH_29_4912MHz + * CLK_PLLH_32_768MHz + * CLK_PLLH_36_0448MHz + * CLK_PLLH_39_3216MHz + * CLK_PLLH_42_5984MHz + * CLK_PLLH_45_8752MHz + * CLK_PLLH_49_152MHz + * CLK_TYPE_XTALH CLK_ClkInitStruct->XTALH(XTALH configuration) is valid + * [in]CLK_ClkInitStruct->XTALH.State: + * CLK_XTALH_ON + * CLK_XTALH_OFF + * CLK_TYPE_RTCCLK CLK_ClkInitStruct->RTCCLK(RTCCLK configuration) is valid + * [in]CLK_ClkInitStruct->RTCCLK.Source: + * CLK_RTCCLKSRC_XTALL + * CLK_RTCCLKSRC_RCL + * [in]CLK_ClkInitStruct->RTCCLK.Divider: + * CLK_RTCCLKDIV_1 + * CLK_RTCCLKDIV_4 + * CLK_TYPE_HCLK CLK_ClkInitStruct->HCLK(AHB Clock(divider) configuration) is valid + * [in]CLK_ClkInitStruct->HCLK.Divider: + * 1 ~ 256 + * CLK_TYPE_PCLK CLK_ClkInitStruct->PCLK(APB Clock(divider) configuration) is valid + * [in]CLK_ClkInitStruct->PCLK.Divider: + * 1 ~ 256 + * + * @param CLK_ClkInitStruct pointer to an CLK_InitTypeDef structure that + * contains the configuration information for the clocks. + * + * @retval None + */ +void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct) +{ + uint32_t tmp; + + assert_parameters(IS_CLK_TYPE(CLK_ClkInitStruct->ClockType)); + + if (CLK_ClkInitStruct->ClockType & CLK_TYPE_AHBSRC) + { + /* Enable BGP */ + ana_reg3_tmp &= ~ANA_REG3_BGPPD; + /* Enable 6.5M RC */ + ana_reg3_tmp &= ~ANA_REG3_RCHPD; + ANA->REG3 = ana_reg3_tmp; + /* AHB clock source switch to RCH */ + MISC2->CLKSEL = 0; + } + + ANA->REGA &= ~BIT6; + ANA->REG2 &= ~BIT7; + + /*---------- XTALH configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_XTALH) + { + assert_parameters(IS_CLK_XTALHSTA(CLK_ClkInitStruct->XTALH.State)); + + /* XTALH state configure */ + ana_reg3_tmp &= ~ANA_REG3_XOHPDN; + ana_reg3_tmp |= CLK_ClkInitStruct->XTALH.State; + ANA->REG3 = ana_reg3_tmp; + } + + /*-------------------- PLLL configuration --------------------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLL) + { + assert_parameters(IS_CLK_PLLLSRC(CLK_ClkInitStruct->PLLL.Source)); + assert_parameters(IS_CLK_PLLLSTA(CLK_ClkInitStruct->PLLL.State)); + assert_parameters(IS_CLK_PLLLFRQ(CLK_ClkInitStruct->PLLL.Frequency)); + + /* XTALL power up */ + tmp = ANA->REG2; + tmp &= ~BIT7; + ANA->REG2 = tmp; + + /* PLLL state configure */ + if (CLK_ClkInitStruct->PLLL.State == CLK_PLLL_ON) + { + /* power up PLLL */ + ana_reg3_tmp |= ANA_REG3_PLLLPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Configure PLLL frequency */ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PLLLSEL; + tmp |= CLK_ClkInitStruct->PLLL.Frequency; + ANA->REG9 = tmp; + + /* Configure PLLL input clock selection */ + tmp = PMU->CONTROL; + tmp &= ~PMU_CONTROL_PLLL_SEL; + tmp |= CLK_ClkInitStruct->PLLL.Source; + PMU->CONTROL = tmp; + } + else + { + /* power down PLLL */ + ana_reg3_tmp &= ~ANA_REG3_PLLLPDN; + ANA->REG3 = ana_reg3_tmp; + } + } + + /*-------------------- PLLH configuration --------------------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLH) + { + assert_parameters(IS_CLK_PLLHSRC(CLK_ClkInitStruct->PLLH.Source)); + assert_parameters(IS_CLK_PLLHSTA(CLK_ClkInitStruct->PLLH.State)); + assert_parameters(IS_CLK_PLLHFRQ(CLK_ClkInitStruct->PLLH.Frequency)); + + /* PLLH state configure */ + if (CLK_ClkInitStruct->PLLH.State == CLK_PLLH_ON) + { + /* Power up PLLH */ + ana_reg3_tmp |= ANA_REG3_PLLHPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Configure PLLH frequency */ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PLLHSEL; + tmp |= CLK_ClkInitStruct->PLLH.Frequency; + ANA->REG9 = tmp; + + /* Clock input source, XTALH, XOH power on*/ + if (CLK_ClkInitStruct->PLLH.Source == CLK_PLLHSRC_XTALH) + { + ana_reg3_tmp |= ANA_REG3_XOHPDN; + ANA->REG3 = ana_reg3_tmp; + } + + /* Configure PLLH input clock selection */ + tmp = PMU->CONTROL; + tmp &= ~PMU_CONTROL_PLLH_SEL; + tmp |= CLK_ClkInitStruct->PLLH.Source; + PMU->CONTROL = tmp; + } + else + { + /* Power down PLLH */ + ana_reg3_tmp &= ~ANA_REG3_PLLHPDN; + ANA->REG3 = ana_reg3_tmp; + } + } + + /*---------- RTCCLK configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_RTCCLK) + { + assert_parameters(IS_CLK_RTCSRC(CLK_ClkInitStruct->RTCCLK.Source)); + assert_parameters(IS_CLK_RTCDIV(CLK_ClkInitStruct->RTCCLK.Divider)); + + /* RTCCLK source(optional) */ + tmp = PMU->CONTROL; + tmp &= ~PMU_CONTROL_RTCLK_SEL; + tmp |= CLK_ClkInitStruct->RTCCLK.Source; + PMU->CONTROL = tmp; + + /*----- RTCCLK Divider -----*/ + RTC_PrescalerConfig(CLK_ClkInitStruct->RTCCLK.Divider); + } + + /*---------- AHB clock source configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_AHBSRC) + { + assert_parameters(IS_CLK_AHBSRC(CLK_ClkInitStruct->AHBSource)); + + /* clock source: 6.5M RC */ + if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MRC) + { + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + + /* clock source: 6_5MXTAL */ + else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MXTAL) + { + /* Power up 6.5M xtal */ + ana_reg3_tmp |= ANA_REG3_XOHPDN; + ANA->REG3 = ana_reg3_tmp; + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + + /* clock source: PLLH */ + else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_HSPLL) + { + /* Power up PLLH */ + ana_reg3_tmp |= ANA_REG3_PLLHPDN; + ANA->REG3 = ana_reg3_tmp; + /* while loop until PLLL is lock */ + while (!(ANA->COMPOUT & ANA_COMPOUT_LOCKH)) + { + } + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + + /* clock source: PLLL */ + else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_LSPLL) + { + /* Power up PLLL */ + ana_reg3_tmp |= ANA_REG3_PLLLPDN; + ANA->REG3 = ana_reg3_tmp; + /* while loop until PLLL is lock */ + while (!(ANA->COMPOUT & ANA_COMPOUT_LOCKL)) + { + } + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + /* clock source: RTCCLK */ + else + { + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + } + + /*---------- HCLK configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_HCLK) + { + assert_parameters(IS_CLK_HCLKDIV(CLK_ClkInitStruct->HCLK.Divider)); + + MISC2->CLKDIVH = (CLK_ClkInitStruct->HCLK.Divider) - 1; + } + + /*---------- PCLK configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PCLK) + { + assert_parameters(IS_CLK_PCLKDIV(CLK_ClkInitStruct->PCLK.Divider)); + + MISC2->CLKDIVP = (CLK_ClkInitStruct->PCLK.Divider) - 1; + } +} + +/** + * @brief AHB Periphral clock control. + * @param Periphral: can use the | operator + CLK_AHBPERIPHRAL_DMA + CLK_AHBPERIPHRAL_GPIO + CLK_AHBPERIPHRAL_LCD + CLK_AHBPERIPHRAL_CRYPT + NewState: + ENABLE + DISABLE + * @retval None. + */ +void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_CLK_AHBPERIPHRAL(Periphral)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC2->HCLKEN |= Periphral; + } + else + { + MISC2->HCLKEN &= ~Periphral; + } +} + +/** + * @brief APB Periphral clock control. + * @param Periphral: can use the | operator + CLK_APBPERIPHRAL_DMA + CLK_APBPERIPHRAL_I2C + CLK_APBPERIPHRAL_SPI1 + CLK_APBPERIPHRAL_SPI2 + CLK_APBPERIPHRAL_UART0 + CLK_APBPERIPHRAL_UART1 + CLK_APBPERIPHRAL_UART2 + CLK_APBPERIPHRAL_UART3 + CLK_APBPERIPHRAL_UART4 + CLK_APBPERIPHRAL_UART5 + CLK_APBPERIPHRAL_ISO78160 + CLK_APBPERIPHRAL_ISO78161 + CLK_APBPERIPHRAL_TIMER + CLK_APBPERIPHRAL_MISC + CLK_APBPERIPHRAL_MISC2 + CLK_APBPERIPHRAL_PMU + CLK_APBPERIPHRAL_RTC + CLK_APBPERIPHRAL_ANA + CLK_APBPERIPHRAL_U32K0 + CLK_APBPERIPHRAL_U32K1 + NewState: + ENABLE + DISABLE + * @retval None. + */ +void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_CLK_APBPERIPHRAL(Periphral)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC2->PCLKEN |= Periphral; + } + else + { + MISC2->PCLKEN &= ~Periphral; + } +} + +/** + * @brief Returns the HCLK frequency + * @param None + * @retval HCLK frequency + */ +uint32_t CLK_GetHCLKFreq(void) +{ + uint32_t ahb_clksrc; + uint32_t ahb_div; + uint32_t pllh_frq; + uint32_t plll_frq; + uint32_t rtcclk_div; + uint32_t hclk; + + /* Get current AHB clock source */ + ahb_clksrc = MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL; + /* Get AHB clock divider */ + ahb_div = (MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1; + + switch (ahb_clksrc) + { + /* AHB Clock source : 6.5M RC */ + case MISC2_CLKSEL_CLKSEL_RCOH: + hclk = 6553600 / ahb_div; + break; + + /* AHB Clock source : 6.5M XTAL */ + case MISC2_CLKSEL_CLKSEL_XOH: + hclk = 6553600 / ahb_div; + break; + + /* AHB Clock source : PLLH */ + case MISC2_CLKSEL_CLKSEL_PLLH: + /* Get PLLH Frequency */ + pllh_frq = ANA->REG9 & ANA_REG9_PLLHSEL; + switch (pllh_frq) + { + case ANA_REG9_PLLHSEL_X2: + hclk = 13107200 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X2_5: + hclk = 16384000 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X3: + hclk = 19660800 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X3_5: + hclk = 22937600 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X4: + hclk = 26214400 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X4_5: + hclk = 29491200 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X5: + hclk = 32768000 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X5_5: + hclk = 36044800 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X6: + hclk = 39321600 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X6_5: + hclk = 42598400 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X7: + hclk = 45875200 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X7_5: + hclk = 49152000 / ahb_div; + break; + + default: + hclk = 0; + break; + } + break; + + /* AHB Clock source : RTCCLK */ + case MISC2_CLKSEL_CLKSEL_RTCCLK: + /* Get current RTC clock divider */ + rtcclk_div = RTC->PSCA & RTC_PSCA_PSCA; + if (rtcclk_div == RTC_PSCA_PSCA_0) + { + hclk = 32768 / ahb_div; + } + else if (rtcclk_div == RTC_PSCA_PSCA_1) + { + hclk = 8192 / ahb_div; + } + else + { + hclk = 0; + } + break; + + /* AHB Clock source : PLLL */ + case MISC2_CLKSEL_CLKSEL_PLLL: + /* Get PLLL Frequency */ + plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL; + switch (plll_frq) + { + case ANA_REG9_PLLLSEL_26M: + hclk = 26214400 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_13M: + hclk = 13107200 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_6_5M: + hclk = 6553600 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_3_2M: + hclk = 3276800 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_1_6M: + hclk = 1638400 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_800K: + hclk = 819200 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_400K: + hclk = 409600 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_200K: + hclk = 204800 / ahb_div; + break; + + default: + hclk = 0; + break; + } + break; + + default: + hclk = 0; + break; + } + + return (hclk); +} + +/** + * @brief Returns the PCLK frequency + * @param None + * @retval PCLK frequency + */ +uint32_t CLK_GetPCLKFreq(void) +{ + return ((CLK_GetHCLKFreq()) / ((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1)); +} + +/** + * @brief Get the CLK_ClkInitStruct according to the internal + * Clock configuration registers. + * + * @param CLK_ClkInitStruct pointer to an CLK_ClkInitStruct structure that + * contains the current clock configuration. + * + * @retval None + */ +void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + CLK_ClkInitStruct->ClockType = CLK_TYPE_ALL; + + /* Get AHB clock source ----------------------------------------------------*/ + CLK_ClkInitStruct->AHBSource = (uint32_t)(MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL); + /* Get PLLL clock configration ---------------------------------------------*/ + CLK_ClkInitStruct->PLLL.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLL_SEL); + CLK_ClkInitStruct->PLLL.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLLSEL); + CLK_ClkInitStruct->PLLL.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLLPDN); + /* Get PLLH clock configuration --------------------------------------------*/ + CLK_ClkInitStruct->PLLH.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLH_SEL); + CLK_ClkInitStruct->PLLH.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLHSEL); + CLK_ClkInitStruct->PLLH.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLHPDN); + /* Get XTALH configuration -------------------------------------------------*/ + CLK_ClkInitStruct->XTALH.State = (uint32_t)(ANA->REG3 & ANA_REG3_XOHPDN); + /* Get HCLK(Divider) configuration -----------------------------------------*/ + CLK_ClkInitStruct->HCLK.Divider = (uint32_t)((MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1); + /* Get PCLK((Divider) configuration ----------------------------------------*/ + CLK_ClkInitStruct->PCLK.Divider = (uint32_t)((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1); +} + +/** + * @brief Get current external 6.5M crystal status. + * + * @param None + * + * @retval 6.5M crystal status + * 0: 6.5536M crystal is absent. + * 1: 6.5536M crystal is present. + */ +uint8_t CLK_GetXTALHStatus(void) +{ + if (PMU->STS & PMU_STS_EXIST_6M) + return (1); + else + return (0); +} + +/** + * @brief Get current external 32K crystal status. + * + * @param None + * + * @retval 32K crystal status + * 0: 32K crystal is absent + * 1: 32K crystal is present. + */ +uint8_t CLK_GetXTALLStatus(void) +{ + if (PMU->STS & PMU_STS_EXIST_32K) + return (1); + else + return (0); +} + +/** + * @brief Get PLL lock status. + * @param PLLStatus: + * CLK_STATUS_LOCKL + * CLK_STATUS_LOCKH + * @retval PLL lock status + * 0 PLL is not locked. + * 1 PLL is locked. + */ +uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus) +{ + /* Check parameters */ + assert_parameters(IS_CLK_PLLLOCK(PLLStatus)); + + if (ANA->COMPOUT & PLLStatus) + return 1; + else + return 0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_comp.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_comp.c new file mode 100644 index 0000000000..c0f899cfc3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_comp.c @@ -0,0 +1,337 @@ +/** + ****************************************************************************** + * @file lib_comp.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief COMP library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_comp.h" + +extern __IO uint32_t ana_reg3_tmp; +/** + * @brief Comparator debounce configure. + * @param COMPx: + COMP_1 + COMP_2 + Debounce: + COMP_DEB_0 + COMP_DEB_1 + COMP_DEB_2 + COMP_DEB_3 + * @retval None + */ +void COMP_DEBConfig(uint32_t COMPx, uint32_t Debounce) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_DEB(Debounce)); + + tmp = ANA->CTRL; + tmp &= ~(ANA_CTRL_CMP1DEB << COMPx); + tmp |= Debounce << COMPx; + ANA->CTRL = tmp; +} + +/** + * @brief Comparator mode configure. + * @param COMPx: + COMP_1 + COMP_2 + Mode: + COMP_MODE_OFF + COMP_MODE_RISING + COMP_MODE_FALLING + COMP_MODE_BOTH + * @retval None + */ +void COMP_ModeConfig(uint32_t COMPx, uint32_t Mode) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_MODE(Mode)); + + tmp = ANA->CTRL; + tmp &= ~(ANA_CTRL_COMP1_SEL << COMPx); + tmp |= Mode << COMPx; + ANA->CTRL = tmp; +} + +/** + * @brief Configure signal source. + * @param COMPx: + * COMP_1 + * COMP_2 + * SourceSelect: + * COMP_SIGNALSRC_P_TO_REF + * COMP_SIGNALSRC_N_TO_REF + * COMP_SIGNALSRC_P_TO_N + * @retval None + */ +void COMP_SignalSourceConfig(uint32_t COMPx, uint32_t SourceSelect) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_SIGNALSRC(SourceSelect)); + + tmp = ANA->REG2; + tmp &= ~(ANA_REG2_CMP1_SEL << COMPx); + tmp |= SourceSelect << COMPx; + + ANA->REG2 = tmp; +} + +/** + * @brief Comparator configure REF selection. + * @param COMPx: + * COMP_1 + * COMP_2 + * REFSelect: + * COMP_REF_VREF + * COMP_REF_BGPREF + * @retval None + */ +void COMP_REFConfig(uint32_t COMPx, uint32_t REFSelect) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_REF(REFSelect)); + + tmp = ANA->REG2; + tmp &= ~(ANA_REG2_REFSEL_CMP1 << (COMPx / 2)); + tmp |= REFSelect << (COMPx / 2); + + ANA->REG2 = tmp; +} + +/** + * @brief Comparator configure Bias current selection. + * @param COMPx: + * COMP_1 + * COMP_2 + * BiasSel: + * COMP_BIAS_20nA + * COMP_BIAS_100nA + * COMP_BIAS_500nA + * @retval None + */ +void COMP_BiasConfig(uint32_t COMPx, uint32_t BiasSel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_BIAS(BiasSel)); + + tmp = ANA->REG5; + tmp &= ~(ANA_REG5_IT_CMP1 << COMPx); + tmp |= BiasSel << COMPx; + + ANA->REG5 = tmp; +} + +/** + * @brief Get comparator count value. + * @param COMPx: + COMP_1 + COMP_2 + * @retval Comparator count value. + */ +uint32_t COMP_GetCNTValue(uint32_t COMPx) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + addr = &ANA->CMPCNT1 + (COMPx / 2); + + return (*addr); +} + +/** + * @brief Clear comparator counter value. + * @param COMPx: + COMP_1 + COMP_2 + * @retval None + */ +void COMP_ClearCNTValue(uint32_t COMPx) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + addr = &ANA->CMPCNT1 + (COMPx / 2); + *addr = 0; +} + +/** + * @brief comparator output enable control. + * @param COMPx: + COMP_1 + COMP_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void COMP_Output_Cmd(uint32_t COMPx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + if (COMPx == COMP_1) + GPIOAF->SELE |= IOE_SEL_SEL7; + else + PMU->IOASEL |= PMU_IOASEL_SEL6; + } + else + { + if (COMPx == COMP_1) + GPIOAF->SELE &= ~IOE_SEL_SEL7; + else + PMU->IOASEL &= ~PMU_IOASEL_SEL6; + } +} + +/** + * @brief Comparator enable control. + * @param COMPx: + COMP_1 + COMP_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void COMP_Cmd(uint32_t COMPx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (COMPx == COMP_1) + { + if (NewState == ENABLE) + ana_reg3_tmp |= ANA_REG3_CMP1PDN; + else + ana_reg3_tmp &= ~ANA_REG3_CMP1PDN; + } + else + { + if (NewState == ENABLE) + ana_reg3_tmp |= ANA_REG3_CMP2PDN; + else + ana_reg3_tmp &= ~ANA_REG3_CMP2PDN; + } + ANA->REG3 = ana_reg3_tmp; +} + +/** + * @brief Get comparator 1 output level + * @param None + * @retval None + */ +uint8_t COMP1_GetOutputLevel(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_COMP1) + return 1; + else + return 0; +} + +/** + * @brief Get comparator 2 output level + * @param None + * @retval None + */ +uint8_t COMP2_GetOutputLevel(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_COMP2) + return 1; + else + return 0; +} + +/** + * @brief Comparator interrupt enable control. + * @param COMPx: + * COMP_1 + * COMP_2 + * NewState: + * ENABLE + * DISABLE + * @retval None + */ +void COMP_INTConfig(uint32_t COMPx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + if (NewState == ENABLE) + { + ANA->INTEN |= ANA_INTEN_INTEN2 << (COMPx/2); + } + else + { + ANA->INTEN &= ~(ANA_INTEN_INTEN2 << (COMPx/2)); + } +} + +/** + * @brief Get comparator interrupt flag status. + * @param COMPx: + * COMP_1 + * COMP_2 + * @retval flag status + * 0: status not set + * 1: status set + */ +uint8_t COMP_GetINTStatus(uint32_t COMPx) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + if (ANA->INTSTS & (ANA_INTSTS_INTSTS2 << (COMPx/2))) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear comparator interrupt flag. + * @param COMPx: + * COMP_1 + * COMP_2 + * @retval None + */ +void COMP_ClearINTStatus(uint32_t COMPx) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + ANA->INTSTS = ANA_INTSTS_INTSTS2 << (COMPx/2); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_crypt.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_crypt.c new file mode 100644 index 0000000000..1e0dbb30d6 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_crypt.c @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file lib_crypt.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief CRYPT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_crypt.h" + +/** + * @brief Configure PTRA register, data in this address will be read out to do + * the CRYPT calculation + * @param AddrA: the SRAM address(Bit 14:0) + * @retval None + */ +void CRYPT_AddressAConfig(uint16_t AddrA) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_ADDR(AddrA)); + + CRYPT->PTRA = AddrA & CRYPT_PTRA_PTRA; +} + +/** + * @brief Configure PTRB register, data in this address will be read out to do + * the CRYPT calculation + * @param AddrB: the SRAM address(Bit 14:0) + * @retval None + */ +void CRYPT_AddressBConfig(uint16_t AddrB) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_ADDR(AddrB)); + + CRYPT->PTRB = AddrB & CRYPT_PTRB_PTRB; +} + +/** + * @brief Configure PTRO register, The CRYPT engine will write calculation + * result into this address + * @param AddrO: the SRAM address(Bit 14:0) + * @retval None + */ +void CRYPT_AddressOConfig(uint16_t AddrO) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_ADDR(AddrO)); + + CRYPT->PTRO = AddrO & CRYPT_PTRO_PTRO; +} + +/** + * @brief Get carry/borrow bit of add/sub operation. + * @param None + * @retval carry/borrow bit value + */ +uint8_t CRYPT_GetCarryBorrowBit(void) +{ + if (CRYPT->CARRY & CRYPT_CARRY_CARRY) + return (1); + else + return (0); +} + +/** + * @brief Start addition operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_ADD \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Start multiplication operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_MULTIPLY \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Start subtraction operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartSub(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_SUB \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Start rigth shift 1-bit operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_RSHIFT1 \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Waiting for last operation to complete. + * @param None + * @retval None + */ +void CRYPT_WaitForLastOperation(void) +{ + while (CRYPT->CTRL & CRYPT_CTRL_ACT) + { + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_dma.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_dma.c new file mode 100644 index 0000000000..113c08d424 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_dma.c @@ -0,0 +1,442 @@ +/** + ****************************************************************************** + * @file lib_dma.c + * @author Application Team + * @version V4.4.0 + * @date 22018-09-27 + * @brief DMA library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_dma.h" + +//registers default reset values +#define DMA_CxCTL_RSTValue (0UL) +#define DMA_CxSRC_RSTValue (0UL) +#define DMA_CxDST_RSTValue (0UL) +#define DMA_AESCTL_RSTValue (0UL) +#define DMA_AESKEY_RSTValue (0UL) + +/** + * @brief Initializes the DMA Cx peripheral registers to their default reset values. + * @param Channel: DMA_CHANNEL_0~DMA_CHANNEL_3 + * @retval None + */ +void DMA_DeInit(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + + /* channel x disable, clear stop */ + addr = &DMA->C0CTL + Channel*4; + *addr &= ~(DMA_CxCTL_EN | DMA_CTL_STOP); + + /* interrupt disable */ + DMA->IE &= ~((1<<(Channel))\ + |(1<<(Channel+4))\ + |(1<<(Channel+8))); + + /* interrupt state clear */ + DMA->STS = (1<<(Channel+4))\ + |(1<<(Channel+8))\ + |(1<<(Channel+12)); + + /* DMA_CxCTL */ + addr = &DMA->C0CTL + Channel*4; + *addr = DMA_CxCTL_RSTValue; + + /* DMA_CxSRC */ + addr = &DMA->C0SRC + Channel*4; + *addr = DMA_CxSRC_RSTValue; + + /* DMA_CxDST */ + addr = &DMA->C0DST + Channel*4; + *addr = DMA_CxDST_RSTValue; +} + +/** + * @brief DMA channel x initialization. + * @param InitStruct: DMA configuration. + DestAddr : destination address + SrcAddr : source address + FrameLen : Frame length (Ranges 0~255, actual length FrameLen+1) + PackLen : Package length (Ranges 0~255, actual length PackLen+1) + ContMode: + DMA_CONTMODE_ENABLE + DMA_CONTMODE_DISABLE + TransMode: + DMA_TRANSMODE_SINGLE + DMA_TRANSMODE_PACK + ReqSrc: + DMA_REQSRC_SOFT + DMA_REQSRC_UART0TX + DMA_REQSRC_UART0RX + DMA_REQSRC_UART1TX + DMA_REQSRC_UART1RX + DMA_REQSRC_UART2TX + DMA_REQSRC_UART2RX + DMA_REQSRC_UART3TX + DMA_REQSRC_UART3RX + DMA_REQSRC_UART4TX + DMA_REQSRC_UART4RX + DMA_REQSRC_UART5TX + DMA_REQSRC_UART5RX + DMA_REQSRC_ISO78160TX + DMA_REQSRC_ISO78160RX + DMA_REQSRC_ISO78161TX + DMA_REQSRC_ISO78161RX + DMA_REQSRC_TIMER0 + DMA_REQSRC_TIMER1 + DMA_REQSRC_TIMER2 + DMA_REQSRC_TIMER3 + DMA_REQSRC_SPI1TX + DMA_REQSRC_SPI1RX + DMA_REQSRC_U32K0 + DMA_REQSRC_U32K1 + DMA_REQSRC_CMP1 + DMA_REQSRC_CMP2 + DMA_REQSRC_SPI2TX + DMA_REQSRC_SPI2RX + DestAddrMode: + DMA_DESTADDRMODE_FIX + DMA_DESTADDRMODE_PEND + DMA_DESTADDRMODE_FEND + SrcAddrMode: + DMA_SRCADDRMODE_FIX + DMA_SRCADDRMODE_PEND + DMA_SRCADDRMODE_FEND + TransSize: + DMA_TRANSSIZE_BYTE + DMA_TRANSSIZE_HWORD + DMA_TRANSSIZE_WORD + Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + * @retval None + */ +void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel) +{ + uint32_t tmp; + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + assert_parameters(IS_DMA_CONTMOD(InitStruct->ContMode)); + assert_parameters(IS_DMA_TRANSMOD(InitStruct->TransMode)); + assert_parameters(IS_DMA_REQSRC(InitStruct->ReqSrc)); + assert_parameters(IS_DMA_DESTADDRMOD(InitStruct->DestAddrMode)); + assert_parameters(IS_DMA_SRCADDRMOD(InitStruct->SrcAddrMode)); + assert_parameters(IS_DMA_TRANSSIZE(InitStruct->TransSize)); + + if (InitStruct->TransSize == DMA_TRANSSIZE_HWORD) + { + assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->SrcAddr)); + assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->DestAddr)); + } + if (InitStruct->TransSize == DMA_TRANSSIZE_WORD) + { + assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->SrcAddr)); + assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->DestAddr)); + } + + addr = &DMA->C0DST + Channel*4; + *addr = InitStruct->DestAddr; + + addr = &DMA->C0SRC + Channel*4; + *addr = InitStruct->SrcAddr; + + addr = &DMA->C0CTL + Channel*4; + + tmp = *addr; + tmp &= ~(DMA_CTL_FLEN\ + |DMA_CTL_PLEN\ + |DMA_CTL_CONT\ + |DMA_CTL_TMODE\ + |DMA_CTL_DMASEL\ + |DMA_CxCTL_DMODE\ + |DMA_CxCTL_SMODE\ + |DMA_CxCTL_SIZE); + tmp |= ((InitStruct->FrameLen<PackLen<ContMode)\ + |(InitStruct->TransMode)\ + |(InitStruct->ReqSrc)\ + |(InitStruct->DestAddrMode)\ + |(InitStruct->SrcAddrMode)\ + |(InitStruct->TransSize)); + *addr = tmp; +} + +/** + * @brief Initializes the DMA AES channel3 registers to their default reset values. + * @param None + * @retval None + */ +void DMA_AESDeInit(void) +{ + DMA->AESCTL = DMA_AESCTL_RSTValue; + DMA->AESKEY0 = DMA_AESKEY_RSTValue; + DMA->AESKEY1 = DMA_AESKEY_RSTValue; + DMA->AESKEY2 = DMA_AESKEY_RSTValue; + DMA->AESKEY3 = DMA_AESKEY_RSTValue; + DMA->AESKEY4 = DMA_AESKEY_RSTValue; + DMA->AESKEY5 = DMA_AESKEY_RSTValue; + DMA->AESKEY6 = DMA_AESKEY_RSTValue; + DMA->AESKEY7 = DMA_AESKEY_RSTValue; +} + +/** + * @brief AES initialization. + * @param InitStruct: AES configuration. + Mode: + DMA_AESMODE_128 + DMA_AESMODE_192 + DMA_AESMODE_256 + Direction: + DMA_AESDIRECTION_ENCODE + DMA_AESDIRECTION_DECODE + KeyStr: the pointer to DMA_AESKEYx register + * @retval None + */ +void DMA_AESInit(DMA_AESInitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_DMA_AESMOD(InitStruct->Mode)); + assert_parameters(IS_DMA_AESDIR(InitStruct->Direction)); + + tmp = DMA->AESCTL; + tmp &= ~(DMA_AESCTL_MODE\ + |DMA_AESCTL_ENC); + tmp |= (InitStruct->Mode\ + |InitStruct->Direction); + DMA->AESCTL = tmp; + DMA->AESKEY0 = InitStruct->KeyStr[0]; + DMA->AESKEY1 = InitStruct->KeyStr[1]; + DMA->AESKEY2 = InitStruct->KeyStr[2]; + DMA->AESKEY3 = InitStruct->KeyStr[3]; + + if ((InitStruct->Mode == DMA_AESMODE_192) ||\ + (InitStruct->Mode == DMA_AESMODE_256)) + { + DMA->AESKEY4 = InitStruct->KeyStr[4]; + DMA->AESKEY5 = InitStruct->KeyStr[5]; + } + if (InitStruct->Mode == DMA_AESMODE_256) + { + DMA->AESKEY6 = InitStruct->KeyStr[6]; + DMA->AESKEY7 = InitStruct->KeyStr[7]; + } +} + +/** + * @brief Interrupt configure. + * @param INTMask: can use the | operator + DMA_INT_C3DA + DMA_INT_C2DA + DMA_INT_C1DA + DMA_INT_C0DA + DMA_INT_C3FE + DMA_INT_C2FE + DMA_INT_C1FE + DMA_INT_C0FE + DMA_INT_C3PE + DMA_INT_C2PE + DMA_INT_C1PE + DMA_INT_C0PE + NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_DMA_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + DMA->IE |= INTMask; + else + DMA->IE &= ~INTMask; +} + +/** + * @brief Get interrupt status. + * @param INTMask: + DMA_INTSTS_C3DA + DMA_INTSTS_C2DA + DMA_INTSTS_C1DA + DMA_INTSTS_C0DA + DMA_INTSTS_C3FE + DMA_INTSTS_C2FE + DMA_INTSTS_C1FE + DMA_INTSTS_C0FE + DMA_INTSTS_C3PE + DMA_INTSTS_C2PE + DMA_INTSTS_C1PE + DMA_INTSTS_C0PE + DMA_INTSTS_C3BUSY + DMA_INTSTS_C2BUSY + DMA_INTSTS_C1BUSY + DMA_INTSTS_C0BUSY + * @retval interrupt status. + */ +uint8_t DMA_GetINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_DMA_INTFLAGR(INTMask)); + + if (DMA->STS&INTMask) + return 1; + else + return 0; +} + +/** + * @brief Clear interrupt status. + * @param INTMask: can use the | operator + DMA_INTSTS_C3DA + DMA_INTSTS_C2DA + DMA_INTSTS_C1DA + DMA_INTSTS_C0DA + DMA_INTSTS_C3FE + DMA_INTSTS_C2FE + DMA_INTSTS_C1FE + DMA_INTSTS_C0FE + DMA_INTSTS_C3PE + DMA_INTSTS_C2PE + DMA_INTSTS_C1PE + DMA_INTSTS_C0PE + * @retval None + */ +void DMA_ClearINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_DMA_INTFLAGC(INTMask)); + + DMA->STS = INTMask; +} + +/** + * @brief DMA channel enable. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_Cmd(uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &DMA->C0CTL + Channel*4; + + if (NewState == ENABLE) + *addr |= DMA_CxCTL_EN; + else + *addr &= ~DMA_CxCTL_EN; +} + +/** + * @brief Enable AES encrypt/decrypt function of DMA channel3. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_AESCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + DMA->C3CTL |= DMA_CTL_AESEN; + else + DMA->C3CTL &= ~DMA_CTL_AESEN; +} + +/** + * @brief DMA stop transmit. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_StopTransmit(uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &DMA->C0CTL + Channel*4; + + if (NewState == ENABLE) + *addr |= DMA_CTL_STOP; + else + *addr &= ~DMA_CTL_STOP; +} + +/** + * @brief Get current frame transferred length. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + * @retval Current frame transferred length. + */ +uint8_t DMA_GetFrameLenTransferred(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + + addr = &DMA->C0LEN + Channel*4; + return ((*addr&0xFF00)>>8); +} + +/** + * @brief Get current package transferred length. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + * @retval Current package transferred length. + */ +uint8_t DMA_GetPackLenTransferred(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + + addr = &DMA->C0LEN + Channel*4; + return (*addr&0xFF); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_flash.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_flash.c new file mode 100644 index 0000000000..261a98eea6 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_flash.c @@ -0,0 +1,297 @@ +/** + ****************************************************************************** + * @file lib_flash.c + * @author Application Team + * @version V4.3.0 + * @date 2018-09-27 + * @brief FLASH library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_flash.h" +#include "lib_clk.h" + +/* FLASH Keys */ +#define FLASH_PASS_KEY 0x55AAAA55 +#define FLASH_SERASE_KEY 0xAA5555AA +#define FLASH_CERASE_KEY 0xAA5555AA +#define FLASH_DSTB_KEY 0xAA5555AA + +#define FLASH_MODE_MASK 0x1F3 + +/** + * @brief FLASH mode initialization. + * @param CSMode: + FLASH_CSMODE_DISABLE + FLASH_CSMODE_ALWAYSON + FLASH_CSMODE_TIM2OF + FLASH_CSMODE_RTC + * @retval None + */ +void FLASH_Init(uint32_t CSMode) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FLASH_CSMODE(CSMode)); + + tmp = FLASH->CTRL; + tmp &= ~FLASH_MODE_MASK; + tmp |= CSMode; + FLASH->CTRL = tmp; +} + +/** + * @brief Configure FLASH interrupt. + * @param IntMask: + FLASH_INT_CS + NewState: + ENABLE + DISABLE + * @retval None + */ +void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FLASH_INT(IntMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = FLASH->CTRL; + tmp &= ~IntMask; + if (NewState == ENABLE) + { + tmp |= IntMask; + } + FLASH->CTRL = tmp; +} + +/** + * @brief Init FLASH 1USCYCLE. + * @param None + * @retval None + */ +void FLASH_CycleInit(void) +{ + uint32_t hclk; + + hclk = CLK_GetHCLKFreq(); + + if (hclk > 1000000) + MISC2->FLASHWC = (hclk/1000000)<<8; + else + MISC2->FLASHWC = 0; +} + +/** + * @brief Erase FLASH sector. + * @param SectorAddr: sector address. + * @retval None + */ +void FLASH_SectorErase(uint32_t SectorAddr) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_ADDRESS(SectorAddr)); + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = SectorAddr; + FLASH->SERASE = FLASH_SERASE_KEY; + while (FLASH->SERASE != 0); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief FLASH word program. + * @param Addr: program start address + WordBuffer: word's buffer pointer to write + Length: The length of WordBuffer + * @retval None + */ +void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length) +{ + uint32_t i; + + /* Check parameters */ + assert_parameters(IS_FLASH_ADRRW(Addr)); + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = Addr; + for (i=0; iPGDATA = *(WordBuffer++); + } + while (FLASH->STS != 1); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief FLASH half-word progarm. + * @param Addr: program start address + HWordBuffer: half-word's buffer pointer to write + Length: The length of HWordBuffer + * @retval None + */ +void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length) +{ + uint32_t i; + + /* Check parameters */ + assert_parameters(IS_FLASH_ADRRHW(Addr)); + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = Addr; + for (i=0; iPGDATA)) = *(HWordBuffer++); + else + *((__IO uint16_t*)(&FLASH->PGDATA ) + 1) = *(HWordBuffer++); + } + while (FLASH->STS != 1); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief FLASH byte progarm. + * @param Addr: program start address + ByteBuffer: byte's buffer pointer to write + Length: The length of ByteBuffer + * @retval None + */ +void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length) +{ + uint32_t i; + + /* Check parameters */ + assert_parameters(IS_FLASH_ADDRESS(Addr)); + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = Addr; + for (i=0; iPGDATA)) = *(ByteBuffer++); + else if (((Addr + i)&0x3) == 1) + *((__IO uint8_t*)(&FLASH->PGDATA) + 1) = *(ByteBuffer++); + else if (((Addr + i)&0x3) == 2) + *((__IO uint8_t*)(&FLASH->PGDATA) + 2) = *(ByteBuffer++); + else + *((__IO uint8_t*)(&FLASH->PGDATA) + 3) = *(ByteBuffer++); + } + while (FLASH->STS != 1); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief Get Write status. + * @param None. + * @retval FLASH_WSTA_BUSY + FLASH_WSTA_FINISH + */ +uint32_t FLASH_GetWriteStatus(void) +{ + if (FLASH->STS == 1) + { + return FLASH_WSTA_FINISH; + } + else + { + return FLASH_WSTA_BUSY; + } +} + +/** + * @brief Set checksum range. + * @param AddrStart: checksum start address + AddrEnd: checksum end address + * @retval None + */ +void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_CHECKSUMADDR(AddrStart,AddrEnd)); + + FLASH->CSSADDR = AddrStart; + FLASH->CSEADDR = AddrEnd; +} + +/** + * @brief Set checksum compare value. + * @param Checksum: checksum compare value + * @retval None + */ +void FLASH_SetCheckSumCompValue(uint32_t Checksum) +{ + FLASH->CSCVALUE = Checksum; +} + +/** + * @brief Get FLASH checksum value. + * @param None + * @retval Checksum + */ +uint32_t FLASH_GetCheckSum(void) +{ + return FLASH->CSVALUE; +} + + +/** + * @brief Get FLASH interrupt status. + * @param IntMask: + FLASH_INT_CS + * @retval 1: interrupt status set + 0: interrupt status reset + */ +uint8_t FLASH_GetINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_INT(IntMask)); + + if (FLASH->INT&FLASH_INT_CSERR) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear FLASH interrupt status. + * @param IntMask: + FLASH_INT_CS + * @retval None + */ +void FLASH_ClearINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_INT(IntMask)); + + if (IntMask == FLASH_INT_CS) + { + FLASH->INT = FLASH_INT_CSERR; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_gpio.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_gpio.c new file mode 100644 index 0000000000..d711a4c592 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_gpio.c @@ -0,0 +1,563 @@ +/** + ****************************************************************************** + * @file lib_gpio.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief GPIO library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_gpio.h" + + +/** + * @brief GPIO initialization. + * @param GPIOx: GPIOB~GPIOF + InitStruct:GPIO configuration. + GPIO_Pin: can use the | operator + GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All + GPIO_Mode: + GPIO_Mode_INPUT + GPIO_Mode_OUTPUT_CMOS + GPIO_Mode_OUTPUT_OD + GPIO_Mode_INOUT_OD + GPIO_Mode_INOUT_CMOS + GPIO_Mode_FORBIDDEN + * @retval None + */ +void GPIOBToF_Init(GPIO_TypeDef *GPIOx, GPIO_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin)); + assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode)); + + if (GPIOF == GPIOx) + InitStruct->GPIO_Pin &= ~(GPIO_Pin_2); + + /* Configure ATT */ + if (InitStruct->GPIO_Mode & 0x2U) + { + tmp_reg1 = GPIOx->ATT; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x1U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->ATT = tmp_reg1; + } + + /* Configure output/input mode */ + tmp_reg1 = GPIOx->OEN; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + tmp_reg2 = GPIOx->IE; + tmp_reg2 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x8U) + { + tmp_reg2 |= InitStruct->GPIO_Pin; + } + if (InitStruct->GPIO_Mode & 0x4U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->OEN = tmp_reg1; + GPIOx->IE = tmp_reg2; +} + +/** + * @brief GPIOA initialization. + * @param GPIOx: GPIOA + InitStruct:GPIO configuration. + GPIO_Pin: can use the | operator + GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All + GPIO_Mode: + GPIO_Mode_INPUT + GPIO_Mode_OUTPUT_CMOS + GPIO_Mode_OUTPUT_OD + GPIO_Mode_INOUT_OD + GPIO_Mode_FORBIDDEN + * @retval None + */ +void GPIOA_Init(GPIOA_TypeDef *GPIOx, GPIO_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin)); + assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode)); + + /* Configure ATT */ + if (InitStruct->GPIO_Mode & 0x2U) + { + tmp_reg1 = GPIOx->ATT; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x1U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->ATT = tmp_reg1; + } + + /* Configure output/input mode */ + tmp_reg1 = GPIOx->OEN; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + tmp_reg2 = GPIOx->IE; + tmp_reg2 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x8U) + { + tmp_reg2 |= InitStruct->GPIO_Pin; + } + if (InitStruct->GPIO_Mode & 0x4U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->OEN = tmp_reg1; + GPIOx->IE = tmp_reg2; +} + +/** + * @brief Read input data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15. + * @retval input pin value. + */ +uint8_t GPIOBToF_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + tmp = GPIOx->STS; + + tmp &= GPIO_Pin; + if (tmp) + return 1; + else + return 0; +} + +/** + * @brief Read input data register bit. + * @param GPIOx: GPIOA + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15. + * @retval input pin value. + */ +uint8_t GPIOA_ReadInputDataBit(GPIOA_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + tmp = GPIOx->STS; + + tmp &= GPIO_Pin; + if (tmp) + return 1; + else + return 0; +} + +/** + * @brief Read input data register. + * @param GPIOx: GPIOB~GPIOF + * @retval input port value. + */ +uint16_t GPIOBToF_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->STS; +} + +/** + * @brief Read input data register. + * @param GPIOx: GPIOA + * @retval input port value. + */ +uint16_t GPIOA_ReadInputData(GPIOA_TypeDef* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->STS; +} + +/** + * @brief Read output data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15 + * @retval output pin value. + */ +uint8_t GPIOBToF_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + tmp = GPIOx->DAT; + tmp &= GPIO_Pin; + if (tmp) + return 1; + else + return 0; +} + +/** + * @brief Read output data register bit. + * @param GPIOx: GPIOA + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15 + * @retval output pin value. + */ +uint8_t GPIOA_ReadOutputDataBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + tmp = GPIOx->DAT; + tmp &= GPIO_Pin; + if (tmp) + return 1; + else + return 0; +} + +/** + * @brief Read output data register. + * @param GPIOx: GPIOB~GPIOF + * @retval Output port value. + */ +uint16_t GPIOBToF_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->DAT; +} + +/** + * @brief Read output data register. + * @param GPIOx: GPIOA + * @retval Output port value. + */ +uint16_t GPIOA_ReadOutputData(GPIOA_TypeDef* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->DAT; +} + +/** + * @brief Set output data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin: can use the | operator + GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All + * @retval None. + */ +void GPIOBToF_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->DAT |= GPIO_Pin; +} + +/** + * @brief Set output data register bit. + * @param GPIOx: GPIOA + GPIO_Pin: can use the | operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + * @retval None. + */ +void GPIOA_SetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->DAT |= GPIO_Pin; +} + +/** + * @brief Reset output data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin: can use the | operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + * @retval None. + */ +void GPIOBToF_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->DAT &= ~GPIO_Pin; +} + +/** + * @brief Reset output data register bit. + * @param GPIOx: GPIOA + GPIO_Pin: can use the | operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + * @retval None. + */ +void GPIOA_ResetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->DAT &= ~GPIO_Pin; +} + +/** + * @brief Write output data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin: can use the | operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + val:value write to register bit. + * @retval None. + */ +void GPIOBToF_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + assert_parameters(IS_GPIO_BITVAL(val)); + + if (val == 1) + { + GPIOx->DAT |= GPIO_Pin; + } + else + { + GPIOx->DAT &= ~GPIO_Pin; + } +} + +/** + * @brief Write output data register bit. + * @param GPIOx: GPIOA + GPIO_Pin: can use the | operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + val:value write to register bit. + * @retval None. + */ +void GPIOA_WriteBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + assert_parameters(IS_GPIO_BITVAL(val)); + + if (val == 1) + { + GPIOx->DAT |= GPIO_Pin; + } + else + { + GPIOx->DAT &= ~GPIO_Pin; + } +} + +/** + * @brief Write output data register. + * @param GPIOx: GPIOB~GPIOF + val:value write to register. + * @retval None. + */ +void GPIOBToF_Write(GPIO_TypeDef* GPIOx, uint16_t val) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + + GPIOx->DAT = val; +} + +/** + * @brief Write output data register. + * @param GPIOx: GPIOA + val:value write to register. + * @retval None. + */ +void GPIOA_Write(GPIOA_TypeDef* GPIOx, uint16_t val) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + + GPIOx->DAT = val; +} + +/** + * @brief GPIO AF configure. + * @param GPIOx:GPIOB GPIOE + GPIO_AFx: + GPIOB_AF_PLLHDIV + GPIOB_AF_OSC + GPIOB_AF_PLLLOUT + GPIOE_AF_CMP1O + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIOBToF_AFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_AFx, uint8_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIOAF_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_GPIOAF(GPIO_AFx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (GPIOx == GPIOB) + { + tmp = GPIOAF->SELB; + if (NewState != DISABLE) + { + tmp |= GPIO_AFx; + } + else + { + tmp &= ~GPIO_AFx; + } + GPIOAF->SELB = tmp; + } + if (GPIOx == GPIOE) + { + tmp = GPIOAF->SELE; + if (NewState != DISABLE) + { + tmp |= GPIO_AFx; + } + else + { + tmp &= ~GPIO_AFx; + } + GPIOAF->SELE = tmp; + } +} + +/** + * @brief GPIO AF configure. + * @param PMUIO_AFx: + PMUIO7_AF_PLLDIV + PMUIO_AF_CMP2O + PMUIO3_AF_PLLDIV + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PMUIOAF(PMUIO_AFx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + GPIOA->SEL |= PMUIO_AFx; + } + else + { + GPIOA->SEL &= ~PMUIO_AFx; + } +} + +/** + * @brief GPIO pin remap. + * @param GPIO_Remap: + GPIO_REMAP_I2C + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_REMAP(GPIO_Remap)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = GPIOAF->_MISC; + tmp &= ~GPIO_Remap; + if (NewState == ENABLE) + tmp |= GPIO_Remap; + GPIOAF->_MISC = tmp; +} + +/** + * @brief GPIO PLLDIV configure. + * @param Divider: + GPIO_PLLDIV_1 + GPIO_PLLDIV_2 + GPIO_PLLDIV_4 + GPIO_PLLDIV_8 + GPIO_PLLDIV_16 + * @retval None. + */ +void GPIO_PLLDIV_Config(uint32_t Divider) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_PLLDIV(Divider)); + + tmp = GPIOAF->_MISC; + tmp &= ~IO_MISC_PLLHDIV; + tmp |= Divider; + GPIOAF->_MISC = tmp; +} + +/** + * @brief GPIOA de-glitch circuit control. + * @param GPIO_Pin: can use the | operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIOA_NoDeg_Cmd( uint16_t GPIO_Pin, uint8_t NewState) +{ + uint16_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = GPIOA->IOANODEG; + /*IOA wake-up signal will not go through de-glitch circuit.*/ + if (NewState != DISABLE) + { + tmp |= GPIO_Pin; + } + /*IOA wake-up signal will go through de-glitch circuit.*/ + else + { + tmp &= ~GPIO_Pin; + } + GPIOA->IOANODEG = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_i2c.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_i2c.c new file mode 100644 index 0000000000..1bf70cb182 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_i2c.c @@ -0,0 +1,689 @@ +/** + ****************************************************************************** + * @file lib_i2c.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief IIC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_i2c.h" + +//registers default reset values +#define I2C_ADDR_RSTValue 0 +#define I2C_CTRL_RSTValue 0 +#define I2C_CTRL2_RSTValue 0 + +/* Private Functions -------------------------------------------------------- */ +static uint16_t I2C_CheckState(uint8_t State); +static void I2C_SendStart(void); +static void I2C_SendRestart(void); +static void I2C_SendByte(uint8_t dat); +static void I2C_SendStop(void); +static uint8_t I2C_ReceiveByte(void); +static void I2C_ClearBus(uint32_t remap); +static void I2C_WaitForCrossPage(uint8_t sla); + +/** + * @brief Check required state. + * @param State: + Required state. + * @retval 0: state OK + !0: state Error, [15:8]Required status code, [7:0] real status code. + */ +static uint16_t I2C_CheckState(uint8_t State) +{ + uint16_t ret; + if (I2C_GetStatusCode() != State) + { + ret = (State<<8)|(I2C_GetStatusCode()); + return ret; + } + else + { + return 0; + } +} + +/** + * @brief Send start signal. + * @param None + * @retval None + */ +static void I2C_SendStart(void) +{ + I2C_GenerateSTART(ENABLE); + while (I2C_GetINTStatus() == 0); + I2C_GenerateSTART(DISABLE); +} + +/** + * @brief Send restart signal. + * @param None + * @retval None + */ +static void I2C_SendRestart(void) +{ + I2C_GenerateSTART(ENABLE); + I2C_ClearINTStatus(); + while (I2C_GetINTStatus() == 0); + I2C_GenerateSTART(DISABLE); +} + +/** + * @brief Send stop signal. + * @param None + * @retval None + */ +static void I2C_SendStop(void) +{ + I2C_GenerateSTOP(ENABLE); + I2C_ClearINTStatus(); + I2C_GenerateSTOP(DISABLE); +} + +/** + * @brief Send data. + * @param dat:data to send. + * @retval None + */ +static void I2C_SendByte(uint8_t dat) +{ + I2C_SendData(dat); + I2C_ClearINTStatus(); + while (I2C_GetINTStatus() == 0); +} + +/** + * @brief Receive byte. + * @param None + * @retval Byte received + */ +static uint8_t I2C_ReceiveByte(void) +{ + I2C_ClearINTStatus(); + while (I2C_GetINTStatus() == 0); + return I2C_ReceiveData(); +} + +/** + * @brief Wait for cross page operation done. + * @param None + * @retval None + */ +static void I2C_WaitForCrossPage(uint8_t sla) +{ + do + { + I2C_SendRestart(); + I2C_SendByte(sla); //device address + }while (I2C_GetStatusCode() !=0x18); + I2C_SendStop(); //stop +} + +static void I2C_ClearBus(uint32_t remap) +{ + __IO uint8_t i, j; + + if (remap) // I2C remap enable, SCL IOC4 + { + GPIOC->DAT &= ~BIT4; + GPIOC->ATT |= BIT4; + GPIOC->OEN &= ~BIT4; + for (i=0; i<9; i++) + { + GPIOC->DAT |= BIT4; + for (j=0; j<100; j++) + __NOP(); + GPIOC->DAT &= ~BIT4; + for (j=0; j<100; j++) + __NOP(); + } + GPIOC->DAT |= BIT4; + GPIOC->OEN |= BIT4; + GPIOC->IE &= ~BIT4; + } + else // I2C remap disable, SCL IOB13 + { + GPIOB->DAT &= ~BIT13; + GPIOB->ATT |= BIT13; + GPIOB->OEN &= ~BIT13; + for (i=0; i<9; i++) + { + GPIOB->DAT |= BIT13; + for (j=0; j<100; j++) + __NOP(); + GPIOB->DAT &= ~BIT13; + for (j=0; j<100; j++) + __NOP(); + } + GPIOB->DAT |= BIT13; + GPIOB->OEN |= BIT13; + GPIOB->IE &= ~BIT13; + } +} + +/* Exported Functions ------------------------------------------------------- */ + +/** + * @brief Initializes the I2C peripheral registers to their default reset values. + * @param remap: I2C_REMAP_ENABLE or I2C_REMAP_DISABLE + * @retval None + */ +void I2C_DeInit(uint32_t remap) +{ + I2C->CTRL &= ~I2C_CTRL_EN; + + I2C->ADDR = I2C_ADDR_RSTValue; + I2C->CTRL = I2C_CTRL_RSTValue; + I2C->CTRL2 = I2C_CTRL2_RSTValue; + + I2C_ClearBus(remap); +} + +/** + * @brief Fills each InitStruct member with its default value. + * @param InitStruct: pointer to an I2C_InitType structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitType *InitStruct) +{ + /*--------------- Reset I2C init structure parameters values ---------------*/ + /* Initialize the AssertAcknowledge member */ + InitStruct->AssertAcknowledge = I2C_ASSERTACKNOWLEDGE_DISABLE; + /* Initialize the ClockSource member */ + InitStruct->ClockSource = I2C_CLOCKSOURCE_APBD256; + /* Initialize the GeneralCallAck member */ + InitStruct->GeneralCallAck = I2C_GENERALCALLACK_DISABLE; + /* Initialize the SlaveAddr member */ + InitStruct->SlaveAddr = 0; +} + +/** + * @brief I2C initialization. + * @param InitStruct: I2C configuration. + SlaveAddr: Own I2C slave address (7 bit) + GeneralCallAck: + I2C_GENERALCALLACK_ENABLE + I2C_GENERALCALLACK_DISABLE + AssertAcknowledge: + I2C_ASSERTACKNOWLEDGE_ENABLE + I2C_ASSERTACKNOWLEDGE_DISABLE + ClockSource: + I2C_CLOCKSOURCE_APBD256 + I2C_CLOCKSOURCE_APBD224 + I2C_CLOCKSOURCE_APBD192 + I2C_CLOCKSOURCE_APBD160 + I2C_CLOCKSOURCE_APBD960 + I2C_CLOCKSOURCE_APBD120 + I2C_CLOCKSOURCE_APBD60 + I2C_CLOCKSOURCE_TIM3OFD8 + * @retval None. + */ +void I2C_Init(I2C_InitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_I2C_GC(InitStruct->GeneralCallAck)); + assert_parameters(IS_I2C_AA(InitStruct->AssertAcknowledge)); + assert_parameters(IS_I2C_CLKSRC(InitStruct->ClockSource)); + + I2C->ADDR = InitStruct->SlaveAddr\ + |InitStruct->GeneralCallAck; + tmp = I2C->CTRL; + tmp &= ~(I2C_CTRL_CR\ + |I2C_CTRL_AA); + tmp |= (InitStruct->ClockSource\ + |InitStruct->AssertAcknowledge); + I2C->CTRL = tmp; +} + +/** + * @brief Interrupt configure. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_INTConfig(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL2 |= I2C_CTRL2_INTEN; + else + I2C->CTRL2 &= ~I2C_CTRL2_INTEN; +} + +/** + * @brief Get interrupt status. + * @param None + * @retval Interrupt status. + */ +uint8_t I2C_GetINTStatus(void) +{ + if (I2C->CTRL&I2C_CTRL_SI) + return 1; + else + return 0; +} + +/** + * @brief Clear interrupt status. + * @param None + * @retval None. + */ +void I2C_ClearINTStatus(void) +{ + I2C->CTRL &= ~I2C_CTRL_SI; +} + +/** + * @brief Read a packge of data from slave device. + * @param InitStruct: I2C_WRType + SlaveAddr : Slave device address + SubAddress : start of slave device sub-address + PageRange : maximum range of page to Read operation + pBuffer : Read data pointer + Length : sum of Read datas + SubAddrType: + I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte) + I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes) + I2C_SUBADDR_OTHER (Slave device sub-address type: othres) + * @retval 0: true + 0status code + bit15~8 status code(true) + bit7~0 status code(false) + */ +uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct) +{ + uint32_t i; + uint16_t ret_val; + + /* Check parameters */ + assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType)); + + I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA + /*-------------------------------- START -----------------------------------*/ + I2C_SendStart(); + ret_val = I2C_CheckState(0x08); + if (ret_val) return ret_val; + + /*------------------------------ Send SLA+W --------------------------------*/ + /* Slave device sub-address type: 1 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: 2 bytes */ + if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: othres */ + if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER) + { + if (InitStruct->PageRange < 256) // 8 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + else // 16 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + /*------------------------------- Restart ----------------------------------*/ + I2C_SendRestart(); //restart + ret_val = I2C_CheckState(0x10); + if (ret_val) return ret_val; + + /*----------------------------- Send SLA+R ---------------------------------*/ + /* Slave device sub-address type: othres */ + if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER) + { + if (InitStruct->PageRange < 256) // 8 + x + I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>7)&0xE)); + else // 16 + x + I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>15)&0xE)); + } + else + I2C_SendByte(InitStruct->SlaveAddr|0x01); + + ret_val = I2C_CheckState(0x40); + if (ret_val) return ret_val; + + /*----------------------------- Read datas ---------------------------------*/ + for (i=0; i<(InitStruct->Length-1); i++) + { + *InitStruct->pBuffer = I2C_ReceiveByte(); + InitStruct->pBuffer++; + ret_val = I2C_CheckState(0x50); + if (ret_val) return ret_val; + } + /*-------------------- Read the last data, disable AA ----------------------*/ + I2C_AssertAcknowledgeConfig(DISABLE); + *InitStruct->pBuffer = I2C_ReceiveByte(); + ret_val = I2C_CheckState(0x58); + if (ret_val) return ret_val; + /*--------------------------------- Stop -----------------------------------*/ + I2C_SendStop(); //stop + return 0; +} + +/** + * @brief Write a packge of data to slave device. + * @param InitStruct: I2C_WRType + SlaveAddr : Slave device address + SubAddress : start of slave device sub-address + PageRange : maximum range of page to write operation + pBuffer : write data pointer + Length : sum of write datas + SubAddrType: + I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte) + I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes) + I2C_SUBADDR_OTHER (Slave device sub-address type: othres) + * @retval 0: true + 0status code + bit15~8 status code(true) + bit7~0 status code(false) + */ +uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct) +{ + uint16_t ret_val; + uint32_t i; + + /* Check parameters */ + assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType)); + + I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA + /*-------------------------------- START -----------------------------------*/ + I2C_SendStart(); + ret_val = I2C_CheckState(0x08); + if (ret_val) return ret_val; + + /*------------------------------ Send SLA+W --------------------------------*/ + /* Slave device sub-address type: 1 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: 2 bytes */ + else if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); //device address + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); //first word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); //second word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: othres */ + else + { + if (InitStruct->PageRange < 256) // 8 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + else // 16 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + /*----------------------------- Write datas --------------------------------*/ + for (i=0; i<(InitStruct->Length); i++) + { + /* Reach the page boundary */ + if ((i > 0) && ((InitStruct->SubAddress+i)%InitStruct->PageRange == 0)) + { + I2C_SendStop(); + I2C_WaitForCrossPage(InitStruct->SlaveAddr); + I2C_SendStart(); //start + ret_val = I2C_CheckState(0x08); + if (ret_val) return ret_val; + /* WriteAddr: 1 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* WriteAddr: 2 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); //device address + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF); //first word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); //second word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* WriteAddr: (16 or 8)+x*/ + if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER) + { + if (InitStruct->PageRange < 256) // 8 + x + { + I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>7)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + else // 16 + x + { + I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>15)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + I2C_SendByte(*InitStruct->pBuffer); + InitStruct->pBuffer++; + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Not reaching the page boundary */ + else + { + I2C_SendByte(*InitStruct->pBuffer); + InitStruct->pBuffer++; + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + I2C_SendStop(); + I2C_WaitForCrossPage(InitStruct->SlaveAddr); + return 0; +} + +/** + * @brief I2C enable. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_EN; + else + I2C->CTRL &= ~I2C_CTRL_EN; +} + +/* I2C Exported Functions Group5: + Others ------------------------------------*/ + +/** + * @brief Assert acknowledge configure. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_AssertAcknowledgeConfig(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_AA; + else + I2C->CTRL &= ~I2C_CTRL_AA; +} + +/** + * @brief Receive a byte data. + * @param None. + * @retval Data received. + */ +uint8_t I2C_ReceiveData(void) +{ + return I2C->DATA; +} + +/** + * @brief Sends a byte data. + * @param Dat:data to transmit. + * @retval None + */ +void I2C_SendData(uint8_t Dat) +{ + I2C->DATA = Dat; +} + +/** + * @brief Generate start signal. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_GenerateSTART(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_STA; + else + I2C->CTRL &= ~I2C_CTRL_STA; +} + +/** + * @brief Generate stop signal. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_GenerateSTOP(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_STO; + else + I2C->CTRL &= ~I2C_CTRL_STO; +} + +/** + * @brief Get status code. + * @param None + * @retval status code. + */ +uint8_t I2C_GetStatusCode(void) +{ + return (I2C->STS&I2C_STS_STS); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_iso7816.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_iso7816.c new file mode 100644 index 0000000000..73a7992de9 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_iso7816.c @@ -0,0 +1,396 @@ +/** + ****************************************************************************** + * @file lib_iso7816.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief ISO7816 library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_iso7816.h" +#include "lib_clk.h" + +//registers default reset values +#define ISO7816_BAUDDIVL_RSTValue 0 +#define ISO7816_BAUDDIVH_RSTValue 0 +#define ISO7816_CFG_RSTValue 0 +#define ISO7816_CLK_RSTValue 0 + +#define ISO7816_INFO_RC_MASK (0xECUL) //R/C +#define ISO7816_INFO_RW_MASK (0x13UL) //R/W + +/** + * @brief ISO7816 initialization. + * @param ISO7816x: ISO78160~ISO78161 + Init_Struct:iso7816 configuration. + FirstBit: + ISO7816_FIRSTBIT_LSB + ISO7816_FIRSTBIT_MSB + ACKLen: + ISO7816_ACKLEN_1 + ISO7816_ACKLEN_2 + Parity: + ISO7816_PARITY_EVEN + ISO7816_PARITY_ODD + Baudrate: Baud rate value + * @retval None + */ +void ISO7816_Init(ISO7816_TypeDef *ISO7816x, ISO7816_InitType *Init_Struct) +{ + uint32_t tmp; + uint16_t div; + uint32_t pclk; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_FIRSTBIT(Init_Struct->FirstBit)); + assert_parameters(IS_ISO7816_ACKLEN(Init_Struct->ACKLen)); + assert_parameters(IS_ISO7816_PARITY(Init_Struct->Parity)); + assert_parameters(IS_ISO7816_BAUDRATE(Init_Struct->Baudrate)); + + tmp = ISO7816x->INFO; + tmp &= ~(ISO7816_INFO_LSB|ISO7816_INFO_RC_MASK); + tmp |= Init_Struct->FirstBit; + ISO7816x->INFO = tmp; + + tmp = ISO7816x->CFG; + tmp &= ~(ISO7816_CFG_ACKLEN\ + |BIT3\ + |BIT2\ + |ISO7816_CFG_CHKP); + tmp |= (Init_Struct->ACKLen\ + |Init_Struct->Parity); + ISO7816x->CFG = tmp; + + pclk = CLK_GetPCLKFreq(); + div = 0x10000 - (pclk/Init_Struct->Baudrate); + ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH; + ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL; +} + +/** + * @brief Fills each InitStruct member with its default value. + * @param InitStruct: pointer to an ISO7816_InitType structure which will be initialized. + * @retval None + */ +void ISO7816_StructInit(ISO7816_InitType *InitStruct) +{ + /*--------------- Reset ISO7816 init structure parameters values ---------------*/ + /* Initialize the ACKLen member */ + InitStruct->ACKLen = ISO7816_ACKLEN_1; + /* Initialize the Baudrate member */ + InitStruct->Baudrate = 9600; + /* Initialize the FirstBit member */ + InitStruct->FirstBit = ISO7816_FIRSTBIT_MSB; + /* Initialize the Parity member */ + InitStruct->Parity = ISO7816_PARITY_EVEN; +} + +/** + * @brief Initializes the ISO7816 peripheral registers to their default reset + values. + * @param ISO7816x: ISO78160~ISO78161 + * @retval None + */ +void ISO7816_DeInit(ISO7816_TypeDef *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + ISO7816x->CFG &= ~ISO7816_CFG_EN; + + /* clear interrupt flag */ + ISO7816x->INFO = ISO7816_INFO_RC_MASK; + ISO7816x->BAUDDIVH = ISO7816_BAUDDIVH_RSTValue; + ISO7816x->BAUDDIVL = ISO7816_BAUDDIVL_RSTValue; + ISO7816x->CFG = ISO7816_CFG_RSTValue; + ISO7816x->CLK = ISO7816_CLK_RSTValue; +} + +/** + * @brief ISO7816 enable control. + * @param ISO7816x: ISO78160~ISO78161 + NewState: + ENABLE + DISABLE + * @retval None. + */ +void ISO7816_Cmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + ISO7816x->CFG |= ISO7816_CFG_EN; + } + else + { + ISO7816x->CFG &= ~ISO7816_CFG_EN; + } +} + +/** + * @brief ISO7816 Baudrate control. + * @param ISO7816x: ISO78160~ISO78161 + BaudRate: + * @retval None + */ +void ISO7816_BaudrateConfig(ISO7816_TypeDef *ISO7816x, uint32_t BaudRate) +{ + uint32_t pclk; + uint16_t div; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_BAUDRATE(BaudRate)); + + pclk = CLK_GetPCLKFreq(); + div = 0x10000 - (pclk/BaudRate); + ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH; + ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL; +} + +/** + * @brief ISO7816 clock divider configure. + * @param ISO7816x: ISO78160~ISO78161 + Prescaler:1~128 + * @retval None + */ +void ISO7816_CLKDIVConfig(ISO7816_TypeDef *ISO7816x, uint32_t Prescaler) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_PRESCALER(Prescaler)); + + tmp = ISO7816x->CLK; + tmp &= ~ISO7816_CLK_CLKDIV; + tmp |= ((Prescaler - 1) & ISO7816_CLK_CLKDIV); + ISO7816x->CLK = tmp; +} + +/** + * @brief ISO7816 clock output enable control. + * @param ISO7816x: ISO78160~ISO78161 + NewState: + ENABLE + DISABLE + * @retval None + */ +void ISO7816_CLKOutputCmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + ISO7816x->CLK |= ISO7816_CLK_CLKEN; + } + else + { + ISO7816x->CLK &= ~ISO7816_CLK_CLKEN; + } +} + +/** + * @brief Read data. + * @param ISO7816: ISO78160~ISO78161 + * @retval The received data. + */ +uint8_t ISO7816_ReceiveData(ISO7816_TypeDef *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + return ISO7816x->DATA; +} + +/** + * @brief Write data. + * @param ISO7816x: ISO78160~ISO78161 + * @retval None + */ +void ISO7816_SendData(ISO7816_TypeDef *ISO7816x, uint8_t ch) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + ISO7816x->DATA = ch; +} + +/** + * @brief Interrupt configure. + * @param ISO7816x: ISO78160~ISO78161 + INTMask: + This parameter can be any combination of the following values + ISO7816_INT_RXOV + ISO7816_INT_RX + ISO7816_INT_TX + NewState: + ENABLE + DISABLE + * @retval None + */ +void ISO7816_INTConfig(ISO7816_TypeDef *ISO7816x, uint32_t INTMask, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + ISO7816x->CFG |= INTMask; + } + else + { + ISO7816x->CFG &= ~INTMask; + } +} + +/** + * @brief Get interrupt state + * @param ISO7816x: ISO78160~ISO78161 + INTMask: + ISO7816_INTSTS_RXOV + ISO7816_INTSTS_RX + ISO7816_INTSTS_TX + * @retval 1: state set + 0: state reset + */ +uint8_t ISO7816_GetINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_INTFLAGR(INTMask)); + + if (ISO7816x->INFO & INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt state. + * @param ISO7816x: ISO78160~ISO78161 + INTMask: + This parameter can be any combination of the following values + ISO7816_INTSTS_RXOV + ISO7816_INTSTS_RX + ISO7816_INTSTS_TX + * @retval None + */ +void ISO7816_ClearINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_INTFLAGC(INTMask)); + + tmp = ISO7816x->INFO; + tmp &= ~ISO7816_INFO_RC_MASK; + tmp |= INTMask; + ISO7816x->INFO = tmp; +} + +/** + * @brief Get peripheral flag. + * @param ISO7816x: ISO78160~ISO78161 + FlagMask: + ISO7816_FLAG_SDERR + ISO7816_FLAG_RCERR + * @retval 1: state set + 0: state reset + */ +uint8_t ISO7816_GetFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_FLAGR(FlagMask)); + + if (ISO7816x->INFO&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear peripheral flag. + * @param ISO7816x: ISO78160~ISO78161 + FlagMask: + This parameter can be any combination of the following values + ISO7816_FLAG_SDERR + ISO7816_FLAG_RCERR + * @retval None + */ +void ISO7816_ClearFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_FLAGC(FlagMask)); + + tmp = ISO7816x->INFO; + tmp &= ~ISO7816_INFO_RC_MASK; + tmp |= FlagMask; + ISO7816x->INFO = tmp; +} + +/** + * @brief Get last transmit ACK. + * @param ISO7816: ISO78160~ISO78161 + * @retval ACK value + */ +uint8_t ISO7816_GetLastTransmitACK(ISO7816_TypeDef *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + if (ISO7816x->INFO&ISO7816_INFO_RCACK) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Get last receive check sum bit. + * @param ISO7816: ISO78160~ISO78161 + * @retval CHKSUM bit value + */ +uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_TypeDef *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + if (ISO7816x->INFO&ISO7816_INFO_CHKSUM) + { + return 1; + } + else + { + return 0; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_lcd.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_lcd.c new file mode 100644 index 0000000000..50a2015401 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_lcd.c @@ -0,0 +1,601 @@ +/** + ****************************************************************************** + * @file lib_lcd.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief LCD library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_lcd.h" +#include "lib_LoadNVR.h" + +//registers default reset values +#define LCD_CTRL_RSTValue 0 +#define LCD_CTRL2_RSTValue 0 +#define LCD_SEGCTRL0_RSTValue 0 +#define LCD_SEGCTRL1_RSTValue 0 +#define LCD_SEGCTRL2_RSTValue 0 + +/* COMx IO */ +const LCD_SEGIO lcd_comio[] = +{ + {&GPIOD->OEN, GPIO_Pin_0}, + {&GPIOD->OEN, GPIO_Pin_1}, + {&GPIOD->OEN, GPIO_Pin_2}, + {&GPIOD->OEN, GPIO_Pin_3}, + {&GPIOD->OEN, GPIO_Pin_4}, + {&GPIOD->OEN, GPIO_Pin_5}, + {&GPIOD->OEN, GPIO_Pin_6}, + {&GPIOD->OEN, GPIO_Pin_7}, +}; + +/* SEGx IO */ +const LCD_SEGIO lcd_segio[] = +{ /**************************/ + /* SEG | GPIO | Pin */ + {&GPIOD->OEN, GPIO_Pin_4}, /* 0 D 4 */ + {&GPIOD->OEN, GPIO_Pin_5}, /* 1 D 5 */ + {&GPIOD->OEN, GPIO_Pin_6}, /* 2 D 6 */ + {&GPIOD->OEN, GPIO_Pin_7}, /* 3 D 7 */ + {&GPIOD->OEN, GPIO_Pin_8}, /* 4 D 8 */ + {&GPIOD->OEN, GPIO_Pin_9}, /* 5 D 9 */ + {&GPIOD->OEN, GPIO_Pin_10}, /* 6 D 10 */ + {&GPIOD->OEN, GPIO_Pin_11}, /* 7 D 11 */ + {&GPIOD->OEN, GPIO_Pin_12}, /* 8 D 12 */ + {&GPIOD->OEN, GPIO_Pin_13}, /* 9 D 13 */ + {&GPIOD->OEN, GPIO_Pin_14}, /* 10 D 14 */ + {&GPIOD->OEN, GPIO_Pin_15}, /* 11 D 15 */ + {&GPIOB->OEN, GPIO_Pin_4}, /* 12 B 4 */ + {&GPIOA->OEN, GPIO_Pin_14}, /* 13 A 14 */ + {&GPIOB->OEN, GPIO_Pin_5}, /* 14 B 5 */ + {&GPIOA->OEN, GPIO_Pin_15}, /* 15 A 15 */ + {&GPIOC->OEN, GPIO_Pin_0}, /* 16 C 0 */ + {&GPIOC->OEN, GPIO_Pin_1}, /* 17 C 1 */ + {&GPIOC->OEN, GPIO_Pin_2}, /* 18 C 2 */ + {&GPIOC->OEN, GPIO_Pin_3}, /* 19 C 3 */ + {&GPIOC->OEN, GPIO_Pin_4}, /* 20 C 4 */ + {&GPIOC->OEN, GPIO_Pin_5}, /* 21 C 5 */ + {&GPIOC->OEN, GPIO_Pin_6}, /* 22 C 6 */ + {&GPIOC->OEN, GPIO_Pin_7}, /* 23 C 7 */ + {&GPIOC->OEN, GPIO_Pin_8}, /* 24 C 8 */ + {&GPIOC->OEN, GPIO_Pin_9}, /* 25 C 9 */ + {&GPIOC->OEN, GPIO_Pin_10}, /* 26 C 10 */ + {&GPIOC->OEN, GPIO_Pin_11}, /* 27 C 11 */ + {&GPIOC->OEN, GPIO_Pin_12}, /* 28 C 12 */ + {&GPIOC->OEN, GPIO_Pin_13}, /* 29 C 13 */ + {&GPIOC->OEN, GPIO_Pin_14}, /* 30 C 14 */ + {&GPIOC->OEN, GPIO_Pin_15}, /* 31 C 15 */ + {&GPIOE->OEN, GPIO_Pin_10}, /* 32 E 10 */ + {&GPIOE->OEN, GPIO_Pin_11}, /* 33 E 11 */ + {&GPIOE->OEN, GPIO_Pin_12}, /* 34 E 12 */ + {&GPIOB->OEN, GPIO_Pin_8}, /* 35 B 8 */ + {&GPIOB->OEN, GPIO_Pin_9}, /* 36 B 9 */ + {&GPIOB->OEN, GPIO_Pin_10}, /* 37 B 10 */ + {&GPIOB->OEN, GPIO_Pin_11}, /* 38 B 11 */ + {&GPIOB->OEN, GPIO_Pin_12}, /* 39 B 12 */ + {&GPIOB->OEN, GPIO_Pin_13}, /* 40 B 13 */ + {&GPIOB->OEN, GPIO_Pin_14}, /* 41 B 14 */ + {&GPIOB->OEN, GPIO_Pin_15}, /* 42 B 15 */ + {&GPIOB->OEN, GPIO_Pin_0}, /* 43 B 0 */ + {&GPIOB->OEN, GPIO_Pin_6}, /* 44 B 6 */ + {&GPIOB->OEN, GPIO_Pin_1}, /* 45 B 1 */ + {&GPIOB->OEN, GPIO_Pin_7}, /* 46 B 7 */ + {&GPIOA->OEN, GPIO_Pin_11}, /* 47 A 11 */ + {&GPIOA->OEN, GPIO_Pin_10}, /* 48 A 10 */ + {&GPIOA->OEN, GPIO_Pin_9}, /* 49 A 9 */ + {&GPIOA->OEN, GPIO_Pin_8}, /* 50 A 8 */ + {&GPIOA->OEN, GPIO_Pin_3}, /* 51 A 3 */ + {&GPIOA->OEN, GPIO_Pin_2}, /* 52 A 2 */ + {&GPIOA->OEN, GPIO_Pin_1}, /* 53 A 1 */ + {&GPIOA->OEN, GPIO_Pin_0}, /* 54 A 0 */ + {&GPIOE->OEN, GPIO_Pin_13}, /* 55 E 13 */ + {&GPIOE->OEN, GPIO_Pin_14}, /* 56 E 14 */ + {&GPIOE->OEN, GPIO_Pin_15}, /* 57 E 15 */ + {&GPIOE->OEN, GPIO_Pin_9}, /* 58 E 9 */ + {&GPIOE->OEN, GPIO_Pin_8}, /* 59 E 8 */ + {&GPIOE->OEN, GPIO_Pin_7}, /* 60 E 7 */ + {&GPIOE->OEN, GPIO_Pin_6}, /* 61 E 6 */ + {&GPIOE->OEN, GPIO_Pin_5}, /* 62 E 5 */ + {&GPIOE->OEN, GPIO_Pin_4}, /* 63 E 4 */ + {&GPIOE->OEN, 0}, /* 64 NC NC */ + {&GPIOE->OEN, 0}, /* 65 NC NC */ + {&GPIOA->OEN, GPIO_Pin_4}, /* 66 A 4 */ + {&GPIOA->OEN, GPIO_Pin_5}, /* 67 A 5 */ + {&GPIOA->OEN, GPIO_Pin_6}, /* 68 A 6 */ + {&GPIOA->OEN, GPIO_Pin_7}, /* 69 A 7 */ + {&GPIOB->OEN, GPIO_Pin_2}, /* 70 B 2 */ + {&GPIOA->OEN, GPIO_Pin_12}, /* 71 A 12 */ + {&GPIOB->OEN, GPIO_Pin_3}, /* 72 B 3 */ + {&GPIOA->OEN, GPIO_Pin_13}, /* 73 A 13 */ + {&GPIOE->OEN, GPIO_Pin_0}, /* 74 E 0 */ + {&GPIOE->OEN, GPIO_Pin_1}, /* 75 E 1 */ + {&GPIOE->OEN, GPIO_Pin_2}, /* 76 E 2 */ + {&GPIOE->OEN, GPIO_Pin_3}, /* 77 E 3 */ + {&GPIOE->OEN, 0}, /* 78 NC NC */ + {&GPIOE->OEN, 0} /* 79 NC NC */ +}; + +/** + * @brief LCD initialization. + * @param InitStruct: LCD configuration. + Type: + LCD_TYPE_4COM + LCD_TYPE_6COM + LCD_TYPE_8COM + Drv: + LCD_DRV_300 + LCD_DRV_600 + LCD_DRV_150 + LCD_DRV_200 + FRQ: + LCD_FRQ_64H + LCD_FRQ_128H + LCD_FRQ_256H + LCD_FRQ_512H + SWPR: Frame buffer switch period(0.5 sec * (SWPR + 1)). + FBMODE: + LCD_FBMODE_BUFA + LCD_FBMODE_BUFAB + LCD_FBMODE_BUFABLANK + BKFILL: + LCD_BKFILL_1 + LCD_BKFILL_0 + * @retval None + */ +void LCD_Init(LCD_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_LCD_TYPE(InitStruct->Type)); + assert_parameters(IS_LCD_DRV(InitStruct->Drv)); + assert_parameters(IS_LCD_FRQ(InitStruct->FRQ)); + assert_parameters(IS_LCD_SWPR(InitStruct->SWPR)); + assert_parameters(IS_LCD_FBMODE(InitStruct->FBMODE)); + assert_parameters(IS_LCD_BKFILL(InitStruct->BKFILL)); + + tmp_reg1 = LCD->CTRL; + tmp_reg2 = LCD->CTRL2; + tmp_reg1 &= ~(LCD_CTRL_TYPE\ + |LCD_CTRL_DRV\ + |LCD_CTRL_FRQ); + tmp_reg1 |= (InitStruct->Type\ + |InitStruct->Drv\ + |InitStruct->FRQ); + tmp_reg2 &= ~(LCD_CTRL2_SWPR\ + |LCD_CTRL2_FBMODE\ + |LCD_CTRL2_BKFILL); + tmp_reg2 |= ((InitStruct->SWPR << 8)\ + |InitStruct->FBMODE\ + |InitStruct->BKFILL); + LCD->CTRL = tmp_reg1; + LCD->CTRL2 = tmp_reg2; +} + +/** + * @brief Fills each LCD_InitStruct member with its default value. + * @param LCD_InitStruct: pointer to an LCD_InitType structure which will be initialized. + * @retval None + */ +void LCD_StructInit(LCD_InitType *LCD_InitStruct) +{ + /*--------------- Reset LCD init structure parameters values ---------------*/ + /* Initialize the BKFILL member */ + LCD_InitStruct->BKFILL = LCD_BKFILL_0; + /* Initialize the Drv member */ + LCD_InitStruct->Drv = LCD_DRV_300; + /* Initialize the FBMODE member */ + LCD_InitStruct->FBMODE = LCD_FBMODE_BUFA; + /* Initialize the FRQ member */ + LCD_InitStruct->FRQ = LCD_FRQ_64H; + /* Initialize the SWPR member */ + LCD_InitStruct->SWPR = 0; + /* Initialize the Type member */ + LCD_InitStruct->Type = LCD_TYPE_4COM; +} + +/** + * @brief Initializes the LCD registers to their default reset values. + * @param None + * @retval None + */ +void LCD_DeInit(void) +{ + LCD->CTRL &= ~LCD_CTRL_EN; + + LCD->CTRL = LCD_CTRL_RSTValue; + LCD->CTRL2 = LCD_CTRL2_RSTValue; + LCD->SEGCTRL0 = LCD_SEGCTRL0_RSTValue; + LCD->SEGCTRL1 = LCD_SEGCTRL1_RSTValue; + LCD->SEGCTRL2 = LCD_SEGCTRL2_RSTValue; +} + +/** + * @brief LCD controller enable. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void LCD_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + LCD->CTRL |= LCD_CTRL_EN; + } + else + { + LCD->CTRL &= ~LCD_CTRL_EN; + } +} + +/** + * @brief Configure LCD COMs'/SEGs' IOs. + * @param ComMode: + LCD_COMMOD_4COM : Control the COM0~3 IO configuration + LCD_COMMOD_6COM : Control the COM0~5 IO configuration + LCD_COMMOD_8COM : Control the COM0~7 IO configuration + * @param SEGVal0 SEGVal1 SEGVal2 : Each bit control the SEGs' IO configuration + * @param NewState: + ENABLE : The corresponded IOs be set to forbidden mode(disable output/disable input), enable SEGs' output and LCD function. + DISABLE : LCD be disabled and the corresponded IOs be set to output(low) mode. + * @retval None + */ +void LCD_IOConfig(uint32_t ComMode, uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2, uint32_t NewState) +{ + uint32_t position, segcurrent; + + /* Check parameters */ + assert_parameters(IS_LCD_COMMOD(ComMode)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + /* Disable LCD */ + LCD->CTRL &= ~LCD_CTRL_EN; + + /* COMs' IO configuration : ouput low */ + *(lcd_comio[0].GPIO+2) &= ~lcd_comio[0].Pin; + *lcd_comio[0].GPIO &= ~lcd_comio[0].Pin; + *(lcd_comio[1].GPIO+2) &= ~lcd_comio[1].Pin; + *lcd_comio[1].GPIO &= ~lcd_comio[1].Pin; + *(lcd_comio[2].GPIO+2) &= ~lcd_comio[2].Pin; + *lcd_comio[2].GPIO &= ~lcd_comio[2].Pin; + *(lcd_comio[3].GPIO+2) &= ~lcd_comio[3].Pin; + *lcd_comio[3].GPIO &= ~lcd_comio[3].Pin; + if (ComMode & 2UL) + { + *(lcd_comio[4].GPIO+2) &= ~lcd_comio[4].Pin; + *lcd_comio[4].GPIO &= ~lcd_comio[4].Pin; + *(lcd_comio[5].GPIO+2) &= ~lcd_comio[5].Pin; + *lcd_comio[5].GPIO &= ~lcd_comio[5].Pin; + } + if (ComMode & 4UL) + { + *(lcd_comio[6].GPIO+2) &= ~lcd_comio[6].Pin; + *lcd_comio[6].GPIO &= ~lcd_comio[6].Pin; + *(lcd_comio[7].GPIO+2) &= ~lcd_comio[7].Pin; + *lcd_comio[7].GPIO &= ~lcd_comio[7].Pin; + } + + /* SEG0~31 IO Configuration : ouput low */ + position = 0; + while ((SEGVal0 >> position) != 0UL) + { + segcurrent = SEGVal0 & (1U << position); + if (segcurrent) + { + *(lcd_segio[position].GPIO + 2) &= ~lcd_segio[position].Pin; + *lcd_segio[position].GPIO &= ~lcd_segio[position].Pin; + } + position++; + } + /* SEG32~63 IO Configuration : ouput low */ + position = 0; + while ((SEGVal1 >> position) != 0UL) + { + segcurrent = SEGVal1 & (1U << position); + if (segcurrent) + { + *(lcd_segio[position + 32].GPIO + 2) &= ~lcd_segio[position + 32].Pin; + *lcd_segio[position + 32].GPIO &= ~lcd_segio[position + 32].Pin; + } + position++; + } + /* SEG64~79 IO Configuration : ouput low */ + position = 0; + while ((SEGVal2 >> position) != 0UL) + { + segcurrent = SEGVal2 & (1U << position); + if (segcurrent) + { + *(lcd_segio[position + 64].GPIO + 2) &= ~lcd_segio[position + 64].Pin; + *lcd_segio[position + 64].GPIO &= ~lcd_segio[position + 64].Pin; + } + position++; + } + } + else + { + /* COMs' IO configuration : forbidden */ + *lcd_comio[0].GPIO |= lcd_comio[0].Pin; + *(lcd_comio[0].GPIO+1) &= ~lcd_comio[0].Pin; + *lcd_comio[1].GPIO |= lcd_comio[1].Pin; + *(lcd_comio[1].GPIO+1) &= ~lcd_comio[1].Pin; + *lcd_comio[2].GPIO |= lcd_comio[2].Pin; + *(lcd_comio[2].GPIO+1) &= ~lcd_comio[2].Pin; + *lcd_comio[3].GPIO |= lcd_comio[3].Pin; + *(lcd_comio[3].GPIO+1) &= ~lcd_comio[3].Pin; + if (ComMode & 2UL) + { + *lcd_comio[4].GPIO |= lcd_comio[4].Pin; + *(lcd_comio[4].GPIO+1) &= ~lcd_comio[4].Pin; + *lcd_comio[5].GPIO |= lcd_comio[5].Pin; + *(lcd_comio[5].GPIO+1) &= ~lcd_comio[5].Pin; + } + if (ComMode & 4UL) + { + *lcd_comio[6].GPIO |= lcd_comio[6].Pin; + *(lcd_comio[6].GPIO+1) &= ~lcd_comio[6].Pin; + *lcd_comio[7].GPIO |= lcd_comio[7].Pin; + *(lcd_comio[7].GPIO+1) &= ~lcd_comio[7].Pin; + } + + /* SEG0~31 IO Configuration */ + position = 0; + while ((SEGVal0 >> position) != 0UL) + { + segcurrent = SEGVal0 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position].GPIO |= lcd_segio[position].Pin; + /* Disable input */ + *(lcd_segio[position].GPIO + 1) &= ~lcd_segio[position].Pin; + } + position++; + } + /* SEG32~63 IO Configuration */ + position = 0; + while ((SEGVal1 >> position) != 0UL) + { + segcurrent = SEGVal1 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position + 32].GPIO |= lcd_segio[position + 32].Pin; + /* Disable input */ + *(lcd_segio[position + 32].GPIO + 1) &= ~lcd_segio[position + 32].Pin; + } + position++; + } + /* SEG64~79 IO Configuration */ + position = 0; + while ((SEGVal2 >> position) != 0UL) + { + segcurrent = SEGVal2 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position + 64].GPIO |= lcd_segio[position + 64].Pin; + /* Disable input */ + *(lcd_segio[position + 64].GPIO + 1) &= ~lcd_segio[position + 64].Pin; + } + position++; + } + + /* Enable SEGs' function of IOs */ + LCD->SEGCTRL0 = SEGVal0; + LCD->SEGCTRL1 = SEGVal1; + LCD->SEGCTRL2 = SEGVal2 & 0xFFFE; + + /* Enable LCD */ + LCD->CTRL |= LCD_CTRL_EN; + } +} + +/** + * @brief LCD SEGx enable. + * @param SEGVal0 SEGVal1 SEGVal2 + * @retval None + */ +void LCD_SetSEG(uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2) +{ + uint32_t position; + uint32_t segcurrent; + + /* SEG0~31 IO Configuration */ + position = 0; + while ((SEGVal0 >> position) != 0UL) + { + segcurrent = SEGVal0 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position].GPIO |= lcd_segio[position].Pin; + /* Disable input */ + *(lcd_segio[position].GPIO + 1) &= ~lcd_segio[position].Pin; + } + position++; + } + /* SEG32~63 IO Configuration */ + position = 0; + while ((SEGVal1 >> position) != 0UL) + { + segcurrent = SEGVal1 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position + 32].GPIO |= lcd_segio[position + 32].Pin; + /* Disable input */ + *(lcd_segio[position + 32].GPIO + 1) &= ~lcd_segio[position + 32].Pin; + } + position++; + } + /* SEG64~79 IO Configuration */ + position = 0; + while ((SEGVal2 >> position) != 0UL) + { + segcurrent = SEGVal2 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position + 64].GPIO |= lcd_segio[position + 64].Pin; + /* Disable input */ + *(lcd_segio[position + 64].GPIO + 1) &= ~lcd_segio[position + 64].Pin; + } + position++; + } + + LCD->SEGCTRL0 = SEGVal0; + LCD->SEGCTRL1 = SEGVal1; + LCD->SEGCTRL2 = SEGVal2 & 0xFFFE; +} + +/** + * @brief LCD BIAS mode configure. + * @param BiasSelection: + LCD_BMODE_DIV3 + LCD_BMODE_DIV4 + * @retval None + */ +void LCD_BiasModeConfig(uint32_t BiasSelection) +{ + uint32_t tmp; + + assert_parameters(IS_LCD_BMODE(BiasSelection)); + + tmp = ANA->REG6; + tmp &= ~ANA_REG6_LCD_BMODE; + tmp |= BiasSelection; + ANA->REG6 = tmp; +} + +/** + * @brief LCD driving voltage configure. + * @note The LCD driving voltage's configuration in NVR will be load to register + * (ANA_REG6[4:1]) in startup_target.s file. + * ex: + * The VLCD information in NVR[0x40D94] 10<<1(-300mV) + * 1. When LCD_VLCD_DEC60MV is selected + * 11<<1(-360mV) will be configured to ANA_REG6[4:1], return 0 + * 2. When LCD_VLCD_DEC360MV is selected(out of range) + * 15<<1(-600mV) will be configured to ANA_REG6[4:1], return 2 + * @param VLCDSelection: + LCD_VLCD_0 + LCD_VLCD_INC60MV + LCD_VLCD_INC120MV + LCD_VLCD_INC180MV + LCD_VLCD_INC240MV + LCD_VLCD_INC300MV + LCD_VLCD_DEC60MV + LCD_VLCD_DEC120MV + LCD_VLCD_DEC180MV + LCD_VLCD_DEC240MV + LCD_VLCD_DEC300MV + LCD_VLCD_DEC360MV + LCD_VLCD_DEC420MV + LCD_VLCD_DEC480MV + LCD_VLCD_DEC540MV + LCD_VLCD_DEC600MV + * @retval 0 Function successed. + 1 NVR LCD information checksum error. + 2 LCD driving voltage's configuration out of range. + */ +uint32_t LCD_VoltageConfig(uint32_t VLCDSelection) +{ + uint32_t lcd_vol; + uint32_t lcd_vol_tmp; + uint32_t tmp; + NVR_LCDINFO LCD_InfoStruct; + + assert_parameters(IS_LCD_VLCD(VLCDSelection)); + + /* Get NVR LCD information */ + if (NVR_GetLCDInfo(&LCD_InfoStruct)) + return (1); + else + lcd_vol_tmp = LCD_InfoStruct.MEALCDVol; + + tmp = ANA->REG6; + tmp &= ~ANA_REG6_VLCD; + lcd_vol = lcd_vol_tmp<0x5U) + { + tmp |= LCD_VLCD_INC300MV << ANA_REG6_VLCD_Pos; + ANA->REG6 = tmp; + return (2); + } + else + { + tmp |= (lcd_vol + (VLCDSelection << ANA_REG6_VLCD_Pos)); + ANA->REG6 = tmp; + return (0); + } + } + /*Adjust voltage is negtive*/ + else if ( (lcd_vol_tmp > 0x5U) && (VLCDSelection > 0x5U) ) + { + /*Adjust voltage is out of range(-600mv)*/ + if ((lcd_vol_tmp + VLCDSelection - 5)>0xFU) + { + tmp |= LCD_VLCD_DEC600MV << ANA_REG6_VLCD_Pos; + ANA->REG6 = tmp; + return (2); + } + else + { + tmp |= (lcd_vol + ((VLCDSelection -0x5)<< ANA_REG6_VLCD_Pos)); + ANA->REG6 = tmp; + return (0); + } + } + else if ( (lcd_vol_tmp > 0x5U) && (VLCDSelection <= 0x5U) ) + { + /*Adjust voltage is postive or 0*/ + if ((lcd_vol_tmp - 5) <= VLCDSelection) + { + tmp |= (((VLCDSelection + 0x5) << ANA_REG6_VLCD_Pos) - lcd_vol); + ANA->REG6 = tmp; + return (0); + } + /*Adjust voltage is negtive*/ + else + { + tmp |= (lcd_vol - ((VLCDSelection) << ANA_REG6_VLCD_Pos)); + ANA->REG6 = tmp; + return (0); + } + } + else + { + /*Adjust voltage is postive or 0*/ + if ((VLCDSelection - 5) <= lcd_vol_tmp) + { + tmp |= (lcd_vol - ((VLCDSelection - 0x5) << ANA_REG6_VLCD_Pos)); + ANA->REG6 = tmp; + return (0); + } + /*Adjust voltage is negtive*/ + else + { + tmp |= ((VLCDSelection << ANA_REG6_VLCD_Pos) - lcd_vol); + ANA->REG6 = tmp; + return (0); + } + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_misc.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_misc.c new file mode 100644 index 0000000000..fba3361c88 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_misc.c @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file lib_misc.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief MISC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_misc.h" + +/** + * @brief Get flag status. + * @param FlagMask: + MISC_FLAG_LOCKUP + MISC_FLAG_PIAC + MISC_FLAG_HIAC + MISC_FLAG_PERR + * @retval Flag status. + */ +uint8_t MISC_GetFlag(uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_MISC_FLAGR(FlagMask)); + + if (MISC->SRAMINT&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear flag status. + * @param FlagMask: can use the | operator + MISC_FLAG_LOCKUP + MISC_FLAG_PIAC + MISC_FLAG_HIAC + MISC_FLAG_PERR + * @retval None + */ +void MISC_ClearFlag(uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_MISC_FLAGC(FlagMask)); + + MISC->SRAMINT = FlagMask; +} + +/** + * @brief Interrupt configure. + * @param INTMask: can use the | operator + MISC_INT_LOCK + MISC_INT_PIAC + MISC_INT_HIAC + MISC_INT_PERR + NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_MISC_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = MISC->SRAMINIT; + if (NewState == ENABLE) + { + tmp |= INTMask; + } + else + { + tmp &= ~INTMask; + } + MISC->SRAMINIT = tmp; +} + +/** + * @brief sram parity contrl. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_SRAMParityCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC->SRAMINIT |= MISC_SRAMINIT_PEN; + } + else + { + MISC->SRAMINIT &= ~MISC_SRAMINIT_PEN; + } +} + +/** + * @brief Get sram parity error address. + * @param None + * @retval parity error address. + */ +uint32_t MISC_GetSRAMPEAddr(void) +{ + uint32_t tmp; + + tmp = MISC->PARERR; + tmp = tmp*4 + 0x20000000; + return tmp; +} + +/** + * @brief Get APB error address. + * @param None + * @retval APB error address. + */ +uint32_t MISC_GetAPBErrAddr(void) +{ + uint32_t tmp; + + tmp = MISC->PIADDR; + tmp = tmp + 0x40010000; + return tmp; +} + +/** + * @brief Get AHB error address. + * @param None + * @retval AHB error address. + */ +uint32_t MISC_GetAHBErrAddr(void) +{ + uint32_t tmp; + + tmp = MISC->HIADDR; + tmp = tmp + 0x40000000; + return tmp; +} + +/** + * @brief IR control. + * @param IRx: + MISC_IREN_TX0 + MISC_IREN_TX1 + MISC_IREN_TX2 + MISC_IREN_TX3 + MISC_IREN_TX4 + MISC_IREN_TX5 + NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_IRCmd(uint32_t IRx, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + assert_parameters(IS_MISC_IREN(IRx)); + + tmp = MISC->IREN; + if (NewState == ENABLE) + { + tmp |= IRx; + } + else + { + tmp &= ~IRx; + } + MISC->IREN = tmp; +} + +/** + * @brief IR duty configure. + * @param DutyHigh + The high pulse width will be (DUTYH + 1)*APBCLK period. + DutyLow + The low pulse width will be (DUTYL + 1)*APBCLK period. + * @retval None + */ +void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow) +{ + MISC->DUTYH = DutyHigh; + MISC->DUTYL = DutyLow; +} + +/** + * @brief Hardfault generation configure. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_HardFaultCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC->IRQLAT &= ~MISC_IRQLAT_NOHARDFAULT; + } + else + { + MISC->IRQLAT |= MISC_IRQLAT_NOHARDFAULT; + } +} + +/** + * @brief Control if the lockup will issue a system reset. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_LockResetCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC->IRQLAT |= MISC_IRQLAT_LOCKRESET; + } + else + { + MISC->IRQLAT &= ~MISC_IRQLAT_LOCKRESET; + } +} + +/** + * @brief IRQLAT configure. + * @param Latency:0~255 + * @retval None + */ +void MISC_IRQLATConfig(uint8_t Latency) +{ + uint32_t tmp; + + tmp = MISC->IRQLAT; + tmp &= ~MISC_IRQLAT_IRQLAT; + tmp |= Latency; + MISC->IRQLAT = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pmu.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pmu.c new file mode 100644 index 0000000000..f86b4e325f --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pmu.c @@ -0,0 +1,1158 @@ +/** + ****************************************************************************** + * @file lib_pmu.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief PMU library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_pmu.h" +#include "lib_gpio.h" +#include "lib_CodeRAM.h" +#include "lib_clk.h" +#include "lib_cortex.h" + +#define DSLEEPPASS_KEY 0xAA5555AA +#define DSLEEPEN_KEY 0x55AAAA55 + +extern __IO uint32_t ana_reg3_tmp; + +/** + * @brief Enter Deep sleep mode. + * @param None + * @retval 1: Current mode is debug mode, function failed. + * 2: Enter deep-sleep mode failed. + */ +uint32_t PMU_EnterDSleepMode(void) +{ + uint32_t hclk; + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Enter deep sleep when WKU event is cleared */ + while (PMU->DSLEEPEN & PMU_DSLEEPEN_WKU) + { + } + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + ANA->REG7 &= ~BIT5; + ANA->REGA |= BIT3 | BIT1; + + PMU->DSLEEPPASS = DSLEEPPASS_KEY; + PMU->DSLEEPEN = DSLEEPEN_KEY; + + return 2; +} + +/** + * @brief Enter idel mode. + * @note Any interrupt generate to CPU will break idle mode. + * @param None + * @retval None + */ +void PMU_EnterIdleMode(void) +{ + /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + __WFI(); +} + +/** + * @brief Enter sleep mode. + * @param None + * @retval 1: Current mode is debug mode, function failed. + * 0: Quit deep-sleep mode ucceeded. + */ +uint32_t PMU_EnterSleepMode(void) +{ + uint32_t hclk; + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + ANA->REG7 &= ~BIT5; + ANA->REGA |= BIT3 | BIT1; + + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + __WFI(); + + return 0; +} + +/** + * @brief PMU interrupt configuration. + * @param INTMask:(between PMU_INT_IOAEN,PMU_INT_32K and PMU_INT_6M, can use the | operator) + PMU_INT_IOAEN + PMU_INT_32K + PMU_INT_6M + NewState: + ENABLE + DISABLE + * @retval None + */ +void PMU_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_PMU_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + PMU->CONTROL |= INTMask; + } + else + { + PMU->CONTROL &= ~INTMask; + } +} + +/** + * @brief Get interrupt status. + * @param INTMask: + PMU_INTSTS_32K + PMU_INTSTS_6M + PMU_INTSTS_EXTRST + PMU_INTSTS_PORST + PMU_INTSTS_DPORST + * @retval 1:status set + 0:status reset + */ +uint8_t PMU_GetINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_INTFLAGR(INTMask)); + + if (PMU->STS&INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt status. + * @param INTMask:specifies the flag to clear. + This parameter can be any combination of the following values + PMU_INTSTS_32K + PMU_INTSTS_6M + PMU_INTSTS_EXTRST + PMU_INTSTS_PORST + PMU_INTSTS_DPORST + * @retval None + */ +void PMU_ClearINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_INTFLAGC(INTMask)); + + PMU->STS = INTMask; +} + +/** + * @brief Get status. + * @param Mask: + PMU_STS_32K + PMU_STS_6M + * @retval 1:status set + 0:status reset + */ +uint8_t PMU_GetStatus(uint32_t Mask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_FLAG(Mask)); + + if (PMU->STS&Mask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Get all IOA interrupt status. + * @param None + * @retval IOA's interrupt status + */ +uint16_t PMU_GetIOAAllINTStatus(void) +{ + return (PMU->IOAINTSTS); +} + +/** + * @brief Get IOA interrupt status. + * @param INTMask: + GPIO_Pin_0 ~ GPIO_Pin_15 + * @retval 1:status set + 0:status reset + */ +uint16_t PMU_GetIOAINTStatus(uint16_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(INTMask)); + + if (PMU->IOAINTSTS&INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear IOA interrupt status. + * @param INTMask: + This parameter can be any combination of the following values + GPIO_Pin_0 ~ GPIO_Pin_15 + * @retval None + */ +void PMU_ClearIOAINTStatus(uint16_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PIN(INTMask)); + + PMU->IOAINTSTS = INTMask; +} + +/** + * @brief Wake-up sources pin configuration. + * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15 + Wakeup_Event: + IOA_DISABLE + IOA_RISING + IOA_FALLING + IOA_HIGH + IOA_LOW + IOA_EDGEBOTH + * @retval None + */ +void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event) +{ + uint32_t tmp; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(IOAx)); + assert_parameters(IS_PMU_WAKEUP(Wakeup_Event)); + + while ((IOAx >> position) != 0U) + { + /* Get current io position */ + iocurrent = IOAx & (0x01U << position); + + if (iocurrent) + { + /* Current IO Input configure*/ + GPIOA->OEN |= iocurrent; + GPIOA->IE |= iocurrent; + + tmp = PMU->IOAWKUEN; + tmp &= ~(3U << (2 * position)); + switch (Wakeup_Event) + { + /* Disable wake-up function */ + default: + case IOA_DISABLE: + break; + + /* wake-up function: Rising */ + case IOA_RISING: + GPIOA->DAT &= ~iocurrent; + tmp |= 1 << (2 * position); + break; + + /* wake-up function: falling */ + case IOA_FALLING: + GPIOA->DAT |= iocurrent; + tmp |= 1 << (2 * position); + break; + + /* wake-up function: high level */ + case IOA_HIGH: + GPIOA->DAT &= ~iocurrent; + tmp |= 2 << (2 * position); + break; + + /* wake-up function: low level */ + case IOA_LOW: + GPIOA->DAT |= iocurrent; + tmp |= 2 << (2 * position); + break; + + /* wake-up function: boht edge */ + case IOA_EDGEBOTH: + tmp |= 3 << (2 * position); + break; + } + PMU->IOAWKUEN = tmp; + } + position++; + } +} + +/** + * @brief Control low-power configuration, enter deep-sleep mode. + * + * @param InitStruct : pointer to PMU_LowPWRTypeDef + COMP1Power: + PMU_COMP1PWR_ON + PMU_COMP1PWR_OFF + COMP2Power: + PMU_COMP2PWR_ON + PMU_COMP2PWR_OFF + TADCPower: + PMU_TADCPWR_ON + PMU_TADCPWR_OFF + BGPPower: + PMU_BGPPWR_ON + PMU_BGPPWR_OFF + AVCCPower: + PMU_AVCCPWR_ON + PMU_AVCCPWR_OFF + LCDPower: + PMU_LCDPWER_ON + PMU_LCDPWER_OFF + VDCINDetector: + PMU_VDCINDET_ENABLE + PMU_VDCINDET_DISABLE + VDDDetector: + PMU_VDDDET_ENABLE + PMU_VDDDET_DISABLE + APBPeriphralDisable: + PMU_APB_ALL + PMU_APB_DMA + PMU_APB_I2C + PMU_APB_SPI1 + PMU_APB_SPI2 + PMU_APB_UART0 + PMU_APB_UART1 + PMU_APB_UART2 + PMU_APB_UART3 + PMU_APB_UART4 + PMU_APB_UART5 + PMU_APB_ISO78160 + PMU_APB_ISO78161 + PMU_APB_TIMER + PMU_APB_MISC + PMU_APB_U32K0 + PMU_APB_U32K1 + AHBPeriphralDisable: + PMU_AHB_ALL + PMU_AHB_DMA + PMU_AHB_GPIO + PMU_AHB_LCD + PMU_AHB_CRYPT + + * @note This function performs the following: + Comparator 1 power control ON or OFF(optional) + Comparator 2 power control ON or OFF(optional) + Tiny ADC power control ON or OFF(optional) + Bandgap power control ON or OFF(optional) + AVCC power control ON or OFF(optional) + LCD controller power control ON or OFF(optional) + VDCIN detector control Disable or Enable(optional) + VDD detector control Disable or Enable(optional) + Disable AHB/APB periphral clock Modules(optional) + Disable AVCC output + Power down ADC, Power down Temp sensor + Disable resistance/capacitance division for ADC input signal + + * @retval 1: Current MODE is debug mode, enter deep-sleep mode failed. + 2: VDCIN is not drop before enter deep-sleep mode or Failure to enter deep sleep mode. + */ +uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct) +{ + uint32_t tmp; + uint32_t hclk; + + /* Check parameters */ + assert_parameters(IS_PMU_COMP1PWR(InitStruct->COMP1Power)); + assert_parameters(IS_PMU_COMP2PWR(InitStruct->COMP2Power)); + assert_parameters(IS_PMU_TADCPWR(InitStruct->TADCPower)); + assert_parameters(IS_PMU_BGPPWR(InitStruct->BGPPower)); + assert_parameters(IS_PMU_AVCCPWR(InitStruct->AVCCPower)); + assert_parameters(IS_PMU_LCDPWER(InitStruct->LCDPower)); + assert_parameters(IS_PMU_VDCINDET(InitStruct->VDCINDetector)); + assert_parameters(IS_PMU_VDDDET(InitStruct->VDDDetector)); + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Disable AVCC output */ + ANA->REGF &= ~ANA_REGF_AVCCO_EN; + /* Power down ADC */ + ana_reg3_tmp &= ~ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + /* Power down Temp sensor */ + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL &= ~(ANA_ADCCTRL_MCH | ANA_ADCCTRL_ACH); + /* Disable resistor/cap division for ADC input signal */ + ANA->REG1 &= ~(ANA_REG1_RESDIV | ANA_REG1_GDE4); + + /******** Comparator 1 power control ********/ + ana_reg3_tmp &= ~ANA_REG3_CMP1PDN; + ana_reg3_tmp |= InitStruct->COMP1Power; + ANA->REG3 = ana_reg3_tmp; + + /******** Comparator 2 power control ********/ + ana_reg3_tmp &= ~ANA_REG3_CMP2PDN; + ana_reg3_tmp |= InitStruct->COMP2Power; + ANA->REG3 = ana_reg3_tmp; + + /******** Tiny ADC power control ********/ + tmp = ANA->REGF; + tmp &= ~ANA_REGF_PDNADT; + tmp |= InitStruct->TADCPower; + ANA->REGF = tmp; + + /******** BGP power control ********/ + ana_reg3_tmp &= ~ANA_REG3_BGPPD; + ana_reg3_tmp |= InitStruct->BGPPower; + ANA->REG3 = ana_reg3_tmp; + + /******** AVCC power control ********/ + tmp = ANA->REG8; + tmp &= ~ANA_REG8_PD_AVCCLDO; + tmp |= InitStruct->AVCCPower; + ANA->REG8 = tmp; + + /******** LCD controller power control ********/ + tmp = LCD->CTRL; + tmp &= ~LCD_CTRL_EN; + tmp |= InitStruct->LCDPower; + LCD->CTRL = tmp; + /* LCD power off, disable all SEG */ + if (InitStruct->LCDPower == PMU_LCDPWER_OFF) + { + LCD->SEGCTRL0 = 0; + LCD->SEGCTRL1 = 0; + LCD->SEGCTRL2 = 0; + } + + /******** VDCIN detector control ********/ + tmp = ANA->REGA; + tmp &= ~ANA_REGA_PD_VDCINDET; + tmp |= InitStruct->VDCINDetector; + ANA->REGA = tmp; + + /******** VDD detector control *********/ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PDDET; + tmp |= InitStruct->VDDDetector; + ANA->REG9 = tmp; + + /******** AHB Periphral clock disable selection ********/ + tmp = MISC2->HCLKEN; + tmp &= ~((InitStruct->AHBPeriphralDisable) & PMU_AHB_ALL); + MISC2->HCLKEN = tmp; + + /******** APB Periphral clock disable selection ********/ + tmp = MISC2->PCLKEN; + tmp &= ~((InitStruct->APBPeriphralDisable) & PMU_APB_ALL); + MISC2->PCLKEN = tmp; + + if ((InitStruct->VDCINDetector) != PMU_VDCINDET_DISABLE) + { + if (!(ANA->COMPOUT & ANA_COMPOUT_VDCINDROP)) + { + return 2; + } + } + // make sure WKU is 0 before entering deep-sleep mode + while (PMU->DSLEEPEN & PMU_DSLEEPEN_WKU); + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + ANA->REG7 &= ~BIT5; + ANA->REGA |= BIT3 | BIT1; + /* Enter deep-sleep mode */ + PMU->DSLEEPPASS = DSLEEPPASS_KEY; + PMU->DSLEEPEN = DSLEEPEN_KEY; + + return 2; +} + +/** + * @brief Control low-power configuration, enter sleep mode. + * + * @param InitStruct : pointer to PMU_LowPWRTypeDef + COMP1Power: + PMU_COMP1PWR_ON + PMU_COMP1PWR_OFF + COMP2Power: + PMU_COMP2PWR_ON + PMU_COMP2PWR_OFF + TADCPower: + PMU_TADCPWR_ON + PMU_TADCPWR_OFF + BGPPower: + PMU_BGPPWR_ON + PMU_BGPPWR_OFF + AVCCPower: + PMU_AVCCPWR_ON + PMU_AVCCPWR_OFF + LCDPower: + PMU_LCDPWER_ON + PMU_LCDPWER_OFF + VDCINDetector: + PMU_VDCINDET_ENABLE + PMU_VDCINDET_DISABLE + VDDDetector: + PMU_VDDDET_ENABLE + PMU_VDDDET_DISABLE + APBPeriphralDisable: + PMU_APB_ALL + PMU_APB_DMA + PMU_APB_I2C + PMU_APB_SPI1 + PMU_APB_SPI2 + PMU_APB_UART0 + PMU_APB_UART1 + PMU_APB_UART2 + PMU_APB_UART3 + PMU_APB_UART4 + PMU_APB_UART5 + PMU_APB_ISO78160 + PMU_APB_ISO78161 + PMU_APB_TIMER + PMU_APB_MISC + PMU_APB_U32K0 + PMU_APB_U32K1 + AHBPeriphralDisable: + PMU_AHB_ALL + PMU_AHB_DMA + PMU_AHB_GPIO + PMU_AHB_LCD + PMU_AHB_CRYPT + + * @note This function performs the following: + Comparator 1 power control ON or OFF(optional) + Comparator 2 power control ON or OFF(optional) + Tiny ADC power control ON or OFF(optional) + Bandgap power control ON or OFF(optional) + AVCC power control ON or OFF(optional) + LCD controller power control ON or OFF(optional) + VDCIN detector control Disable or Enable(optional) + VDD detector control Disable or Enable(optional) + Disable AHB/APB periphral clock Modules(optional) + Disable AVCC output + Power down ADC, Power down Temp sensor + Disable resistance/capacitance division for ADC input signal + + * @retval 2: VDCIN is not drop before enter sleep mode(failed). + 1: Current mode is debug mode, enter sleep mode failed. + 0: Quit from sleep mode success. +*/ +uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct) +{ + uint32_t tmp; + uint32_t hclk; + + /* Check parameters */ + assert_parameters(IS_PMU_COMP1PWR(InitStruct->COMP1Power)); + assert_parameters(IS_PMU_COMP2PWR(InitStruct->COMP2Power)); + assert_parameters(IS_PMU_TADCPWR(InitStruct->TADCPower)); + assert_parameters(IS_PMU_BGPPWR(InitStruct->BGPPower)); + assert_parameters(IS_PMU_AVCCPWR(InitStruct->AVCCPower)); + assert_parameters(IS_PMU_LCDPWER(InitStruct->LCDPower)); + assert_parameters(IS_PMU_VDCINDET(InitStruct->VDCINDetector)); + assert_parameters(IS_PMU_VDDDET(InitStruct->VDDDetector)); + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Disable AVCC output */ + ANA->REGF &= ~ANA_REGF_AVCCO_EN; + /* Power down ADC */ + ana_reg3_tmp &= ~ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + /* Power down Temp sensor */ + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL &= ~(ANA_ADCCTRL_MCH | ANA_ADCCTRL_ACH); + /* Disable resistor/cap division for ADC input signal */ + ANA->REG1 &= ~(ANA_REG1_RESDIV | ANA_REG1_GDE4); + + /******** Comparator 1 power control ********/ + ana_reg3_tmp &= ~ANA_REG3_CMP1PDN; + ana_reg3_tmp |= InitStruct->COMP1Power; + ANA->REG3 = ana_reg3_tmp; + + /******** Comparator 2 power control ********/ + ana_reg3_tmp &= ~ANA_REG3_CMP2PDN; + ana_reg3_tmp |= InitStruct->COMP2Power; + ANA->REG3 = ana_reg3_tmp; + + /******** Tiny ADC power control ********/ + tmp = ANA->REGF; + tmp &= ~ANA_REGF_PDNADT; + tmp |= InitStruct->TADCPower; + ANA->REGF = tmp; + + /******** BGP power control ********/ + ana_reg3_tmp &= ~ANA_REG3_BGPPD; + ana_reg3_tmp |= InitStruct->BGPPower; + ANA->REG3 = ana_reg3_tmp; + + /******** AVCC power control ********/ + tmp = ANA->REG8; + tmp &= ~ANA_REG8_PD_AVCCLDO; + tmp |= InitStruct->AVCCPower; + ANA->REG8 = tmp; + + /******** LCD controller power control ********/ + tmp = LCD->CTRL; + tmp &= ~LCD_CTRL_EN; + tmp |= InitStruct->LCDPower; + LCD->CTRL = tmp; + /* LCD power off, disable all SEG */ + if (InitStruct->LCDPower == PMU_LCDPWER_OFF) + { + LCD->SEGCTRL0 = 0; + LCD->SEGCTRL1 = 0; + LCD->SEGCTRL2 = 0; + } + + /******** VDCIN detector control ********/ + tmp = ANA->REGA; + tmp &= ~ANA_REGA_PD_VDCINDET; + tmp |= InitStruct->VDCINDetector; + ANA->REGA = tmp; + + /******** VDD detector control *********/ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PDDET; + tmp |= InitStruct->VDDDetector; + ANA->REG9 = tmp; + + /******** AHB Periphral clock disable selection ********/ + tmp = MISC2->HCLKEN; + tmp &= ~((InitStruct->AHBPeriphralDisable) & PMU_AHB_ALL); + MISC2->HCLKEN = tmp; + + /******** APB Periphral clock disable selection ********/ + tmp = MISC2->PCLKEN; + tmp &= ~((InitStruct->APBPeriphralDisable) & PMU_APB_ALL); + MISC2->PCLKEN = tmp; + + if ((InitStruct->VDCINDetector) != PMU_VDCINDET_DISABLE) + { + if (!(ANA->COMPOUT & ANA_COMPOUT_VDCINDROP)) + { + return 2; + } + } + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + ANA->REG7 &= ~BIT5; + ANA->REGA |= BIT3 | BIT1; + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + + return 0; +} + + +/** + * @brief Flash deep standby, enter idle mode. + * @param None + * @retval None + */ +#ifndef __GNUC__ +void PMU_EnterIdle_LowPower(void) +{ + uint32_t hclk; + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + PMU_EnterIdle_FlashDSTB(); +} +#endif + +/** + * @brief IOA wake-up source configure about Sleep mode. + * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15 + Wakeup_Event: + IOA_DISABLE + IOA_RISING + IOA_FALLING + IOA_HIGH + IOA_LOW + IOA_EDGEBOTH + Priority: The preemption priority for the IRQn channel. + This parameter can be a value between 0 and 3. + * @retval + */ +void PMU_SleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(IOAx)); + assert_parameters(IS_PMU_WAKEUP(Wakeup_Event)); + + /* Disable PMU interrupt in NVIC */ + NVIC_DisableIRQ(PMU_IRQn); + /* Wake-up pins configuration */ + PMU_WakeUpPinConfig(IOAx, Wakeup_Event); + /* Clear interrupt flag */ + PMU->IOAINTSTS = IOAx; + /* Enable PMU interrupt */ + PMU->CONTROL |= PMU_CONTROL_INT_IOA_EN; + CORTEX_SetPriority_ClearPending_EnableIRQ(PMU_IRQn, Priority); +} + +/** + * @brief RTC wake-up source configure about Sleep mode. + * @param Wakeup_Event: + This parameter can be any combination of the following values + PMU_RTCEVT_ACDONE + PMU_RTCEVT_WKUCNT + PMU_RTCEVT_MIDNIGHT + PMU_RTCEVT_WKUHOUR + PMU_RTCEVT_WKUMIN + PMU_RTCEVT_WKUSEC + PMU_RTCEVT_TIMEILLE + Priority: The preemption priority for the IRQn channel. + This parameter can be a value between 0 and 3. + * @retval + */ +void PMU_SleepWKUSRC_Config_RTC(uint32_t Wakeup_Event, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_PMU_RTCEVT(Wakeup_Event)); + + /* Disable RTC interrupt in NVIC */ + NVIC_DisableIRQ(RTC_IRQn); + /* Clear interrupt flag */ + RTC->INTSTS = Wakeup_Event; + /* Enable RTC interrupt */ + RTC->INTEN |= Wakeup_Event & (~0x01UL); + CORTEX_SetPriority_ClearPending_EnableIRQ(RTC_IRQn, Priority); +} +/** + * @brief IOA wake-up source configure about Deep-Sleep mode. + * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15 + Wakeup_Event: + IOA_DISABLE + IOA_RISING + IOA_FALLING + IOA_HIGH + IOA_LOW + IOA_EDGEBOTH + * @retval + */ +void PMU_DeepSleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(IOAx)); + assert_parameters(IS_PMU_WAKEUP(Wakeup_Event)); + + /* Wake-up pins configuration */ + PMU_WakeUpPinConfig(IOAx, Wakeup_Event); + /* Clear interrupt flag */ + PMU->IOAINTSTS = IOAx; +} + +/** + * @brief RTC wake-up source configure about Deep-Sleep mode. + * @param Wakeup_Event: + This parameter can be any combination of the following values + PMU_RTCEVT_ACDONE + PMU_RTCEVT_WKUCNT + PMU_RTCEVT_MIDNIGHT + PMU_RTCEVT_WKUHOUR + PMU_RTCEVT_WKUMIN + PMU_RTCEVT_WKUSEC + PMU_RTCEVT_TIMEILLE + * @retval + */ +void PMU_DeepSleepWKUSRC_Config_RTC(uint32_t Wakeup_Event) +{ + /* Check parameters */ + assert_parameters(IS_PMU_RTCEVT(Wakeup_Event)); + + /* Clear interrupt flag */ + RTC->INTSTS = Wakeup_Event; + /* Enable RTC interrupt */ + RTC->INTEN |= Wakeup_Event & (~0x01UL); +} + +/** + * @brief Set the deep sleep behavior when VDD/VDCIN is not drop. + * @param VDCIN_PDNS: + PMU_VDCINPDNS_0 , can't enter deep-sleep mode when VDCIN is not drop + can wake-up mcu from deep-sleep, when VDCIN is not drop. + PMU_VDCINPDNS_1 , The condition for entering deep sleep mode is independent of VDCIN. + VDD_PDNS: + PMU_VDDPDNS_0 , can't enter deep-sleep mode when VDD is not drop(>Threshold) + can wake-up mcu from deep-sleep, when VDD is not drop. + PMU_VDDPDNS_1 , The condition for entering deep sleep mode is independent of VDD. + * @retval None + */ +void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMU_VDCINPDNS(VDCIN_PDNS)); + assert_parameters(IS_PMU_VDDPDNS(VDD_PDNS)); + + tmp = ANA->CTRL; + tmp &= ~(ANA_CTRL_PDNS | ANA_CTRL_PDNS2); + tmp |= (VDCIN_PDNS | VDD_PDNS); + + ANA->CTRL = tmp; +} + +/** + * @brief BGP power control. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_BGP_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ana_reg3_tmp &= ~ANA_REG3_BGPPD; + else + ana_reg3_tmp |= ANA_REG3_BGPPD; + ANA->REG3 = ana_reg3_tmp; +} + +/** + * @brief Configure VDD alarm threshold voltage. + * @param PowerThreshold: + * PMU_PWTH_4_5 + * PMU_PWTH_4_2 + * PMU_PWTH_3_9 + * PMU_PWTH_3_6 + * PMU_PWTH_3_2 + * PMU_PWTH_2_9 + * PMU_PWTH_2_6 + * PMU_PWTH_2_3 + * @retval None + */ +void PMU_VDDAlarmTHConfig(uint32_t PowerThreshold) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMU_PWTH(PowerThreshold)); + + tmp = ANA->REG8; + tmp &= ~ANA_REG8_VDDPVDSEL; + tmp |= PowerThreshold; + + ANA->REG8 = tmp; +} + +/** + * @brief Get POWALARM status. + * @param None + * @retval POWALARM status + * 0: Voltage of VDD is higher than threshold. + * 1: Voltage of VDD is lower than threshold. + */ +uint8_t PMU_GetVDDALARMStatus(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_VDDALARM) + return 1; + else + return 0; +} + +/** + * @brief VDD detector enable control. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_VDDDetectorCmd(uint32_t NewState) +{ + /* Check parameter */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG9 &= ~ANA_REG9_PDDET; + else + ANA->REG9 |= ANA_REG9_PDDET; +} + +/** + * @brief Gets current MODE pin status. + * @param None + * @retval MODE pin status + * 0: Debug mode. + * 1: Normal mode. + */ +uint8_t PMU_GetModeStatus(void) +{ + if(PMU->STS & PMU_STS_MODE) + return 1; + else + return 0; +} + +/** + * @brief Control AVCC enable. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_AVCC_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG8 &= ~ANA_REG8_PD_AVCCLDO; + else + ANA->REG8 |= ANA_REG8_PD_AVCCLDO; +} + +/** + * @brief Control VDD33_O pin power. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_AVCCOutput_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + ANA->REGF &= ~ANA_REGF_AVCCO_EN; + else + ANA->REGF |= ANA_REGF_AVCCO_EN; +} + +/** + * @brief AVCC Low Voltage detector power control. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_AVCCLVDetector_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG5 &= ~ANA_REG5_PD_AVCCDET; + else + ANA->REG5 |= ANA_REG5_PD_AVCCDET; +} + +/** + * @brief Get AVCC low power status. + * @param None + * @retval low power status of AVCC + * 0: status not set, AVCC is higher than 2.5V. + * 1: status set, AVCC is lower than 2.5V. + */ +uint8_t PMU_GetAVCCLVStatus(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_AVCCLV) + return 1; + else + return 0; +} + +/** + * @brief Control VDCIN decector enable. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_VDCINDetector_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REGA &= ~ANA_REGA_PD_VDCINDET; + else + ANA->REGA |= ANA_REGA_PD_VDCINDET; +} + +/** + * @brief Get VDCIN drop status. + * @param None + * @retval drop status of VDCIN + * 0: status not set, VDCIN is not drop. + * 1: status set, VDCIN is drop. + */ +uint8_t PMU_GetVDCINDropStatus(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_VDCINDROP) + return 1; + else + return 0; +} + +/** + * @brief Discharge the BAT battery. + * @param BATDisc: + * PMU_BATRTC_DISC + * NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_PMU_BATRTCDISC(BATDisc)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG6 |= BATDisc; + else + ANA->REG6 &= ~BATDisc; +} + +/** + * @brief Power drop de-bounce control. + * @param Debounce: + * PMU_PWRDROP_DEB_0 + * PMU_PWRDROP_DEB_1 + * PMU_PWRDROP_DEB_2 + * PMU_PWRDROP_DEB_3 + * @retval None + */ +void PMU_PWRDropDEBConfig(uint32_t Debounce) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMU_PWRDROP_DEB(Debounce)); + + tmp = ANA->CTRL; + tmp &= ~ANA_CTRL_PWRDROPDEB; + tmp |= Debounce; + + ANA->CTRL = tmp; +} + +/** + * @brief Get last reset source. + * @param RSTSource: + PMU_RSTSRC_EXTRST + PMU_RSTSRC_PORST + PMU_RSTSRC_DPORST + * @retval 1:status set + 0:status reset + */ +uint8_t PMU_GetRSTSource(uint32_t RSTSource) +{ + /* Check parameters */ + assert_parameters(IS_PMU_RSTSRC(RSTSource)); + + if (PMU->STS & RSTSource) + { + PMU->STS = RSTSource; //Clear flag + return (1); + } + else + { + return (0); + } +} + +/** + * @brief Get power status. + * @param StatusMask: + PMU_PWRSTS_AVCCLV + PMU_PWRSTS_VDCINDROP + PMU_PWRSTS_VDDALARM + * @retval power status + * 1 status set + * 0 status not set + */ +uint8_t PMU_GetPowerStatus(uint32_t StatusMask) +{ + if (ANA->COMPOUT & StatusMask) + return 1; + else + return 0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pwm.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pwm.c new file mode 100644 index 0000000000..6b99c2be1c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pwm.c @@ -0,0 +1,466 @@ +/** + ****************************************************************************** + * @file lib_pwm.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief PWM library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_pwm.h" + +/** + * @brief PWM timebase initialization. + * @param PWMx: PWM0~PWM3 + InitStruct:PWM BASE configuration. + ClockDivision: + PWM_CLKDIV_2 + PWM_CLKDIV_4 + PWM_CLKDIV_8 + PWM_CLKDIV_16 + Mode: + PWM_MODE_STOP + PWM_MODE_UPCOUNT + PWM_MODE_CONTINUOUS + PWM_MODE_UPDOWN + ClockSource: + PWM_CLKSRC_APB + PWM_CLKSRC_APBD128 + * @retval None + */ +void PWM_BaseInit(PWM_TypeDef *PWMx, PWM_BaseInitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CLKDIV(InitStruct->ClockDivision)); + assert_parameters(IS_PWM_CNTMODE(InitStruct->Mode)); + assert_parameters(IS_PWM_CLKSRC(InitStruct->ClockSource)); + + tmp = PWMx->CTL; + tmp &= ~(PWM_CTL_ID\ + |PWM_CTL_MC\ + |PWM_CTL_TESL); + tmp |= (InitStruct->ClockDivision\ + |InitStruct->Mode\ + |InitStruct->ClockSource); + PWMx->CTL = tmp; +} + +/** + * @brief Fills each PWM_BaseInitType member with its default value. + * @param InitStruct: pointer to an PWM_BaseInitType structure which will be initialized. + * @retval None + */ +void PWM_BaseStructInit(PWM_BaseInitType *InitStruct) +{ + /*------------ Reset PWM base init structure parameters values ------------*/ + /* Initialize the ClockDivision member */ + InitStruct->ClockDivision = PWM_CLKDIV_2; + /* Initialize the ClockSource member */ + InitStruct->ClockSource = PWM_CLKSRC_APBD128; + /* Initialize the Mode member */ + InitStruct->Mode = PWM_MODE_STOP; +} + +/** + * @brief Fills each PWM_OCInitType member with its default value. + * @param OCInitType: pointer to an PWM_OCInitType structure which will be initialized. + * @retval None + */ +void PWM_OCStructInit(PWM_OCInitType *OCInitType) +{ + /*------- Reset PWM output channel init structure parameters values --------*/ + /* Initialize the OutMode member */ + OCInitType->OutMode = PWM_OUTMOD_CONST; + /* Initialize the Period member */ + OCInitType->Period = 0; +} + +/** + * @brief PWM output compare channel 0. + * @param PWMx: PWM0~PWM3 + OCInitType:PWM output compare configuration. + OutMode: + PWM_OUTMOD_CONST + PWM_OUTMOD_SET + PWM_OUTMOD_TOGGLE_RESET + PWM_OUTMOD_SET_RESET + PWM_OUTMOD_TOGGLE + PWM_OUTMOD_RESET + PWM_OUTMOD_TOGGLE_SET + PWM_OUTMOD_RESET_SET + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_OC0Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode)); + assert_parameters(IS_PWM_CCR(OCInitType->Period)); + + tmp = PWMx->CCTL0; + tmp &= ~(PWM_CCTL_OUTMOD | PWM_CCTL_CCIGG); + tmp |= OCInitType->OutMode; + PWMx->CCTL0 = tmp; + PWMx->CCR0 = OCInitType->Period; +} + +/** + * @brief PWM output compare channel 1. + * @param PWMx: PWM0~PWM3 + OCInitType:PWM output compare configuration. + OutMode: + PWM_OUTMOD_CONST + PWM_OUTMOD_SET + PWM_OUTMOD_TOGGLE_RESET + PWM_OUTMOD_SET_RESET + PWM_OUTMOD_TOGGLE + PWM_OUTMOD_RESET + PWM_OUTMOD_TOGGLE_SET + PWM_OUTMOD_RESET_SET + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_OC1Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode)); + assert_parameters(IS_PWM_CCR(OCInitType->Period)); + + tmp = PWMx->CCTL1; + tmp &= ~(PWM_CCTL_OUTMOD | PWM_CCTL_CCIGG); + tmp |= OCInitType->OutMode; + PWMx->CCTL1 = tmp; + PWMx->CCR1 = OCInitType->Period; +} + +/** + * @brief PWM output compare channel 2. + * @param PWMx: PWM0~PWM3 + OCInitType:PWM output compare configuration. + OutMode: + PWM_OUTMOD_CONST + PWM_OUTMOD_SET + PWM_OUTMOD_TOGGLE_RESET + PWM_OUTMOD_SET_RESET + PWM_OUTMOD_TOGGLE + PWM_OUTMOD_RESET + PWM_OUTMOD_TOGGLE_SET + PWM_OUTMOD_RESET_SET + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_OC2Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode)); + assert_parameters(IS_PWM_CCR(OCInitType->Period)); + + tmp = PWMx->CCTL2; + tmp &= ~(PWM_CCTL_OUTMOD | PWM_CCTL_CCIGG); + tmp |= OCInitType->OutMode; + PWMx->CCTL2 = tmp; + PWMx->CCR2 = OCInitType->Period; +} + +/** + * @brief PWM base interrupt configure. + * @param PWMx: PWM0~PWM3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void PWM_BaseINTConfig(PWM_TypeDef *PWMx, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = PWMx->CTL; + tmp &= ~(PWM_CTL_IE | PWM_CTL_IFG); + if (NewState == ENABLE) + { + tmp |= PWM_CTL_IE; + } + PWMx->CTL = tmp; +} + +/** + * @brief Get PWM base interrupt status. + * @param PWMx: PWM0~PWM3 + * @retval interrupt status. + */ +uint8_t PWM_GetBaseINTStatus(PWM_TypeDef *PWMx) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + + if (PWMx->CTL&PWM_CTL_IFG) + return 1; + else + return 0; +} + +/** + * @brief Clear PWM base interrupt status. + * @param PWMx: PWM0~PWM3 + * @retval None. + */ +void PWM_ClearBaseINTStatus(PWM_TypeDef *PWMx) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + + PWMx->CTL |= PWM_CTL_IFG; +} + +/** + * @brief channel interrupt configure. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void PWM_ChannelINTConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &PWMx->CCTL0 + Channel; + tmp = *addr; + tmp &= ~(PWM_CCTL_CCIE | PWM_CCTL_CCIGG); + if (NewState == ENABLE) + { + tmp |= PWM_CCTL_CCIE; + } + *addr = tmp; +} + +/** + * @brief Get channel interrupt status. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + * @retval interrupt status + */ +uint8_t PWM_GetChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + + addr = &PWMx->CCTL0 + Channel; + tmp = *addr; + if (tmp & PWM_CCTL_CCIGG) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear channel interrupt status. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + * @retval None + */ +void PWM_ClearChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + + addr = &PWMx->CCTL0 + Channel; + + tmp = *addr; + tmp &= ~PWM_CCTL_CCIGG; + tmp |= PWM_CCTL_CCIGG; + *addr = tmp; +} + +/** + * @brief PWM clear counter. + * @param PWMx: PWM0~PWM3 + * @retval None + */ +void PWM_ClearCounter(PWM_TypeDef *PWMx) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + + PWMx->CTL |= PWM_CTL_CLR; +} + +/** + * @brief Configure PWMx channelx's CCR value. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_CCRConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint16_t Period) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + + addr = &PWMx->CCR0 + Channel; + *addr = Period; +} + +/** + * @brief pwm output line selection. + * @param OutSelection: + PWM0_OUT0 + PWM0_OUT1 + PWM0_OUT2 + PWM1_OUT0 + PWM1_OUT1 + PWM1_OUT2 + PWM2_OUT0 + PWM2_OUT1 + PWM2_OUT2 + PWM3_OUT0 + PWM3_OUT1 + PWM3_OUT2 + OLine: can use the | operator + PWM_OLINE_0 + PWM_OLINE_1 + PWM_OLINE_2 + PWM_OLINE_3 + * @note PWM Single channel's output waveform can be output on multiple output lines. + * Multiple-line configuration can be performed by using the | operator. + * ex: PWM_OLineConfig(PWM0_OUT0, PWM_OLINE_0 | PWM_OLINE_2) + * PWM0 channel0 output by PWM0&PWM2's lien. + * @retval None + */ +void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine) +{ + uint32_t tmp; + uint32_t position = 0; + + /* Check parameters */ + assert_parameters(IS_PWM_OUTLINE(OLine)); + assert_parameters(IS_PWM_OUTSEL(OutSelection)); + + tmp = PWMMUX->OSEL; + while ((OLine >> position) != 0UL) + { + if ((OLine >> position) & 1UL) + { + tmp &= ~(PWM_O_SEL_O_SEL0 << (position * 4)); + tmp |= (OutSelection << (position * 4)); + } + position++; + } + PWMMUX->OSEL = tmp; +} + +/** + * @brief PWM output enable. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void PWM_OutputCmd(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &PWMx->CCTL0 + Channel; + tmp = *addr; + tmp &= ~PWM_CCTL_CCIGG; + if (NewState == ENABLE) + tmp |= PWM_CCTL_OUTEN; + else + tmp &= ~PWM_CCTL_OUTEN; + *addr = tmp; +} + +/** + * @brief Set channel output level. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + Level: + PWM_LEVEL_HIGH + PWM_LEVEL_LOW + * @retval None + */ +void PWM_SetOutLevel(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t Level) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_PWM_OUTLVL(Level)); + + addr = &PWMx->CCTL0 + Channel; + tmp = *addr; + tmp &= ~(PWM_CCTL_OUT | PWM_CCTL_CCIGG); + tmp |= Level; + *addr = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_rtc.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_rtc.c new file mode 100644 index 0000000000..855817dfee --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_rtc.c @@ -0,0 +1,667 @@ +/** + ****************************************************************************** + * @file lib_rtc.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief RTC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_rtc.h" + +#define RTCPWD_KEY 0x5AA55AA5 +#define RTCCE_SETKEY 0xA55AA55B +#define RTCCE_CLRKEY 0xA55AA55A + +/** + * @brief RTC registers write protection control. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void RTC_WriteProtection(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + /* Enable RTC Write-Protection */ + if (NewState != DISABLE) + { + RTC->PWD = RTCPWD_KEY; + RTC->CE = RTCCE_CLRKEY; + } + /* Disable RTC Write-Protection */ + else + { + RTC->PWD = RTCPWD_KEY; + RTC->CE = RTCCE_SETKEY; + } +} + +/** + * @brief Wait until the RTC registers (be W/R protected) are synchronized + * with RTC APB clock. + * + * @note The RTC Resynchronization mode is write protected, use the + * RTC_WriteProtection(DISABLE) before calling this function. + * Write-Operation process as follows: + * 1. RTC_WriteProtection(DISABLE); + * 2. RTC Registers write operation(only first write-operation be + * valid on the same register). + * 3. RTC_WriteProtection(ENABLE); + * 4. RTC_WaitForSynchro(); Wait until the RTC registers be + * synchronized by calling this function. + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + while (RTC->CE & RTC_CE_BSY) + { + } +} + +/** + * @brief Write RTC registers(continuous/be write-protected). + * @param[in] StartAddr the start address of registers be written + * @param[in] wBuffer pointer to write + * @param[in] Len number of registers be written + * @retval None + */ +void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len) +{ + uint8_t cnt; + + /* Parameter check */ + assert_parameters(IS_RTC_REGOP_STARTADDR(StartAddr)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + for (cnt=0; cntLOAD */ + tmp = RTC->LOAD; + tmp += 1; + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Read registers */ + for (cnt=0; cntYear)); + assert_parameters(IS_RTC_TIME_MONTH(sTime->Month)); + assert_parameters(IS_RTC_TIME_DATE(sTime->Date)); + assert_parameters(IS_RTC_TIME_WEEKDAY(sTime->WeekDay)); + assert_parameters(IS_RTC_TIME_HOURS(sTime->Hours)); + assert_parameters(IS_RTC_TIME_MINS(sTime->Minutes)); + assert_parameters(IS_RTC_TIME_SECS(sTime->Seconds)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write RTC time registers */ + RTC->SEC = sTime->Seconds; + RTC->MIN = sTime->Minutes; + RTC->HOUR = sTime->Hours; + RTC->DAY = sTime->Date; + RTC->WEEK = sTime->WeekDay; + RTC->MON = sTime->Month; + RTC->YEAR = sTime->Year; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Get RTC current time. + * @param gTime: Pointer to Time structure + * @retval None +*/ +void RTC_GetTime(RTC_TimeTypeDef *gTime) +{ + __IO uint32_t dummy_data = 0; + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Dummy read-operation to RTC->LOAD register */ + dummy_data = RTC->LOAD; + dummy_data += 1; + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Read RTC time registers */ + gTime->Seconds = RTC->SEC; + gTime->Minutes = RTC->MIN; + gTime->Hours = RTC->HOUR; + gTime->Date = RTC->DAY; + gTime->WeekDay = RTC->WEEK; + gTime->Month = RTC->MON; + gTime->Year = RTC->YEAR; +} + +/** + * @brief Interrupt configure. + * @param INTMask: can use the | operator + RTC_INT_CEILLE + RTC_INT_ACDONE + RTC_INT_WKUCNT + RTC_INT_MIDNIGHT + RTC_INT_WKUHOUR + RTC_INT_WKUMIN + RTC_INT_WKUSEC + RTC_INT_TIMEILLE + NewState: + ENABLE + DISABLE + * @retval None + */ +void RTC_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_RTC_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = RTC->INTEN; + tmp &= ~(0x1UL); + + if (NewState == ENABLE) + tmp |= INTMask; + else + tmp &= ~INTMask; + + RTC->INTEN = tmp; +} + +/** + * @brief Get interrupt status. + * @param INTMask: + RTC_INTSTS_CEILLE + RTC_INTSTS_ACDONE + RTC_INTSTS_WKUCNT + RTC_INTSTS_MIDNIGHT + RTC_INTSTS_WKUHOUR + RTC_INTSTS_WKUMIN + RTC_INTSTS_WKUSEC + RTC_INTSTS_TIMEILLE + * @retval 1: status set + 0: status reset. + */ +uint8_t RTC_GetINTStatus(uint32_t FlagMask) +{ + /* Parameter check */ + assert_parameters(IS_RTC_INTFLAGR(FlagMask)); + + if (RTC->INTSTS&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt status. + * @param INTMask: can use the | operator + RTC_INTSTS_CEILLE + RTC_INTSTS_ACDONE + RTC_INTSTS_WKUCNT + RTC_INTSTS_MIDNIGHT + RTC_INTSTS_WKUHOUR + RTC_INTSTS_WKUMIN + RTC_INTSTS_WKUSEC + RTC_INTSTS_TIMEILLE + * @retval None + */ +void RTC_ClearINTStatus(uint32_t FlagMask) +{ + /* Parameter check */ + assert_parameters(IS_RTC_INTFLAGC(FlagMask)); + + RTC->INTSTS = FlagMask; +} + +/** + * @brief Fills each RTCAC_InitStruct member with its default value. + * @param RTCAC_InitStruct: pointer to an RTC_AutCalType structure which will be initialized. + * @retval None + */ +void RTC_AutoCalStructInit(RTC_AutCalType *RTCAC_InitStruct) +{ + /*------------ Reset RTC AutCal init structure parameters values -----------*/ + /* Initialize the ADCSource member */ + RTCAC_InitStruct->ADCSource = RTC_ADCS_DATA; + /* Initialize the ATClockSource member */ + RTCAC_InitStruct->ATClockSource = RTC_ATCS_DISABLE; + /* Initialize the ATDelay member */ + RTCAC_InitStruct->ATDelay = RTC_ATDELAY_15MS; + /* Initialize the Period member */ + RTCAC_InitStruct->Period = 0; +} + +/** + * @brief Auto calibration initialization. + * @param InitStruct: pointer to AutoCal_InitType Auto calibration configuration. + * ATDelay: + * RTC_ATDELAY_15MS + * RTC_ATDELAY_31MS + * RTC_ATDELAY_62MS + * RTC_ATDELAY_125MS + * ATClockSource: + * RTC_ATCS_DISABLE + * RTC_ATCS_SEC + * RTC_ATCS_MIN + * RTC_ATCS_HOUR + * ADCSource: + * RTC_ADCS_DATA + * RTC_ADCS_PORT + * Period: 0 ~ 63 + * @note Auto trigger period is (Period+1)*1, unit is set by ATClockSource. + * Auto trigger function is not valid when ATClockSource is RTC_ATCS_DISABLE. + * @retval None + */ +void RTC_AutoCalInit(RTC_AutCalType *InitStruct) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_RTC_AUTOCAL_ATDLY(InitStruct->ATDelay)); + assert_parameters(IS_RTC_AUTOCAL_ATCS(InitStruct->ATClockSource)); + assert_parameters(IS_RTC_AUTOCAL_ADCSRC(InitStruct->ADCSource)); + assert_parameters(IS_RTC_AUTOCAL_PERIOD(InitStruct->Period)); + + tmp = RTC->ACCTRL; + tmp &= ~(RTC_ACCTRL_ACPER\ + |RTC_ACCTRL_ACDEL\ + |RTC_ACCTRL_ACCLK\ + |RTC_ACCTRL_ADCSEL); + tmp |= (InitStruct->ADCSource\ + |InitStruct->ATClockSource\ + |InitStruct->ATDelay\ + |((InitStruct->Period << RTC_ACCTRL_ACPER_Pos) & RTC_ACCTRL_ACPER)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + RTC->ACCTRL = tmp; + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief RTC automatic calibration auto-trigger source configure. + * @param TrigSource: + * RTC_ATCS_DISABLE + * RTC_ATCS_SEC + * RTC_ATCS_MIN + * RTC_ATCS_HOUR + * Period: 0 ~ 63 + * @retval None + */ +void RTC_TrigSourceConfig(uint32_t TrigSource, uint32_t Period) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_RTC_AUTOCAL_ATCS(TrigSource)); + assert_parameters(IS_RTC_AUTOCAL_PERIOD(Period)); + + tmp = RTC->ACCTRL; + tmp &= ~(RTC_ACCTRL_ACPER | RTC_ACCTRL_ACCLK); + tmp |= (TrigSource | (Period << RTC_ACCTRL_ACPER_Pos)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + RTC->ACCTRL = tmp; + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief ADC Auto-calibration enable control. + * @note When DISABLE is selected, the automatic triggering of the RTC-auto-calibration must be turned off by calling + * RTC_TrigSourceConfig(RTC_ATCS_DISABLE, 0) before using this function. + * @param NewState: + * ENABLE + * DISABLE + * @retval 0: Function succeeded + * 1: Function failded, the automatic triggering be enabled when DISABLE selected + */ +uint32_t RTC_AutoCalCmd(uint32_t NewState) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = RTC->ACCTRL; + if (NewState == DISABLE) + { + if (tmp & RTC_ACCTRL_ACCLK) + return 1; + else + tmp &= ~RTC_ACCTRL_ACEN; + } + else + { + tmp |= RTC_ACCTRL_ACEN; + } + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + RTC->ACCTRL = tmp; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + return 0; +} + +/** + * @brief Start RTC Auto-calibration manually. + * @param None + * @retval None + */ +void RTC_StartAutoCalManual(void) +{ + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* manual trigger Auto-calibration */ + RTC->ACCTRL |= RTC_ACCTRL_MANU; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Wait until Auto-calibration manual is done. + * @param None + * @retval None + */ +void RTC_WaitForAutoCalManual(void) +{ + while (RTC->ACCTRL&RTC_ACCTRL_MANU) + { + } +} + +/** + * @brief Get auto-calibration busy flag. + * @param None + * @retval 1 flag set + * 0 flag reset. + */ +uint8_t RTC_GetACBusyFlag(void) +{ + if (RTC->INTSTS & RTC_INTSTS_ACBSY) return (1); + else return (0); +} + + +/* + * @brief Multi-second wake up configure. + * @param nPeriodN seconds interval. + * @note For the first interrupt generated by calling this function, it may + * have < 1 sec error if the new WKUSEC number(parameter) is not equal + * to current WKUSEC number. If the new WKUSEC is equal to current WKUSEC, + * the first interrupt time may have 0~(WKUSEC +1) variation. + * To avoid this problem, set an alternative parameter (like 1) by calling + * this function, then set the correct parameter to it. + * @retval None + */ +void RTC_WKUSecondsConfig(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUSEC_PERIOD(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUSEC = nPeriod - 1; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/* + * @brief Multi-minute wake up configure. + * @param nPeriodN minute interval. + * @note For the first interrupt generated by calling this function, it may + * have < 1 min error if the new WKUMIN number(parameter) is not equal + * to current WKUMIN number. If the new WKUMIN is equal to current WKUMIN, + * the first interrupt time may have 0~(WKUMIN +1) variation. + * To avoid this problem, set an alternative parameter (like 1) by calling + * this function, then set the correct parameter to it. + * @retval None + */ +void RTC_WKUMinutesConfig(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUMIN_PERIOD(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUMIN = nPeriod - 1; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/* + * @brief Multi-hour wake up configure. + * @param nPeriodN hour interval. + * @note For the first interrupt generated by calling this function, it may + * have < 1 hour error if the new WKUHOUR number(parameter) is not equal + * to current WKUHOUR number. If the new WKUHOUR is equal to current WKUHOUR, + * the first interrupt time may have 0~(WKUHOUR +1) variation. + * To avoid this problem, set an alternative parameter (like 1) by calling + * this function, then set the correct parameter to it. + * @retval None + */ +void RTC_WKUHoursConfig(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUHOUR_PERIOD(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUHOUR = nPeriod - 1; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief RTC counter wake up configure. + * @param nClock: 1 ~ 0x1000000 + CNTCLK: + RTC_WKUCNT_RTCCLK + RTC_WKUCNT_2048 + RTC_WKUCNT_512 + RTC_WKUCNT_128 + * @retval None + */ +void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUCNT_PERIOD(nClock)); + assert_parameters(IS_RTC_WKUCNT_CNTSEL(CNTCLK)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUCNT = (CNTCLK & RTC_WKUCNT_CNTSEL) | (nClock -1 ); + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Gets RTC wake-up counter value. + * @retval RTC wake-up counter value + */ +uint32_t RTC_GetWKUCounterValue(void) +{ + return RTC->WKUCNTR; +} + +/** + * @brief RTC clock prescaler configure. + * @param[in] Prescaler: + * RTC_CLKDIV_1 + * RTC_CLKDIV_4 + * @retval None + */ +void RTC_PrescalerConfig(uint32_t Prescaler) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_RTC_CLKDIV(Prescaler)); + + tmp = RTC->PSCA; + tmp &= ~RTC_PSCA_PSCA; + tmp |= Prescaler; + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + RTC->PSCA = tmp; + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief RTC PLLDIV frequency configure. + * @param nfrequency(HZ): the frequency of RTC PLLDIV output configuration. + * @note Ensure clocks be configured by calling function CLK_ClockConfig(), + * get correct PCLK frequency by calling function CLK_GetPCLKFreq(). + * @retval None + */ +void RTC_PLLDIVConfig(uint32_t nfrequency) +{ + RTC->DIV = CLK_GetPCLKFreq()/2/nfrequency - 1; +} + +/** + * @brief RTC PLLDIV output enable. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void RTC_PLLDIVOutputCmd(uint8_t NewState) +{ + /* Parameter check */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) RTC->CTL |= RTC_CTL_RTCPLLOE; + else RTC->CTL &= ~RTC_CTL_RTCPLLOE; +} + + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_spi.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_spi.c new file mode 100644 index 0000000000..b134d359cd --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_spi.c @@ -0,0 +1,430 @@ +/** + ****************************************************************************** + * @file lib_spi.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief SPI library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_spi.h" + +#define SPI_MISC_RSTValue (0UL) + +/** + * @brief Reset SPI controller. + * @param SPIx:SPI1~SPI2 + * @retval None + */ +void SPI_DeviceInit(SPI_TypeDef *SPIx) +{ + __IO uint32_t dummy_data = 0UL; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + /* Disable SPI */ + SPIx->CTRL = 0; + /* SPI soft reset */ + SPIx->CTRL |= SPI_CTRL_SPIRST; + SPIx->CTRL &= ~SPI_CTRL_SPIRST; + /* Clear flag */ + dummy_data = SPIx->RXDAT; + dummy_data += 1; + SPIx->TXSTS = SPI_TXSTS_TXIF; + SPIx->RXSTS = SPI_RXSTS_RXIF; + /* write default values */ + SPIx->MISC_ = SPI_MISC_RSTValue; +} + +/** + * @brief Fills each SPI_InitType member with its default value. + * @param InitStruct: pointer to an SPI_InitType structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitType *InitStruct) +{ + /*--------------- Reset SPI init structure parameters values ---------------*/ + /* Initialize the ClockDivision member */ + InitStruct->ClockDivision = SPI_CLKDIV_2; + /* Initialize the CSNSoft member */ + InitStruct->CSNSoft = SPI_CSNSOFT_DISABLE; + /* Initialize the Mode member */ + InitStruct->Mode = SPI_MODE_MASTER; + /* Initialize the SPH member */ + InitStruct->SPH = SPI_SPH_0; + /* Initialize the SPO member */ + InitStruct->SPO = SPI_SPO_0; + /* Initialize the SWAP member */ + InitStruct->SWAP = SPI_SWAP_DISABLE; +} + +/** + * @brief SPI initialization. + * @param SPIx:SPI1~SPI2 + InitStruct: SPI configuration. + Mode: + SPI_MODE_MASTER + SPI_MODE_SLAVE + SPH: + SPI_SPH_0 + SPI_SPH_1 + SPO: + SPI_SPO_0 + SPI_SPO_1 + ClockDivision: + SPI_CLKDIV_2 + SPI_CLKDIV_4 + SPI_CLKDIV_8 + SPI_CLKDIV_16 + SPI_CLKDIV_32 + SPI_CLKDIV_64 + SPI_CLKDIV_128 + CSNSoft: + SPI_CSNSOFT_ENABLE + SPI_CSNSOFT_DISABLE + SWAP: + SPI_SWAP_ENABLE + SPI_SWAP_DISABLE + * @retval None + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_MODE(InitStruct->Mode)); + assert_parameters(IS_SPI_SPH(InitStruct->SPH)); + assert_parameters(IS_SPI_SPO(InitStruct->SPO)); + assert_parameters(IS_SPI_CLKDIV(InitStruct->ClockDivision)); + assert_parameters(IS_SPI_CSN(InitStruct->CSNSoft)); + assert_parameters(IS_SPI_SWAP(InitStruct->SWAP)); + + tmp = SPIx->CTRL; + tmp &= ~(SPI_CTRL_MOD\ + |SPI_CTRL_SCKPHA\ + |SPI_CTRL_SCKPOL\ + |SPI_CTRL_CSGPIO\ + |SPI_CTRL_SWAP\ + |SPI_CTRL_SCKSEL); + tmp |= (InitStruct->Mode\ + |InitStruct->SPH\ + |InitStruct->SPO\ + |InitStruct->CSNSoft\ + |InitStruct->SWAP\ + |InitStruct->ClockDivision); + SPIx->CTRL = tmp; +} + +/** + * @brief Enables or disables SPI. + * @param SPIx:SPI1~SPI2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_Cmd(SPI_TypeDef *SPIx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + SPIx->CTRL |= SPI_CTRL_SPIEN; + else + SPIx->CTRL &= ~SPI_CTRL_SPIEN; +} + +/** + * @brief SPI interrupt config. + * @param SPIx:SPI1~SPI2 + INTMask: can use the | operator + SPI_INT_TX + SPI_INT_RX + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_INTConfig(SPI_TypeDef *SPIx, uint32_t INTMask, uint32_t NewState) +{ + uint32_t tmp, tmp_INTMask; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp_INTMask = INTMask; + if (tmp_INTMask & 0x80000000) + { + INTMask &= 0xFFFF; + tmp = SPIx->TXSTS; + tmp &= ~SPI_TXSTS_TXIF; + if (NewState == ENABLE) + { + tmp |= INTMask; + SPIx->TXSTS = tmp; + } + else + { + tmp &= ~INTMask; + SPIx->TXSTS = tmp; + } + } + if (tmp_INTMask & 0x40000000) + { + INTMask &= 0xFFFF; + tmp = SPIx->RXSTS; + tmp &= ~SPI_RXSTS_RXIF; + if (NewState == ENABLE) + { + tmp |= INTMask; + SPIx->RXSTS = tmp; + } + else + { + tmp &= ~INTMask; + SPIx->RXSTS = tmp; + } + } +} + +/** + * @brief Get status flag. + * @param SPIx:SPI1~SPI2 + Status: + SPI_STS_TXIF + SPI_STS_TXEMPTY + SPI_STS_TXFUR + SPI_STS_RXIF + SPI_STS_RXFULL + SPI_STS_RXFOV + SPI_STS_BSY + SPI_STS_RFF + SPI_STS_RNE + SPI_STS_TNF + SPI_STS_TFE + * @retval Flag status. + */ +uint8_t SPI_GetStatus(SPI_TypeDef *SPIx, uint32_t Status) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_STSR(Status)); + + if ((Status&0xE0000000) == 0x80000000) + { + if (Status&SPIx->TXSTS) + return 1; + else + return 0; + } + else if ((Status&0xE0000000) == 0x40000000) + { + if (Status&SPIx->RXSTS) + return 1; + else + return 0; + } + else + { + if (Status&SPIx->MISC_) + return 1; + else + return 0; + } +} + +/** + * @brief Clear status flag. + * @param SPIx:SPI1~SPI2 + Status: can use the | operator + SPI_STS_TXIF + SPI_STS_RXIF + * @retval None + */ +void SPI_ClearStatus(SPI_TypeDef *SPIx, uint32_t Status) +{ + uint32_t tmp_status; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_STSC(Status)); + + tmp_status = Status; + if (tmp_status & 0x80000000) + { + Status &= 0xFFFF; + SPIx->TXSTS |= Status; + } + if (tmp_status & 0x40000000) + { + Status &= 0xFFFF; + SPIx->RXSTS |= Status; + } +} + +/** + * @brief Load send data register. + * @param SPIx:SPI1~SPI2 + ch: data write to send data register + * @retval None + */ +void SPI_SendData(SPI_TypeDef *SPIx, uint8_t ch) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + SPIx->TXDAT = ch; +} + +/** + * @brief Read receive data register. + * @param SPIx:SPI1~SPI2 + * @retval receive data value + */ +uint8_t SPI_ReceiveData(SPI_TypeDef *SPIx) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + return (SPIx->RXDAT); +} + +/** + * @brief Transmit fifo level configure. + * @param SPIx:SPI1~SPI2 + FIFOLevel: + SPI_TXFLEV_0 + SPI_TXFLEV_1 + SPI_TXFLEV_2 + SPI_TXFLEV_3 + SPI_TXFLEV_4 + SPI_TXFLEV_5 + SPI_TXFLEV_6 + SPI_TXFLEV_7 + * @retval None + */ +void SPI_TransmitFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_TXFLEV(FIFOLevel)); + + tmp = SPIx->TXSTS; + tmp &= ~(SPI_TXSTS_TXFLEV | SPI_TXSTS_TXIF); + tmp |= FIFOLevel; + SPIx->TXSTS = tmp; +} + +/** + * @brief Receive fifo level configure. + * @param SPIx:SPI1~SPI2 + FIFOLevel: + SPI_RXFLEV_0 + SPI_RXFLEV_1 + SPI_RXFLEV_2 + SPI_RXFLEV_3 + SPI_RXFLEV_4 + SPI_RXFLEV_5 + SPI_RXFLEV_6 + SPI_RXFLEV_7 + * @retval None + */ +void SPI_ReceiveFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_RXFLEV(FIFOLevel)); + + tmp = SPIx->RXSTS; + tmp &= ~(SPI_RXSTS_RXFLEV | SPI_RXSTS_RXIF); + tmp |= FIFOLevel; + SPIx->RXSTS = tmp; +} + +/** + * @brief Get transmit fifo level. + * @param SPIx:SPI1~SPI2 + * @retval Transmit fifo level. + */ +uint8_t SPI_GetTransmitFIFOLevel(SPI_TypeDef *SPIx) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + return (SPIx->TXSTS & SPI_TXSTS_TXFFLAG); +} + +/** + * @brief Get receive fifo level. + * @param SPIx:SPI1~SPI2 + * @retval Receive fifo level. + */ +uint8_t SPI_GetReceiveFIFOLevel(SPI_TypeDef *SPIx) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + return (SPIx->RXSTS & SPI_RXSTS_RXFFLAG); +} + +/** + * @brief FIFO smart mode. + * @param SPIx:SPI1~SPI2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_SmartModeCmd(SPI_TypeDef *SPIx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + SPIx->MISC_ |= SPI_MISC_SMART; + } + else + { + SPIx->MISC_ &= ~SPI_MISC_SMART; + } +} + +/** + * @brief FIFO over write mode. + * @param SPIx:SPI1~SPI2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_OverWriteModeCmd(SPI_TypeDef *SPIx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + SPIx->MISC_ |= SPI_MISC_OVER; + } + else + { + SPIx->MISC_ &= ~SPI_MISC_OVER; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_tmr.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_tmr.c new file mode 100644 index 0000000000..b022bb511c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_tmr.c @@ -0,0 +1,178 @@ +/** + ****************************************************************************** + * @file lib_tmr.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Timer library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_tmr.h" + +#define TMR_CTRL_RSTValue (0UL) +#define TMR_VALUE_RSTValue (0UL) +#define TMR_RELOAD_RSTValue (0UL) + +/** + * @brief Initializes the TMRx peripheral registers to their default reset values. + * @param TMRx: + TMR0 ~ TMR3 + * @retval None + */ +void TMR_DeInit(TMR_TypeDef *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + /* Disable timer */ + TMRx->CTRL &= ~TMR_CTRL_EN; + /* clear interrupt status */ + TMRx->INT = TMR_INT_INT; + /* write default reset values */ + TMRx->CTRL = TMR_CTRL_RSTValue; + TMRx->RELOAD = TMR_RELOAD_RSTValue; + TMRx->VALUE = TMR_VALUE_RSTValue; +} + +/** + * @brief TMR initialization. + * @param TMRx: + TMR0 ~ TMR3 + InitStruct: Timer configuration. + ClockSource: + TMR_CLKSRC_INTERNAL + TMR_CLKSRC_EXTERNAL + EXTGT: + TMR_EXTGT_DISABLE + TMR_EXTGT_ENABLE + Period: the auto-reload value + * @retval None + */ +void TMR_Init(TMR_TypeDef *TMRx, TMR_InitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + assert_parameters(IS_TMR_CLKSRC(InitStruct->ClockSource)); + assert_parameters(IS_TMR_EXTGT(InitStruct->EXTGT)); + + tmp = TMRx->CTRL; + tmp &= ~(TMR_CTRL_EXTCLK|TMR_CTRL_EXTEN); + tmp |= (InitStruct->ClockSource|InitStruct->EXTGT); + TMRx->CTRL = tmp; + TMRx->VALUE = InitStruct->Period; + TMRx->RELOAD = InitStruct->Period; +} + +/** + * @brief Fills each TMR_InitType member with its default value. + * @param InitStruct: pointer to an TMR_InitType structure which will be initialized. + * @retval None + */ +void TMR_StructInit(TMR_InitType *InitStruct) +{ + /*--------------- Reset TMR init structure parameters values ---------------*/ + /* Initialize the ClockSource member */ + InitStruct->ClockSource = TMR_CLKSRC_INTERNAL; + /* Initialize the EXTGT member */ + InitStruct->EXTGT = TMR_EXTGT_DISABLE; + /* Initialize the Period member */ + InitStruct->Period = 0; +} + +/** + * @brief Interrupt configuration. + * @param TMRx: + TMR0~TMR3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void TMR_INTConfig(TMR_TypeDef *TMRx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + TMRx->CTRL |= TMR_CTRL_INTEN; + } + else + { + TMRx->CTRL &= ~TMR_CTRL_INTEN; + } +} + +/** + * @brief Get timer interrupt status. + * @param TMRx: + TMR0~TMR3 + * @retval Interrupt status. + */ +uint8_t TMR_GetINTStatus(TMR_TypeDef *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + if (TMRx->INT&TMR_INT_INT) + return 1; + else + return 0; +} + +/** + * @brief Clear timer interrupt status bit. + * @param TMRx: + TMR0~TMR3 + * @retval None. + */ +void TMR_ClearINTStatus(TMR_TypeDef *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + TMRx->INT = TMR_INT_INT; +} + +/** + * @brief TMRER enable. + * @param TMRx: + TMR0~TMR3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void TMR_Cmd(TMR_TypeDef *TMRx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + TMRx->CTRL |= TMR_CTRL_EN; + else + TMRx->CTRL &= ~TMR_CTRL_EN; +} + +/** + * @brief Get TMRx current value. + * @param TMRx: + TMR0~TMR3 + * @retval timer value. + */ +uint32_t TMR_GetCurrentValue(TMR_TypeDef *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + return (TMRx->VALUE); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_u32k.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_u32k.c new file mode 100644 index 0000000000..4d321ec9f3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_u32k.c @@ -0,0 +1,317 @@ +/** + ****************************************************************************** + * @file lib_u32k.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief UART 32K library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_u32k.h" + +#define U32K_STS_Msk (0x7UL) +#define U32K_CTRL0_RSTValue (0UL) +#define U32K_CTRL1_RSTValue (0UL) +#define U32K_PHASE_RSTValue (0x4B00UL) + +/** + * @brief Initializes the U32Kx peripheral registers to their default reset + values. + * @param U32Kx: U32K0~U32K1 + * @retval None + */ +void U32K_DeInit(U32K_TypeDef *U32Kx) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + + /* Disable U32K */ + U32Kx->CTRL0 &= ~U32K_CTRL0_EN; + /* clear interrupt status */ + U32Kx->STS = U32K_STS_Msk; + /* write default reset values */ + U32Kx->CTRL0 = U32K_CTRL0_RSTValue; + U32Kx->CTRL1 = U32K_CTRL1_RSTValue; + U32Kx->PHASE = U32K_PHASE_RSTValue; +} + +/** + * @brief U32K initialization. + * @param U32Kx: + U32K0~U32K1 + InitStruct: U32K configuration + Debsel: + U32K_DEBSEL_0 + U32K_DEBSEL_1 + U32K_DEBSEL_2 + U32K_DEBSEL_3 + Parity: + U32K_PARITY_EVEN + U32K_PARITY_ODD + U32K_PARITY_0 + U32K_PARITY_1 + U32K_PARITY_NONE + WordLen: + U32K_WORDLEN_8B + U32K_WORDLEN_9B + FirstBit: + U32K_FIRSTBIT_LSB + U32K_FIRSTBIT_MSB + AutoCal: + U32K_AUTOCAL_ON + U32K_AUTOCAL_OFF + LineSel: + U32K_LINE_RX0 + U32K_LINE_RX1 + U32K_LINE_RX2 + U32K_LINE_RX3 + Baudrate: Baudrate value + * @retval None + */ +void U32K_Init(U32K_TypeDef *U32Kx, U32K_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_DEBSEL(InitStruct->Debsel)); + assert_parameters(IS_U32K_PARITY(InitStruct->Parity)); + assert_parameters(IS_U32K_WORDLEN(InitStruct->WordLen)); + assert_parameters(IS_U32K_FIRSTBIT(InitStruct->FirstBit)); + assert_parameters(IS_U32K_AUTOCAL(InitStruct->AutoCal)); + assert_parameters(IS_U32K_LINE(InitStruct->LineSel)); + assert_parameters(IS_U32K_BAUDRATE(InitStruct->Baudrate)); + + tmp_reg1 = U32Kx->CTRL0; + tmp_reg1 &= ~(U32K_CTRL0_DEBSEL\ + |U32K_CTRL0_PMODE\ + |U32K_CTRL0_MODE\ + |U32K_CTRL0_MSB\ + |U32K_CTRL0_ACOFF); + tmp_reg1 |= (InitStruct->Debsel\ + |InitStruct->Parity\ + |InitStruct->WordLen\ + |InitStruct->FirstBit\ + |InitStruct->AutoCal); + U32Kx->CTRL0 = tmp_reg1; + if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz + U32Kx->PHASE = 65536*InitStruct->Baudrate/32768; + else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz + U32Kx->PHASE = 65536*InitStruct->Baudrate/8192; + else + assert_parameters(0); + + tmp_reg2 = U32Kx->CTRL1; + tmp_reg2 &= ~(U32K_CTRL1_RXSEL); + tmp_reg2 |= (InitStruct->LineSel); + U32Kx->CTRL1 = tmp_reg2; +} + +/** + * @brief Fills each U32K_InitType member with its default value. + * @param InitStruct: pointer to an U32K_InitType structure which will be initialized. + * @retval None + */ +void U32K_StructInit(U32K_InitType *InitStruct) +{ + /*-------------- Reset U32K init structure parameters values ---------------*/ + /* Initialize the AutoCal member */ + InitStruct->AutoCal = U32K_AUTOCAL_ON; + /* Initialize the Baudrate member */ + InitStruct->Baudrate = 9600; + /* Initialize the Debsel member */ + InitStruct->Debsel = U32K_DEBSEL_0; + /* Initialize the FirstBit member */ + InitStruct->FirstBit = U32K_FIRSTBIT_LSB; + /* Initialize the LineSel member */ + InitStruct->LineSel = U32K_LINE_RX0; + /* Initialize the Parity member */ + InitStruct->Parity = U32K_PARITY_NONE; + /* Initialize the Parity member */ + InitStruct->WordLen = U32K_WORDLEN_8B; +} + +/** + * @brief U32K interrupt configuration. + * @param U32Kx: + U32K0~U32K1 + INTMask: can use the | operator + U32K_INT_RXOV + U32K_INT_RXPE + U32K_INT_RX + NewState: + ENABLE + DISABLE + * @retval None + */ +void U32K_INTConfig(U32K_TypeDef *U32Kx, uint32_t INTMask, uint8_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = U32Kx->CTRL1; + tmp &= ~INTMask; + if (NewState == ENABLE) + { + tmp |= INTMask; + } + U32Kx->CTRL1 = tmp; +} + +/** + * @brief Get interrupt flag status. + * @param U32Kx: + U32K0~U32K1 + INTMask: + U32K_INTSTS_RXOV + U32K_INTSTS_RXPE + U32K_INTSTS_RX + * @retval Flag status + */ +uint8_t U32K_GetINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_INTFLAGR(INTMask)); + + if (U32Kx->STS&INTMask) + return 1; + else + return 0; +} + +/** + * @brief Clear flag status. + * @param U32Kx: + U32K0~U32K1 + INTMask: can use the | operator + U32K_INTSTS_RXOV + U32K_INTSTS_RXPE + U32K_INTSTS_RX + * @retval None + */ +void U32K_ClearINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_INTFLAGC(INTMask)); + + U32Kx->STS = INTMask; +} + +/** + * @brief Read receive data register. + * @param U32Kx: + U32K0~U32K1 + * @retval Receive data value + */ +uint8_t U32K_ReceiveData(U32K_TypeDef *U32Kx) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + + return (U32Kx->DATA); +} + +/** + * @brief U32K Baudrate control. + * @param U32Kx: U32K0~U32K1 + BaudRate: Baudrate value + * @retval None + */ +void U32K_BaudrateConfig(U32K_TypeDef *U32Kx, uint32_t BaudRate) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_BAUDRATE(BaudRate)); + + if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz + U32Kx->PHASE = 65536*BaudRate/32768; + else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz + U32Kx->PHASE = 65536*BaudRate/8192; + else + assert_parameters(0); +} + +/** + * @brief U32K controlller enable. + * @param U32Kx: + U32K0~U32K1 + NewState: + ENABLE + DISABLE + * @retval None + */ +void U32K_Cmd(U32K_TypeDef *U32Kx, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = U32Kx->CTRL0; + tmp &= ~(U32K_CTRL0_EN); + if (NewState == ENABLE) + { + tmp |= U32K_CTRL0_EN; + } + U32Kx->CTRL0 = tmp; +} + +/** + * @brief U32K receive line selection. + * @param U32Kx: + U32K0~U32K1 + Line: + U32K_LINE_RX0 + U32K_LINE_RX1 + U32K_LINE_RX2 + U32K_LINE_RX3 + * @retval None + */ +void U32K_LineConfig(U32K_TypeDef *U32Kx, uint32_t Line) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_LINE(Line)); + + tmp = U32Kx->CTRL1; + tmp &= ~U32K_CTRL1_RXSEL; + tmp |= Line; + U32Kx->CTRL1 = tmp; +} + +/** + * @brief Wake-up mode configure. + * @param U32Kx: + U32K0~U32K1 + WKUMode: + U32K_WKUMOD_RX + U32K_WKUMOD_PC + * @retval None + */ +void U32K_WKUModeConfig(U32K_TypeDef *U32Kx, uint32_t WKUMode) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_WKUMODE(WKUMode)); + + tmp = U32Kx->CTRL0; + tmp &= ~U32K_CTRL0_WKUMODE; + tmp |= WKUMode; + U32Kx->CTRL0 = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_uart.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_uart.c new file mode 100644 index 0000000000..7aeecea45b --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_uart.c @@ -0,0 +1,391 @@ +/** + ****************************************************************************** + * @file lib_uart.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief UART library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_uart.h" +#include "lib_clk.h" + +#define UART_STATE_RCMsk (0x3CUL) +#define UART_INTSTS_RCMsk (0x3FUL) +#define UART_BAUDDIV_RSTValue (0UL) +#define UART_CTRL_RSTValue (0UL) +#define UART_CTRL2_RSTValue (0UL) + +/** + * @brief Iinitializes the UARTx peripheral registers to their default reset + values. + * @param UARTx: UART0~UART5 + * @retval None + */ +void UART_DeInit(UART_TypeDef *UARTx) +{ + __IO uint32_t dummy_data = 0UL; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + /* read data, clear RXFULL flag */ + dummy_data = UARTx->DATA; + dummy_data += 1; + + UARTx->INTSTS = UART_INTSTS_RCMsk; + UARTx->STATE = UART_STATE_RCMsk; + UARTx->BAUDDIV = UART_BAUDDIV_RSTValue; + UARTx->CTRL2 = UART_CTRL2_RSTValue; + UARTx->CTRL = UART_CTRL_RSTValue; +} + +/** + * @brief UART initialization. + * @param UARTx: UART0~UART5 + InitStruct:UART configuration. + Mode: (between UART_MODE_RX and UART_MODE_TX, can use the | operator) + UART_MODE_RX + UART_MODE_TX + UART_MODE_OFF + Parity: + UART_PARITY_EVEN + UART_PARITY_ODD + UART_PARITY_0 + UART_PARITY_1 + UART_PARITY_NONE + WordLen: + UART_WORDLEN_8B + UART_WORDLEN_9B + FirstBit: + UART_FIRSTBIT_LSB + UART_FIRSTBIT_MSB + Baudrate: Baudrate value + * @retval None + */ +void UART_Init(UART_TypeDef *UARTx, UART_InitType *InitStruct) +{ + uint32_t pclk; + uint32_t div; + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_MODE(InitStruct->Mode)); + assert_parameters(IS_UART_PARITY(InitStruct->Parity)); + assert_parameters(IS_UART_WORDLEN(InitStruct->WordLen)); + assert_parameters(IS_UART_FIRSTBIT(InitStruct->FirstBit)); + assert_parameters(IS_UART_BAUDRATE(InitStruct->Baudrate)); + + tmp_reg1 = UARTx->CTRL; + tmp_reg1 &= ~(UART_CTRL_RXEN\ + |UART_CTRL_TXEN); + tmp_reg1 |= (InitStruct->Mode); + + tmp_reg2 = UARTx->CTRL2; + tmp_reg2 &= ~(UART_CTRL2_MSB \ + |UART_CTRL2_MODE \ + |UART_CTRL2_PMODE); + tmp_reg2 |= (InitStruct->Parity\ + |InitStruct->WordLen\ + |InitStruct->FirstBit); + UARTx->CTRL2 = tmp_reg2; + + pclk = CLK_GetPCLKFreq(); + div = pclk/InitStruct->Baudrate; + + if ((pclk%InitStruct->Baudrate) > (InitStruct->Baudrate/2)) + { + div++; + } + + UARTx->BAUDDIV = div; + UARTx->CTRL = tmp_reg1; +} + +/** + * @brief Fills each UART_InitType member with its default value. + * @param InitStruct: pointer to an UART_InitType structure which will be initialized. + * @retval None + */ +void UART_StructInit(UART_InitType *InitStruct) +{ + /*-------------- Reset UART init structure parameters values ---------------*/ + /* Initialize the Baudrate member */ + InitStruct->Baudrate = 9600; + /* Initialize the FirstBit member */ + InitStruct->FirstBit = UART_FIRSTBIT_LSB; + /* Initialize the Mode member */ + InitStruct->Mode = UART_MODE_OFF; + /* Initialize the Parity member */ + InitStruct->Parity = UART_PARITY_NONE; + /* Initialize the WordLen member */ + InitStruct->WordLen = UART_WORDLEN_8B; +} + +/** + * @brief Get peripheral flag. + * @param UARTx: UART0~UART5 + FlagMask: flag to get. + --UART_FLAG_RXPARITY + --UART_FLAG_TXDONE + --UART_FLAG_RXPE + --UART_FLAG_RXOV + --UART_FLAG_TXOV + --UART_FLAG_RXFULL + * @retval 1:flag set + 0:flag reset + */ +uint8_t UART_GetFlag(UART_TypeDef *UARTx, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_FLAGR(FlagMask)); + + if (UARTx->STATE&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear peripheral flag. + * @param UARTx: UART0~UART5 + FlagMask: status to clear, can use the | operator. + --UART_FLAG_TXDONE + --UART_FLAG_RXPE + --UART_FLAG_RXOV + --UART_FLAG_TXOV + * @retval None + */ +void UART_ClearFlag(UART_TypeDef *UARTx, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_FLAGC(FlagMask)); + + UARTx->STATE = FlagMask; +} + +/** + * @brief Enable or disable the specified UART interrupts. + * @param UARTx: UART0~UART5 + INTMask: can use the | operator. + --UART_INT_TXDONE + --UART_INT_RXPE + --UART_INT_RXOV + --UART_INT_TXOV + --UART_INT_RX + NewState:New status of interrupt mask. + * @retval None + */ +void UART_INTConfig(UART_TypeDef *UARTx, uint32_t INTMask, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + UARTx->CTRL |= INTMask; + } + else + { + UARTx->CTRL &= ~INTMask; + } +} + +/** + * @brief Get interrupt status. + * @param UARTx: UART0~UART5 + INTMask: status to get. + --UART_INTSTS_TXDONE + --UART_INTSTS_RXPE + --UART_INTSTS_RXOV + --UART_INTSTS_TXOV + --UART_INTSTS_RX + * @retval 1:status set + 0:status reset + */ +uint8_t UART_GetINTStatus(UART_TypeDef *UARTx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_INTFLAGR(INTMask)); + + if (UARTx->INTSTS&INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt status. + * @param UARTx: UART0~UART5 + INTMask: status to clear, can use the | operator. + --UART_INTSTS_TXDONE + --UART_INTSTS_RXPE + --UART_INTSTS_RXOV + --UART_INTSTS_TXOV + --UART_INTSTS_RX + * @retval None + */ +void UART_ClearINTStatus(UART_TypeDef *UARTx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_INTFLAGC(INTMask)); + + UARTx->INTSTS = INTMask; +} + +/** + * @brief Load send data register. + * @param UARTx: UART0~USART5 + DAT: data to send. + * @retval None + */ +void UART_SendData(UART_TypeDef *UARTx, uint8_t ch) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + UARTx->DATA = ch; +} + +/** + * @brief Read receive data register. + * @param UARTx: UART0~UART5 + * @retval The received data. + */ +uint8_t UART_ReceiveData(UART_TypeDef *UARTx) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + return UARTx->DATA; +} + +/** + * @brief UART Baudrate control. + * @param UARTx: UART0~UART5 + BaudRate: Baudrate value + * @retval None + */ +void UART_BaudrateConfig(UART_TypeDef *UARTx, uint32_t BaudRate) +{ + uint32_t pclk; + uint32_t div; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_BAUDRATE(BaudRate)); + + pclk = CLK_GetPCLKFreq(); + div = pclk/BaudRate; + if ((pclk%BaudRate) > (BaudRate/2)) + { + div++; + } + + UARTx->BAUDDIV = div; +} + +/** + * @brief UART Transmit/Receive enable control. + * @param UARTx: UART0~UART5 + Mode: + UART_MODE_RX + UART_MODE_TX + NewState: + ENABLE + DISABLE + * @retval None + */ +void UART_Cmd(UART_TypeDef *UARTx, uint32_t Mode, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_MODE(Mode)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + UARTx->CTRL |= Mode; + } + else + { + UARTx->CTRL &= ~Mode; + } +} + +/** + * @brief Get UART configure information. + * @param UARTx: UART0~UART5 + * ConfigInfo: The pointer of UART configuration. + * @retval None + */ +void UART_GetConfigINFO(UART_TypeDef *UARTx, UART_ConfigINFOType *ConfigInfo) +{ + uint32_t tmp1, tmp2, tmp3; + uint32_t pclk; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + tmp1 = UARTx->CTRL; + tmp2 = UARTx->BAUDDIV; + pclk = CLK_GetPCLKFreq(); + tmp3 = UARTx->CTRL2; + + /* Mode_Transmit */ + if (tmp1 & UART_CTRL_TXEN) + ConfigInfo->Mode_Transmit = 1; + else + ConfigInfo->Mode_Transmit = 0; + + /* Mode_Receive */ + if (tmp1 & UART_CTRL_RXEN) + ConfigInfo->Mode_Receive = 1; + else + ConfigInfo->Mode_Receive = 0; + + /* Baudrate */ + ConfigInfo->Baudrate = pclk / tmp2; + + /* LSB/MSB */ + if (tmp3 & UART_CTRL2_MSB) + ConfigInfo->FirstBit = 1; + else + ConfigInfo->FirstBit = 0; + + /* WordLen */ + if (tmp3 & UART_CTRL2_MODE) + ConfigInfo->WordLen = 9; + else + ConfigInfo->WordLen = 8; + + /* Parity */ + if ((tmp3 & UART_CTRL2_PMODE) == UART_CTRL2_PMODE_0) + ConfigInfo->Parity = 0; + else if ((tmp3 & UART_CTRL2_PMODE) == UART_CTRL2_PMODE_1) + ConfigInfo->Parity = 1; + else if ((tmp3 & UART_CTRL2_PMODE) == UART_CTRL2_PMODE_EVEN) + ConfigInfo->Parity = 2; + else + ConfigInfo->Parity = 3; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_version.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_version.c new file mode 100644 index 0000000000..5f24015193 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_version.c @@ -0,0 +1,25 @@ +/** +******************************************************************************* + * @file lib_version.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief Version library. +*******************************************************************************/ +#include "lib_version.h" + +#define Target_DriveVersion DRIVER_VERSION(4, 7) + +/** + * @brief Get Target driver's current version. + * @param None + * @retval Version value + * Bit[15:8] : Major version + * Bit[7:0] : Minor version + */ +uint16_t Target_GetDriveVersion(void) +{ + return (Target_DriveVersion); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_wdt.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_wdt.c new file mode 100644 index 0000000000..94d58e9034 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_wdt.c @@ -0,0 +1,88 @@ +/** + ****************************************************************************** + * @file lib_wdt.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief WDT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_wdt.h" + +#define WDTPASS_KEY 0xAA5555AA +#define WDTCLR_KEY 0x55AAAA55 + +/** + * @brief Enable WDT timer. + * @param None + * @retval None + */ +void WDT_Enable(void) +{ + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN |= PMU_WDTEN_WDTEN; + + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN |= PMU_WDTEN_WDTEN; +} + +/** + * @brief Disable WDT timer. + * @param None + * @retval None + */ +void WDT_Disable(void) +{ + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN &= ~PMU_WDTEN_WDTEN; + + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN &= ~PMU_WDTEN_WDTEN; +} + +/** + * @brief Clear WDT counter. + * @param None + * @retval None + */ +void WDT_Clear(void) +{ + PMU->WDTCLR = WDTCLR_KEY; +} + +/** + * @brief Set WDT counting period. + * @param counting period: + WDT_2_SECS + WDT_1_SECS + WDT_0_5_SECS + WDT_0_25_SECS + * @retval None + */ +void WDT_SetPeriod(uint32_t period) +{ + uint32_t tmp; + + assert_parameters(IS_WDT_PERIOD(period)); + + tmp = PMU->WDTEN; + tmp &= ~PMU_WDTEN_WDTSEL; + tmp |= period; + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN = tmp; +} + +/** + * @brief Get WDT counter value. + * @param None + * @retval current counter value. + */ +uint16_t WDT_GetCounterValue(void) +{ + return (PMU->WDTCLR & PMU_WDTCLR_WDTCNT); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/README.md b/bsp/Vango_V85xx/README.md new file mode 100644 index 0000000000..ca890ee44a --- /dev/null +++ b/bsp/Vango_V85xx/README.md @@ -0,0 +1,72 @@ +# VANGOV85XX-EVAL + +## 简介 + +VANGOV85XX-EVAL是-杭州万高科技推出的一款基于V85XX的评估板，板载资源主要如下： + +| 硬件 | 描述 | +| --------- | ------------- | +| 芯片型号 | V8530 | +| CPU | ARM Cortex M0 | +| 主频 | 26M | +| 片内SRAM | 32K | +| 片内FLASH | 256K | + +## 编译说明 + +VANGOV85XX-EVAL板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | ---------------------------- | +| GCC |gcc version 6.2.1 20161205 (release) | + +## 烧写及执行 + +供电方式：开发板使用 USB TypeA 接口或者 DC-005 连接器提供 5V 电源。 + +下载程序：下载程序到开发板需要一套 JLink 或者使用 SD612 工具。 + +串口连接：使用串口线连接到COM1(UART0)，或者使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)。 + +### 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Jan 4 2021 + 2006 - 2021 Copyright by rt-thread team +msh /> +``` +## 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| --------- | -------- | :------------------------: | +| UART | 支持 | UART0~4 | +| GPIO | 支持 | GPIOB~F | +| ADC | 未支持 | ADC0~7 | +| HWTIMER | 未支持 | TIMER0~3 | +| RTC | 未支持 | RTC | +| WDT | 未支持 | Free watchdog timer | +| IIC | 未支持 | I2C0 | +| SPI | 未支持 | SPI0~1 | +| LCD | 未支持 | | +| SDRAM | 未支持 | | +| SPI FLASH | 未支持 | | + +### IO在板级支持包中的映射情况 + +| IO号 | 板级包中的定义 | +| ---- | -------------- | +| PC0 | LED1 | +| PC2 | LED2 | +| PE0 | LED3 | +| PE1 | LED4 | +| PA0 | KEY1 | +| PC13 | KEY2 | +| PB14 | KEY3 | + +## 联系人信息 + +维护人：[idk500](https://github.com/idk500) diff --git a/bsp/Vango_V85xx/SConscript b/bsp/Vango_V85xx/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/Vango_V85xx/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/Vango_V85xx/SConstruct b/bsp/Vango_V85xx/SConstruct new file mode 100644 index 0000000000..8925090c6c --- /dev/null +++ b/bsp/Vango_V85xx/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread-VangoV85xx.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/Vango_V85xx/Target_FLASH.icf b/bsp/Vango_V85xx/Target_FLASH.icf new file mode 100644 index 0000000000..f10a7cb75e --- /dev/null +++ b/bsp/Vango_V85xx/Target_FLASH.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango_V85xx/Target_FLASH.ld b/bsp/Vango_V85xx/Target_FLASH.ld new file mode 100644 index 0000000000..5e38d5bd02 --- /dev/null +++ b/bsp/Vango_V85xx/Target_FLASH.ld @@ -0,0 +1,173 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 256KByte FLASH, 32KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-01-07 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango_V85xx/Target_FLASH.sct b/bsp/Vango_V85xx/Target_FLASH.sct new file mode 100644 index 0000000000..4e38d9b280 --- /dev/null +++ b/bsp/Vango_V85xx/Target_FLASH.sct @@ -0,0 +1,17 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00010000 { ; load region size_region + ER_IROM1 0x00000000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00002000 { ; RW data + lib_CodeRAM.o (+RO +ZI +RW) + .ANY (+RW +ZI) + } +} + diff --git a/bsp/Vango_V85xx/applications/SConscript b/bsp/Vango_V85xx/applications/SConscript new file mode 100644 index 0000000000..ca2395451a --- /dev/null +++ b/bsp/Vango_V85xx/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/Vango_V85xx/applications/main.c b/bsp/Vango_V85xx/applications/main.c new file mode 100644 index 0000000000..26035bde9d --- /dev/null +++ b/bsp/Vango_V85xx/applications/main.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + */ + +#include +#include +#include +#include +#include +#include "board.h" + +#define LED1 GET_PIN(C, 0) + +int main(void) +{ + rt_pin_mode(LED1, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED1, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED1, PIN_LOW); + rt_thread_mdelay(500); + } + + return 0; +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif \ No newline at end of file diff --git a/bsp/Vango_V85xx/drivers/SConscript b/bsp/Vango_V85xx/drivers/SConscript new file mode 100644 index 0000000000..30a1a338d0 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/SConscript @@ -0,0 +1,35 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'drivers') + +# add the general drivers. +src = Split(""" +board.c +""") + +CPPPATH = [cwd] + +# add uart drivers. +if GetDepend('RT_USING_SERIAL'): + src += ['drv_usart.c'] + +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +if GetDepend('RT_USING_ADC'): + src += ['drv_adc.c'] + +if GetDepend('RT_USING_HWTIMER'): + src += ['drv_hwtimer.c'] + +if GetDepend('RT_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('RT_USING_WDT'): + src += ['drv_iwdt.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/Vango_V85xx/drivers/board.c b/bsp/Vango_V85xx/drivers/board.c new file mode 100644 index 0000000000..5175269820 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/board.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + */ + +#include +#include +#include + +#include +#include +#include + +/* + * System Clock Configuration + */ +void SystemClock_Config(void) +{ +// SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(SysTick_IRQn, 0); + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/* + * This is the timer interrupt service routine. + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial V85xx board. + */ +void rt_hw_board_init() +{ + SystemClock_Config(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef BSP_USING_SDRAM + rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END); +#else + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +} + +/*@}*/ diff --git a/bsp/Vango_V85xx/drivers/board.h b/bsp/Vango_V85xx/drivers/board.h new file mode 100644 index 0000000000..b945ad59ef --- /dev/null +++ b/bsp/Vango_V85xx/drivers/board.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#include "drv_gpio.h" + +#define V85XX_SRAM_SIZE 48 +#define V85XX_SRAM_END (0x20000000 + V85XX_SRAM_SIZE * 1024) + +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) + +#define HEAP_END V85XX_SRAM_END + +#endif diff --git a/bsp/Vango_V85xx/drivers/drv_comm.h b/bsp/Vango_V85xx/drivers/drv_comm.h new file mode 100644 index 0000000000..5aef53cce2 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_comm.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-28 iysheng first version + */ + +#ifndef __DRV_COMM_H__ +#define __DRV_COMM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_HWTIMER_H__ */ + diff --git a/bsp/Vango_V85xx/drivers/drv_gpio.c b/bsp/Vango_V85xx/drivers/drv_gpio.c new file mode 100644 index 0000000000..8250a11bab --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_gpio.c @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-27 iysheng first version + * 2021-01-01 iysheng support exti interrupt + * 2021-09-07 FuC Suit for Vango V85xx + */ + +#include +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +#if defined(GPIOG) +#define __GD32_PORT_MAX 7u +#elif defined(GPIOF) +#define __GD32_PORT_MAX 6u +#elif defined(GPIOE) +#define __GD32_PORT_MAX 5u +#elif defined(GPIOD) +#define __GD32_PORT_MAX 4u +#elif defined(GPIOC) +#define __GD32_PORT_MAX 3u +#elif defined(GPIOB) +#define __GD32_PORT_MAX 2u +#elif defined(GPIOA) +#define __GD32_PORT_MAX 1u +#else +#define __GD32_PORT_MAX 0u +#error Unsupported GD32 GPIO peripheral. +#endif + +#define PIN_GDPORT_MAX __GD32_PORT_MAX + +// static const struct pin_irq_map pin_irq_map[] = +// { +// #if defined(SOC_SERIES_GD32F1) +// {GPIO_Pin_0, EXTI0_IRQn}, +// {GPIO_Pin_1, EXTI1_IRQn}, +// {GPIO_Pin_2, EXTI2_IRQn}, +// {GPIO_Pin_3, EXTI3_IRQn}, +// {GPIO_Pin_4, EXTI4_IRQn}, +// {GPIO_Pin_5, EXTI9_5_IRQn}, +// {GPIO_Pin_6, EXTI9_5_IRQn}, +// {GPIO_Pin_7, EXTI9_5_IRQn}, +// {GPIO_Pin_8, EXTI9_5_IRQn}, +// {GPIO_Pin_9, EXTI9_5_IRQn}, +// {GPIO_Pin_10, EXTI15_10_IRQn}, +// {GPIO_Pin_11, EXTI15_10_IRQn}, +// {GPIO_Pin_12, EXTI15_10_IRQn}, +// {GPIO_Pin_13, EXTI15_10_IRQn}, +// {GPIO_Pin_14, EXTI15_10_IRQn}, +// {GPIO_Pin_15, EXTI15_10_IRQn}, +// #else +// #error "Unsupported soc series" +// #endif +// }; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static rt_base_t v85xx_pin_get(const char *name) +{ + rt_base_t pin = 0; + int hw_port_num, hw_pin_num = 0; + int i, name_len; + + name_len = rt_strlen(name); + + if ((name_len < 4) || (name_len >= 6)) + { + return -RT_EINVAL; + } + if ((name[0] != 'P') || (name[2] != '.')) + { + return -RT_EINVAL; + } + + if ((name[1] >= 'A') && (name[1] <= 'Z')) + { + hw_port_num = (int)(name[1] - 'A'); + } + else + { + return -RT_EINVAL; + } + + for (i = 3; i < name_len; i++) + { + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; + } + + pin = PIN_NUM(hw_port_num, hw_pin_num); + + return pin; +} + +static void v85xx_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; + + if (PIN_PORT(pin) < PIN_GDPORT_MAX) + { + gpio_port = PIN_GDPORT(pin); + gpio_pin = PIN_GDPIN(pin); + + GPIOBToF_WriteBit(gpio_port, gpio_pin, (BitState)value);//GPIOA ignored + } +} + +static int v85xx_pin_read(rt_device_t dev, rt_base_t pin) +{ + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; + int value = PIN_LOW; + + if (PIN_PORT(pin) < PIN_GDPORT_MAX) + { + gpio_port = PIN_GDPORT(pin); + gpio_pin = PIN_GDPIN(pin); + value = GPIOBToF_ReadInputDataBit(gpio_port, gpio_pin);//GPIOA ignored + } + + return value; +} + +static void v85xx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + GPIO_InitType GPIO_InitStruct = {0}; + + if (PIN_PORT(pin) >= PIN_GDPORT_MAX) + { + return; + } + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin); + // GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_2MHZ; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT; + + switch (mode) + { + case PIN_MODE_OUTPUT: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUTPUT_CMOS; + break; + case PIN_MODE_INPUT: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT; + break; + case PIN_MODE_INPUT_PULLUP: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INOUT_CMOS; + break; + case PIN_MODE_INPUT_PULLDOWN: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INOUT_OD; + break; + case PIN_MODE_OUTPUT_OD: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INOUT_OD; + break; + default: + break; + } + + GPIOBToF_Init(PIN_GDPORT(pin), &GPIO_InitStruct);//ignore GPIOA +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +const static struct rt_pin_ops _v85xx_pin_ops = +{ + v85xx_pin_mode, + v85xx_pin_write, + v85xx_pin_read, + v85xx_pin_get, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +// /** +// * @brief This function handles EXTI interrupt request. +// * @param gpio_pin: Specifies the pins connected EXTI line +// * @retval none +// */ +// void v85xx_pin_exti_irqhandler(uint16_t gpio_pin) +// { +// if (SET == EXTI_GetIntBitState(gpio_pin)) +// { +// EXTI_ClearIntBitState(gpio_pin); +// pin_irq_hdr(bit2bitno(gpio_pin)); +// } +// } + +// void EXTI0_IRQHandler(void) +// { +// rt_interrupt_enter(); +// v85xx_pin_exti_irqhandler(GPIO_Pin_0); +// rt_interrupt_leave(); +// } + +// void EXTI1_IRQHandler(void) +// { +// rt_interrupt_enter(); +// v85xx_pin_exti_irqhandler(GPIO_Pin_1); +// rt_interrupt_leave(); +// } + +// void EXTI2_IRQHandler(void) +// { +// rt_interrupt_enter(); +// v85xx_pin_exti_irqhandler(GPIO_Pin_2); +// rt_interrupt_leave(); +// } + +// void EXTI3_IRQHandler(void) +// { +// rt_interrupt_enter(); +// v85xx_pin_exti_irqhandler(GPIO_Pin_3); +// rt_interrupt_leave(); +// } + +// void EXTI4_IRQHandler(void) +// { +// rt_interrupt_enter(); +// v85xx_pin_exti_irqhandler(GPIO_Pin_4); +// rt_interrupt_leave(); +// } + +// void EXTI5_9_IRQHandler(void) +// { +// rt_interrupt_enter(); +// v85xx_pin_exti_irqhandler(GPIO_Pin_5); +// v85xx_pin_exti_irqhandler(GPIO_Pin_6); +// v85xx_pin_exti_irqhandler(GPIO_Pin_7); +// v85xx_pin_exti_irqhandler(GPIO_Pin_8); +// v85xx_pin_exti_irqhandler(GPIO_Pin_9); +// rt_interrupt_leave(); +// } + +// void EXTI10_15_IRQHandler(void) +// { +// rt_interrupt_enter(); +// v85xx_pin_exti_irqhandler(GPIO_Pin_10); +// v85xx_pin_exti_irqhandler(GPIO_Pin_11); +// v85xx_pin_exti_irqhandler(GPIO_Pin_12); +// v85xx_pin_exti_irqhandler(GPIO_Pin_13); +// v85xx_pin_exti_irqhandler(GPIO_Pin_14); +// v85xx_pin_exti_irqhandler(GPIO_Pin_15); +// rt_interrupt_leave(); +// } + +int rt_hw_pin_init(void) +{ + GPIO_InitType GPIO_InitStruct; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_All; +#if defined(GPIOG) + GPIOBToF_Init(GPIOG, &GPIO_InitStruct); +#endif +#if defined(GPIOF) + GPIOBToF_Init(GPIOF, &GPIO_InitStruct); +#endif +#if defined(GPIOE) + GPIOBToF_Init(GPIOE, &GPIO_InitStruct); +#endif +#if defined(GPIOD) + GPIOBToF_Init(GPIOD, &GPIO_InitStruct); +#endif +#if defined(GPIOC) + GPIOBToF_Init(GPIOC, &GPIO_InitStruct); +#endif +#if defined(GPIOB) + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); +#endif +#if defined(GPIOA) + GPIOA_Init(GPIOA, &GPIO_InitStruct); +#endif + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + return rt_device_pin_register("pin", &_v85xx_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); +#endif /* RT_USING_PIN */ + diff --git a/bsp/Vango_V85xx/drivers/drv_gpio.h b/bsp/Vango_V85xx/drivers/drv_gpio.h new file mode 100644 index 0000000000..e11595e129 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_gpio.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-27 iysheng first release + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __V85XX_PORT(port) GPIO##port##_BASE + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__V85XX_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) + +#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) + +#define PIN_GDPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) +#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/Vango_V85xx/drivers/drv_usart.c b/bsp/Vango_V85xx/drivers/drv_usart.c new file mode 100644 index 0000000000..026151c446 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_usart.c @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + */ + +#include +#include +#include + +#ifdef RT_USING_SERIAL + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \ + !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) + #error "Please define at least one UARTx" + +#endif + +#include + +static void uart_isr(struct rt_serial_device *serial); + +#if defined(BSP_USING_UART0) +struct rt_serial_device serial0; + +void UART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial0); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +struct rt_serial_device serial1; + +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +struct rt_serial_device serial2; + +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial2); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +struct rt_serial_device serial3; + +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial3); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +struct rt_serial_device serial4; + +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial4); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +static const struct V85xx_uart uarts[] = { +#ifdef BSP_USING_UART0 + { + UART0, /* uart peripheral index */ + UART0_IRQn, /* uart iqrn */ + // // RCU_UART0, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + // GPIOA, GPIOA, /* tx port, tx alternate, tx pin */ + // GPIO_PIN_9, GPIO_PIN_10, /* rx port, rx alternate, rx pin */ + &serial0, + "uart0", + }, +#endif + +#ifdef BSP_USING_UART1 + { + UART1, /* uart peripheral index */ + UART1_IRQn, /* uart iqrn */ + // RCU_UART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + // GPIOA, GPIOA, /* tx port, tx alternate, tx pin */ + // GPIO_PIN_2, GPIO_PIN_3, /* rx port, rx alternate, rx pin */ + &serial1, + "uart1", + }, +#endif + +#ifdef BSP_USING_UART2 + { + UART2, /* uart peripheral index */ + UART2_IRQn, /* uart iqrn */ + // RCU_UART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */ + // GPIOB, GPIOB, /* tx port, tx alternate, tx pin */ + // GPIO_PIN_10, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ + &serial2, + "uart2", + }, +#endif + +#ifdef BSP_USING_UART3 + { + UART3, /* uart peripheral index */ + UART3_IRQn, /* uart iqrn */ + // RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ + // GPIOC, GPIOC, /* tx port, tx alternate, tx pin */ + // GPIO_PIN_10, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ + &serial3, + "uart3", + }, +#endif + +#ifdef BSP_USING_UART4 + { + UART4, /* uart peripheral index */ + UART4_IRQn, /* uart iqrn */ + // RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */ + // GPIOC, GPIOD, /* tx port, tx alternate, tx pin */ + // GPIO_PIN_12, GPIO_PIN_2, /* rx port, rx alternate, rx pin */ + &serial4, + "uart4", + }, +#endif +}; + +static rt_err_t V85xx_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct V85xx_uart *uart; + UART_TypeDef *UARTx; + UART_InitType UART_InitParaStruct = {0}; + + UART_StructInit(&UART_InitParaStruct); + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = (struct V85xx_uart *)serial->parent.user_data; + + UARTx = (UART_TypeDef *)uart->uart_periph; + UART_InitParaStruct.Baudrate = cfg->baud_rate; + + switch (cfg->data_bits) { + case DATA_BITS_9: + UART_InitParaStruct.WordLen = UART_WORDLEN_9B; + break; + + default: + UART_InitParaStruct.WordLen = UART_WORDLEN_8B; + break; + } + + // switch (cfg->stop_bits) { + // case STOP_BITS_2: + // UART_InitParaStruct.UART_STBits = UART_STBITS_2; + // break; + // default: + // UART_InitParaStruct.UART_STBits = UART_STBITS_1; + // break; + // } + + switch (cfg->parity) { + case PARITY_ODD: + UART_InitParaStruct.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + UART_InitParaStruct.Parity = UART_PARITY_EVEN; + break; + default: + UART_InitParaStruct.Parity = UART_PARITY_NONE; + break; + } + + // UART_InitParaStruct.UART_HardwareFlowControl = UART_HARDWAREFLOWCONTROL_NONE; + UART_InitParaStruct.Mode = UART_MODE_RX | UART_MODE_TX; + UART_Init(UARTx, &UART_InitParaStruct); + UART_Cmd(UARTx, UART_InitParaStruct.Mode, ENABLE); + + return RT_EOK; +} + +static rt_err_t V85xx_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct V85xx_uart *uart; + UART_TypeDef *UARTx; + + RT_ASSERT(serial != RT_NULL); + uart = (struct V85xx_uart *)serial->parent.user_data; + UARTx = (UART_TypeDef *)uart->uart_periph; + + switch (cmd) { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irqn); + /* disable interrupt */ + UART_INTConfig(UARTx, UART_INT_RXPE, DISABLE); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irqn); + /* enable interrupt */ + UART_INTConfig(UARTx, UART_INT_RXPE, ENABLE); + break; + } + + return RT_EOK; +} + +static int V85xx_putc(struct rt_serial_device *serial, char ch) +{ + struct V85xx_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct V85xx_uart *)serial->parent.user_data; + + + UART_SendData((UART_TypeDef *)uart->uart_periph, ch); + while ((UART_GetFlag(uart->uart_periph, UART_FLAG_TXDONE) == RESET)); + + return 1; +} + +static int V85xx_getc(struct rt_serial_device *serial) +{ + int ch; + struct V85xx_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct V85xx_uart *)serial->parent.user_data; + + ch = -1; + if (UART_GetFlag(uart->uart_periph, UART_FLAG_RXFULL) != RESET) + ch = UART_ReceiveData(uart->uart_periph); + return ch; +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct V85xx_uart *uart = (struct V85xx_uart *) serial->parent.user_data; + + RT_ASSERT(uart != RT_NULL); + + if ((UART_GetINTStatus((UART_TypeDef *)uart->uart_periph, UART_INTSTS_RX) != RESET) && + (UART_GetFlag((UART_TypeDef *)uart->uart_periph, UART_FLAG_RXPE) != RESET)) { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + /* Clear RXNE interrupt flag */ + UART_ClearINTStatus(uart->uart_periph, UART_INTSTS_RX); + } +} + +static const struct rt_uart_ops V85xx_uart_ops = { + V85xx_configure, + V85xx_control, + V85xx_putc, + V85xx_getc, +}; + +int V85xx_hw_usart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + int i; + + + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { + uarts[i].serial->ops = &V85xx_uart_ops; + uarts[i].serial->config = config; + + /* register UART device */ + rt_hw_serial_register(uarts[i].serial, + uarts[i].device_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + (void *)&uarts[i]); + } + + return 0; +} +INIT_BOARD_EXPORT(V85xx_hw_usart_init); +#endif diff --git a/bsp/Vango_V85xx/drivers/drv_usart.h b/bsp/Vango_V85xx/drivers/drv_usart.h new file mode 100644 index 0000000000..c558ac7d6f --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_usart.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + */ + +#ifndef __USART_H__ +#define __USART_H__ + +#include +#include + +/* GD32 uart driver */ +struct V85xx_uart { + UART_TypeDef * uart_periph; + IRQn_Type irqn; + // rcu_periph_enum per_clk; + // rcu_periph_enum tx_gpio_clk; + // rcu_periph_enum rx_gpio_clk; + // GPIO_TypeDef * tx_port; + // GPIO_TypeDef * rx_port; + // uint16_t tx_pin; + // uint16_t rx_pin; + + struct rt_serial_device *serial; + char *device_name; +}; + +#endif diff --git a/bsp/Vango_V85xx/rtconfig.h b/bsp/Vango_V85xx/rtconfig.h new file mode 100644 index 0000000000..266486186f --- /dev/null +++ b/bsp/Vango_V85xx/rtconfig.h @@ -0,0 +1,182 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_SERIES_GD32F1 +#define SOC_GD32103C + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART2 + +#endif diff --git a/bsp/Vango_V85xx/rtconfig.py b/bsp/Vango_V85xx/rtconfig.py new file mode 100644 index 0000000000..8302af0cf5 --- /dev/null +++ b/bsp/Vango_V85xx/rtconfig.py @@ -0,0 +1,126 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # tool-chains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-v85xx.map,-cref,-u,Reset_Handler -T Target_FLASH.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-v85xx.map --scatter Target_FLASH.sct' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + EXEC_PATH += '/ARM/ARMCC/bin' + print(EXEC_PATH) + + CFLAGS += ' --c99' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D VANGOV85XXDEV' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config Target_FLASH.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH += '/arm/bin/' + POST_ACTION = '' + -- GitLab