- 04 10月, 2019 1 次提交
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由 Chris Mason 提交于
STM32F0 has PCLK=48MHz and maximum ADC clock is 14MHz so use PCLK/4=12MHz to stay within spec of the ADC peripheral. In pyb.ADC set common sampling time to approx 4uS for internal and external sources. In machine.ADC reduce sample time to approx 1uS for external source, leave internal at maximum sampling time.
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- 12 9月, 2019 1 次提交
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由 Damien George 提交于
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- 06 9月, 2019 1 次提交
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由 Damien George 提交于
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- 04 9月, 2019 1 次提交
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由 Damien George 提交于
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