Merge pull request #926 from SummerGGift/master_20171031

[BSP] add iar template for 429bsp

bsp/stm32f429-apollo/.config

@@ -2,6 +2,7 @@
 # Automatically generated file; DO NOT EDIT.
 # RT-Thread Configuration
 #
+CONFIG_BOARD_STM32F429_APPOLO=y
 
 #
 # RT-Thread Kernel
@@ -45,6 +46,9 @@ CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
 # CONFIG_RT_USING_MODULE is not set
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M4=y
 
 #
 # RT-Thread Components
@@ -78,6 +82,10 @@ CONFIG_DFS_USING_WORKDIR=y
 CONFIG_DFS_FILESYSTEMS_MAX=2
 CONFIG_DFS_FD_MAX=4
 CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
 CONFIG_RT_DFS_ELM_CODE_PAGE=437
 CONFIG_RT_DFS_ELM_WORD_ACCESS=y
 CONFIG_RT_DFS_ELM_USE_LFN_0=y
@@ -92,6 +100,9 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
 CONFIG_RT_DFS_ELM_REENTRANT=y
 CONFIG_RT_USING_DFS_DEVFS=y
 CONFIG_RT_USING_DFS_NET=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
 # CONFIG_RT_USING_DFS_NFS is not set
 
 #
@@ -198,6 +209,11 @@ CONFIG_LWIP_SO_RCVBUF=1
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_EZXML is not set
 
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_MARVELLWIFI is not set
+
 #
 # security packages
 #
@@ -222,13 +238,9 @@ CONFIG_LWIP_SO_RCVBUF=1
 # miscellaneous packages
 #
 # CONFIG_PKG_USING_HELLO is not set
-
-#
-# BSP_SPECIAL CONFIG
-#
-CONFIG_RT_RTC_NAME="rtc"
 CONFIG_RT_USING_EXT_SDRAM=y
 CONFIG_RT_USING_UART1=y
 CONFIG_RT_USING_UART2=y
 CONFIG_RT_USING_UART3=y
 CONFIG_RT_USING_SPI5=y
+CONFIG_RT_RTC_NAME="rtc"

bsp/stm32f429-apollo/drivers/drv_mpu.c

@@ -20,7 +20,7 @@
 
 
 
-void mpu_init(void)
+int mpu_init(void)
 {
     /* Disable MPU */
     MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
@@ -32,7 +32,7 @@ void mpu_init(void)
     MPU->RNR = 0;//indicate MPU region 0
     MPU->RBAR = 0x00000000; // update the base address for the region 0
     MPU->RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)     //full access
-                | MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_1MB)   //512Kb size
+                | MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_1MB)     //512Kb size
                 | MPU_REGION_ENABLE;                            //region enable
 
     /* - Region 1:0x20000000 - 0x20007FFF --- on chip SRAM
@@ -92,5 +92,7 @@ void mpu_init(void)
 
     /* Enable MPU */
     MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
+	
+	return 0;
 }
 INIT_BOARD_EXPORT(mpu_init);

bsp/stm32f429-apollo/drivers/drv_mpu.h

@@ -2,7 +2,7 @@
 #define __DRV_MPU_H
 
 /* Initialize Cortex M4 MPU */
-void mpu_init(void);
+int mpu_init(void);
 void mpu_enable(int enable);
 
 #endif

bsp/stm32f429-apollo/project.eww

+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/stm32f429-apollo/rtconfig.h

@@ -4,6 +4,8 @@
 /* Automatically generated file; DO NOT EDIT. */
 /* RT-Thread Configuration */
 
+#define BOARD_STM32F429_APPOLO
+
 /* RT-Thread Kernel */
 
 #define RT_NAME_MAX 8
@@ -42,6 +44,9 @@
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart"
 /* RT_USING_MODULE is not set */
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M4
 
 /* RT-Thread Components */
 
@@ -186,6 +191,10 @@
 /* PKG_USING_CJSON is not set */
 /* PKG_USING_EZXML is not set */
 
+/* Marvell WiFi */
+
+/* PKG_USING_MARVELLWIFI is not set */
+
 /* security packages */
 
 /* PKG_USING_MBEDTLS is not set */

bsp/stm32f429-apollo/stm32f429_flash.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__   = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly, block RTT_INIT_FUNC };
+place in RAM_region   { readwrite, block CSTACK, last block HEAP};