- 02 7月, 2010 1 次提交
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由 Catalin Marinas 提交于
RealView boards with certain revisions of the L210/L220 cache controller may have issues (hardware deadlock) with the mandatory barriers (DSB followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled. The patch disables ARM_DMA_MEM_BUFFERABLE for these boards. Tested-by: NLinus Walleij <linus.walleij@stericsson.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 01 7月, 2010 1 次提交
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由 Catalin Marinas 提交于
Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 17 5月, 2010 1 次提交
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由 Russell King 提交于
Provide a configuration option to allow the ARMv6 to use normal bufferable memory for coherent DMA. This option is forced to 'y' for ARMv7, and offered as a configuration option on ARMv6. Enabling this option requires drivers to have the necessary barriers to ensure that data in DMA coherent memory is visible prior to the DMA operation commencing. Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 11 5月, 2010 1 次提交
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由 Haojian Zhuang 提交于
Enable Tauros2 L2 in mmp2. Tauros2 L2 is shared in Marvell ARM cores. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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- 04 5月, 2010 1 次提交
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由 Dave Estes 提交于
Handle incorrectly reported permission faults for qsd8650. On permission faults, retry MVA to PA conversion. If retry detects translation fault. Report as translation fault. Cc: Jamie Lokier <jamie@shareable.org> Signed-off-by: NDave Estes <cestes@quicinc.com>
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- 02 5月, 2010 1 次提交
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由 Russell King 提交于
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 14 4月, 2010 1 次提交
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由 Srinidhi Kasagar 提交于
This enables the l2x0 support and ensures that the secondary CPU can see the page table and secondary data at this point. Signed-off-by: Nsrinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: NLinus Walleij <linus.walleij@stericsson.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 26 3月, 2010 3 次提交
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由 Catalin Marinas 提交于
The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor systems for things like ordering Normal Non-cacheable memory accesses with DMA transfer (via Device memory writes). The current implementation uses dmb() for mb() and friends but this is not sufficient. The DMB only ensures the relative ordering of the observability of accesses by other processors or devices acting as masters. In case of DMA transfers started by writes to device memory, the relative ordering is not ensured because accesses to slave ports of a device are not considered observable by the DMB definition. A DSB is required for the data to reach the main memory (even if mapped as Normal Non-cacheable) before the device receives the notification to begin the transfer. Furthermore, some L2 cache controllers (like L2x0 or PL310) buffer stores to Normal Non-cacheable memory and this would need to be drained with the outer_sync() function call. The patch also allows platforms to define their own mandatory barriers implementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a mach/barriers.h file. Note that the SMP barriers are unchanged (being DMBs as before) since they are only guaranteed to work with Normal Cacheable memory. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
The L2x0 cache controllers need to explicitly drain their write buffer even for Normal Noncacheable memory accesses. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
This patch introduces the outer_cache_fns.sync function pointer together with the OUTER_CACHE_SYNC config option that can be used to drain the write buffer of the outer cache. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 25 2月, 2010 1 次提交
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由 Kukjin Kim 提交于
Add ARM_L1_CACHE_SHIFT_6 to arch/arm/Kconfig to allow CPUs with L1 cache lines which are 64bytes to indicate this without having to alter the arch/arm/mm/Kconfig entry each time. Update the mm Kconfig so that ARM_L1_CACHE_SHIFT default value uses this and change OMAP3 and S5PC1XX to select ARM_L1_CACHE_SHIFT_6. Acked-by: NBen Dooks <ben-linux@fluff.org> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 16 2月, 2010 2 次提交
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由 Santosh Shilimkar 提交于
This patch adds L2 Cache support for OMAP4. External L2 cache is used in OMAP4 CC: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Tony Lindgren 提交于
Otherwise the kernel built with both CPU_V6 and CPU_V7 will not boot on omap2. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 19 12月, 2009 1 次提交
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由 Russell King 提交于
26-bit ARM support was removed a long time ago, and this symbol has been defined to be 'y' ever since. As it's never disabled anymore, we can kill it without any side effects. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 28 11月, 2009 2 次提交
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由 Lennert Buytenhek 提交于
Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Signed-off-by: NSaeed Bishara <saeed@marvell.com> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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由 Saeed Bishara 提交于
The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Signed-off-by: NSaeed Bishara <saeed@marvell.com> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 24 11月, 2009 1 次提交
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由 Marek Szyprowski 提交于
Samsung S5PC1xx SoCs are based on ARM Coretex8, which has 64 bytes of L1 cache line size. Enable proper handling of L1 cache on these SoCs. Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 21 10月, 2009 1 次提交
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由 Hartley Sweeten 提交于
Remove the URL listed for Maverick EP9312 since it is not available and modify the help text appropriately. Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: NRyan Mallon <ryan@bluewatersys.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 03 10月, 2009 1 次提交
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由 Kirill A. Shutemov 提交于
Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 16 9月, 2009 1 次提交
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由 Kirill A. Shutemov 提交于
Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. It's not true at least for CPUs based on Cortex-A8. List of CPUs with cache line size != 32 should be expanded later. Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 03 7月, 2009 1 次提交
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由 Alessandro Rubini 提交于
Signed-off-by: NAlessandro Rubini <rubini@unipv.it> Acked-by: NAndrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 31 5月, 2009 1 次提交
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由 Russell King 提交于
Kconfig entries default to n, so there's no need for this to be explicitly specified. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 30 5月, 2009 2 次提交
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由 Catalin Marinas 提交于
Starting with ARMv6, the CPUs support the BE-8 variant of big-endian (byte-invariant). This patch adds the core support: - setting of the BE-8 mode via the CPSR.E register for both kernel and user threads - big-endian page table walking - REV used to rotate instructions read from memory during fault processing as they are still little-endian format - Kconfig and Makefile support for BE-8. The --be8 option must be passed to the final linking stage to convert the instructions to little-endian Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Colin Tuckley 提交于
This is a RealView platform supporting core tiles with ARM11MPCore, Cortex-A8 or Cortex-A9 (multicore) processors. It has support for MMC, CompactFlash, PCI-E. Signed-off-by: NColin Tuckley <colin.tuckley@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 25 3月, 2009 1 次提交
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由 Paulius Zaleckas 提交于
Adds support for Faraday FA526 core. This core is used at least by: Cortina Systems Gemini and Centroid family Cavium Networks ECONA family Grain Media GM8120 Pixelplus ImageARM Prolific PL-1029 Faraday IP evaluation boards v2: - move TLB_BTB to separate patch - update copyrights Signed-off-by: NPaulius Zaleckas <paulius.zaleckas@teltonika.lt>
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- 23 3月, 2009 1 次提交
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由 Eric Miao 提交于
"""The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: NJason Chagas <chagas@marvell.com> Signed-off-by: NEric Miao <eric.miao@marvell.com>
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- 13 3月, 2009 1 次提交
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由 Sascha Hauer 提交于
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 01 12月, 2008 1 次提交
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由 Jon Callan 提交于
This patch adds the necessary definitions and Kconfig entries to enable Cortex-A9 (ARMv7 SMP) tiles on the RealView/EB board. Signed-off-by: NJon Callan <Jon.Callan@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 27 11月, 2008 1 次提交
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由 Russell King 提交于
Rather than: config CPU_BLAH bool depends on ARCH_FOO || MACH_BAR default y if ARCH_FOO || MACH_BAR arrange for ARCH_FOO and MACH_BAR to select CPU_BLAH directly. Acked-by: NNicolas Pitre <nico@marvell.com> Acked-by: NAndrew Victor <linux@maxim.org.za> Acked-by: NBrian Swetland <swetland@google.com> Acked-by: NEric Miao <eric.miao@marvell.com> Acked-by: NNicolas Bellido <ml@acolin.be> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 22 10月, 2008 1 次提交
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由 Brian Swetland 提交于
The MSM architecture covers a wider family of chips than just the MSM7X00A. Move to a more generic name, in perparation for supporting the specific SoC variants as sub-architectures (ARCH_MSM7X01A, ARCH_MSM722X, etc). This gives us ARCH_MSM for the (many) common peripherals. This also removes the unused/obsolete config item MSM7X00A_IDLE. Signed-off-by: NBrian Swetland <swetland@google.com>
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- 09 10月, 2008 1 次提交
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由 Syed Mohammed, Khasim 提交于
Add minimal Beagle board support. Based on earlier patches by Syed Mohammed Khasim with some fixes from linux-omap tree. Signed-off-by: NSyed Mohammed Khasim <khasim@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 26 9月, 2008 1 次提交
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由 Ronen Shitrit 提交于
Feroceon L2 cache can work in eighther write through or write back mode on Kirkwood. Add the option to configure this mode according to Kconfig. Signed-off-by: NRonen Shitrit <rshitrit@marvell.com> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 29 7月, 2008 1 次提交
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由 Eric Miao 提交于
(20072fd0 lost most of its changes somehow, came from a mbox archive applied with git-am. No idea what happened. This puts back the missing bits. --rmk) The initial patch from Lothar, and Lennert make it into a cleaner one, modified and tested on PXA320 by Eric Miao. This patch moves the L2 cache operations out of proc-xsc3.S into dedicated outer cache support code. CACHE_XSC3L2 can be deselected so no L2 cache specific code will be linked in, and that L2 enable bit will not be set, this applies to the following cases: a. _only_ PXA300/PXA310 support included and no L2 cache wanted b. PXA320 support included, but want L2 be disabled So the enabling of L2 depends on two things: - CACHE_XSC3L2 is selected - and L2 cache is present Where the latter is only a safeguard (previous testing shows it works OK even when this bit is turned on). IXP series of processors with XScale3 cannot disable L2 cache for the moment since they depend on the L2 cache for its coherent memory, so IXP may always select CACHE_XSC3L2. Other L2 relevant bits are always turned on (i.e. the original code enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side effects. Specifically, these bits are: - OC bits in TTBASE register (table walk outer cache attributes) - LLR Outer Cache Attributes (OC) in Auxiliary Control Register Signed-off-by: NLothar WaÃ<9f>mann <LW@KARO-electronics.de> Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Signed-off-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 28 7月, 2008 1 次提交
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由 Sascha Hauer 提交于
It seems this small label was lost in the last merge. Without it no CPU type is selected for the MX2 family of processors. And a build will fail badly... Signed-off-by: NJuergen Beisert <j.beisert@pengutronix.de> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 10 7月, 2008 1 次提交
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由 sedji gaouaou 提交于
Support for the at91sam9g20 : Atmel 400Mhz ARM 926ej-s SOC. AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed. We created a new board for this device but based the chip support directly on 9260 files with little updates. Here is the chip page on Atmel wabsite: http://atmel.com/dyn/products/product_card.asp?part_id=4337Signed-off-by: NSedji Gaouaou <sedji.gaouaou@atmel.com> Signed-off-by: NJustin Waters <justin.waters@timesys.com> Acked-by: NAndrew Victor <linux@maxim.org.za> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 05 7月, 2008 1 次提交
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由 Juergen Beisert 提交于
This patch adds basic mach support for the mx2 processor family, based on the original freescale code and adapted to mainline kernel coding style. This part adds the global build only. Signed-off-by: NJuergen Beisert <j.beisert@pengutronix.de>
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- 23 6月, 2008 4 次提交
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由 Stanislav Samsonov 提交于
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring (depending on the model) one or two Feroceon CPU cores with 512K of L2 cache and VFP coprocessors running at (depending on the model) between 800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe interfaces that can each run either in x4 or quad x1 mode, three USB 2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI interface, four UARTs, and depending on the model, two or four gigabit ethernet interfaces. This patch adds basic support for the platform, and allows booting on the MV78x00 development board, with functional UARTs, SATA, PCIe, GigE and USB ports. Signed-off-by: NStanislav Samsonov <samsonov@marvell.com> Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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由 Saeed Bishara 提交于
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: NSaeed Bishara <saeed@marvell.com> Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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由 Lennert Buytenhek 提交于
This patch adds support for the unified Feroceon L2 cache controller as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo families of ARM SoCs. Note that: - Page table walks are outer uncacheable on Kirkwood and Discovery Duo, since the ARMv5 spec provides no way to indicate outer cacheability of page table walks (specifying it in TTBR[4:3] is an ARMv6+ feature). This requires adding L2 cache clean instructions to proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled by defining a new TLB type (TLB_FEROCEON) which is almost identical to the v4wbi one but provides a TLB_L2CLEAN_FR flag. - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2 range by MVA' and 'invalidate L2 range by MVA') operations, and this patch uses those range operations for all Linux outer cache operations, as they are faster than the regular per-line operations. L2 range operations are not interruptible on this hardware, which avoids potential livelock issues, but can be bad for interrupt latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which allows you to select the maximum range size to operate on at once. (Valid range is between one cache line and one 4KiB page, and must be a multiple of the line size.) Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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由 Lennert Buytenhek 提交于
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU core running at between 400 MHz and 1.0 GHz, and features a 64 bit DDR controller, 512K of internal SRAM, two x4 PCI-Express ports, two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs, two TWSI controllers, and IDMA/XOR engines. This patch adds support for the Marvell LB88RC8480 Development Board, enabling the use of the PCIe interfaces, the ethernet interfaces, the TWSI interfaces and the UARTs. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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