- 09 10月, 2008 1 次提交
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由 Syed Mohammed, Khasim 提交于
Add minimal Beagle board support. Based on earlier patches by Syed Mohammed Khasim with some fixes from linux-omap tree. Signed-off-by: NSyed Mohammed Khasim <khasim@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 29 7月, 2008 1 次提交
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由 Eric Miao 提交于
(20072fd0 lost most of its changes somehow, came from a mbox archive applied with git-am. No idea what happened. This puts back the missing bits. --rmk) The initial patch from Lothar, and Lennert make it into a cleaner one, modified and tested on PXA320 by Eric Miao. This patch moves the L2 cache operations out of proc-xsc3.S into dedicated outer cache support code. CACHE_XSC3L2 can be deselected so no L2 cache specific code will be linked in, and that L2 enable bit will not be set, this applies to the following cases: a. _only_ PXA300/PXA310 support included and no L2 cache wanted b. PXA320 support included, but want L2 be disabled So the enabling of L2 depends on two things: - CACHE_XSC3L2 is selected - and L2 cache is present Where the latter is only a safeguard (previous testing shows it works OK even when this bit is turned on). IXP series of processors with XScale3 cannot disable L2 cache for the moment since they depend on the L2 cache for its coherent memory, so IXP may always select CACHE_XSC3L2. Other L2 relevant bits are always turned on (i.e. the original code enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side effects. Specifically, these bits are: - OC bits in TTBASE register (table walk outer cache attributes) - LLR Outer Cache Attributes (OC) in Auxiliary Control Register Signed-off-by: NLothar WaÃ<9f>mann <LW@KARO-electronics.de> Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Signed-off-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 28 7月, 2008 1 次提交
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由 Sascha Hauer 提交于
It seems this small label was lost in the last merge. Without it no CPU type is selected for the MX2 family of processors. And a build will fail badly... Signed-off-by: NJuergen Beisert <j.beisert@pengutronix.de> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 10 7月, 2008 1 次提交
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由 sedji gaouaou 提交于
Support for the at91sam9g20 : Atmel 400Mhz ARM 926ej-s SOC. AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed. We created a new board for this device but based the chip support directly on 9260 files with little updates. Here is the chip page on Atmel wabsite: http://atmel.com/dyn/products/product_card.asp?part_id=4337Signed-off-by: NSedji Gaouaou <sedji.gaouaou@atmel.com> Signed-off-by: NJustin Waters <justin.waters@timesys.com> Acked-by: NAndrew Victor <linux@maxim.org.za> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 05 7月, 2008 1 次提交
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由 Juergen Beisert 提交于
This patch adds basic mach support for the mx2 processor family, based on the original freescale code and adapted to mainline kernel coding style. This part adds the global build only. Signed-off-by: NJuergen Beisert <j.beisert@pengutronix.de>
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- 23 6月, 2008 4 次提交
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由 Stanislav Samsonov 提交于
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring (depending on the model) one or two Feroceon CPU cores with 512K of L2 cache and VFP coprocessors running at (depending on the model) between 800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe interfaces that can each run either in x4 or quad x1 mode, three USB 2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI interface, four UARTs, and depending on the model, two or four gigabit ethernet interfaces. This patch adds basic support for the platform, and allows booting on the MV78x00 development board, with functional UARTs, SATA, PCIe, GigE and USB ports. Signed-off-by: NStanislav Samsonov <samsonov@marvell.com> Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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由 Saeed Bishara 提交于
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: NSaeed Bishara <saeed@marvell.com> Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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由 Lennert Buytenhek 提交于
This patch adds support for the unified Feroceon L2 cache controller as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo families of ARM SoCs. Note that: - Page table walks are outer uncacheable on Kirkwood and Discovery Duo, since the ARMv5 spec provides no way to indicate outer cacheability of page table walks (specifying it in TTBR[4:3] is an ARMv6+ feature). This requires adding L2 cache clean instructions to proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled by defining a new TLB type (TLB_FEROCEON) which is almost identical to the v4wbi one but provides a TLB_L2CLEAN_FR flag. - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2 range by MVA' and 'invalidate L2 range by MVA') operations, and this patch uses those range operations for all Linux outer cache operations, as they are faster than the regular per-line operations. L2 range operations are not interruptible on this hardware, which avoids potential livelock issues, but can be bad for interrupt latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which allows you to select the maximum range size to operate on at once. (Valid range is between one cache line and one 4KiB page, and must be a multiple of the line size.) Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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由 Lennert Buytenhek 提交于
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU core running at between 400 MHz and 1.0 GHz, and features a 64 bit DDR controller, 512K of internal SRAM, two x4 PCI-Express ports, two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs, two TWSI controllers, and IDMA/XOR engines. This patch adds support for the Marvell LB88RC8480 Development Board, enabling the use of the PCIe interfaces, the ethernet interfaces, the TWSI interfaces and the UARTs. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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- 29 4月, 2008 2 次提交
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由 Lennert Buytenhek 提交于
This patch implements a set of Feroceon-specific {copy,clear}_user_page() routines that perform more optimally than the generic implementations. This also deals with write-allocate caches (Feroceon can run L1 D in WA mode) which otherwise prevents Linux from booting. [nico: optimized the code even further] Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Tested-by: NSylver Bruneau <sylver.bruneau@googlemail.com> Tested-by: NMartin Michlmayr <tbm@cyrius.com> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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由 Lennert Buytenhek 提交于
Since the Feroceon doesn't have a global WT override bit like ARM926 does, remove all code relating to this mode of operation from proc-feroceon.S. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 24 4月, 2008 1 次提交
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由 Catalin Marinas 提交于
The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 19 4月, 2008 6 次提交
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由 Catalin Marinas 提交于
By default, this option was selected by the platform Kconfig. This patch adds "depends on" to L2X0 so that it can be enabled/disabled manually. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Bahadir Balban 提交于
This patch enables the building of Linux for the PB1176 platform. Signed-off-by: NBahadir Balban <bahadir.balban@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Bahadir Balban 提交于
This patch adds the PB11MPCore support to the corresponding Kconfig and Makefile to enable building. Signed-off-by: NBahadir Balban <bahadir.balban@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
This patch changes the CPU_V7 configuration dependency to allow MACH_REALVIEW_EB. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Paul Brook 提交于
This patch adds a prefetch abort handler similar to the data abort one and renames the latter for consistency. Initial implementation by Paul Brook with some renaming by Catalin Marinas. Signed-off-by: NPaul Brook <paul@codesourcery.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
This patch adds the detection and handling of the ThumbEE extension on ARMv7 CPUs. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 28 3月, 2008 1 次提交
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由 Lennert Buytenhek 提交于
Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e. not the plat-orion bits.) Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Reviewed-by: NTzachi Perelstein <tzachi@marvell.com> Acked-by: NSaeed Bishara <saeed@marvell.com> Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 26 1月, 2008 4 次提交
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由 Tzachi Perelstein 提交于
This enables the usage of some old Feroceon cores for which the CPU ID is equal to the ARM926 ID. Relevant for Feroceon-1850 and old Feroceon-2850. Signed-off-by: NTzachi Perelstein <tzachi@marvell.com> Signed-off-by: NNicolas Pitre <nico@marvell.com> Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Assaf Hoffman 提交于
The Feroceon is a family of independent ARMv5TE compliant CPU core implementations, supporting a variable depth pipeline and out-of-order execution. The Feroceon is configurable with VFP support, and the later models in the series are superscalar with up to two instructions per clock cycle. This patch adds the initial low-level cache/TLB handling for this core. Signed-off-by: NAssaf Hoffman <hoffman@marvell.com> Reviewed-by: NTzachi Perelstein <tzachi@marvell.com> Reviewed-by: NNicolas Pitre <nico@marvell.com> Reviewed-by: NLennert Buytenhek <buytenh@marvell.com> Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Andrew Victor 提交于
Add support for Atmel's AT91CAP9 Customizable Microcontroller family. <http://www.atmel.com/products/AT91CAP/Default.asp> Signed-off-by: NStelian Pop <stelian@popies.net> Signed-off-by: NAndrew Victor <linux@maxim.org.za> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Brian Swetland 提交于
- core header files for arch-msm - Kconfig and Makefiles to enable ARCH_MSM7X00A builds - MSM7X00A specific arch_idle - peripheral iomap and irq number definitions Signed-off-by: NBrian Swetland <swetland@google.com>
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- 16 10月, 2007 1 次提交
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由 eric miao 提交于
Signed-off-by: Neric miao <eric.y.miao@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 13 10月, 2007 1 次提交
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由 Russell King 提交于
PXA3 SoCs are supported by the Xscale3 CPU code rather than the Xscale CPU code. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 22 7月, 2007 1 次提交
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由 Quinn Jensen 提交于
This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: NQuinn Jensen <quinn.jensen@freescale.com> Acked-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 21 7月, 2007 5 次提交
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由 Catalin Marinas 提交于
Currently, Linux doesn't generate correct page tables for ARMv6 and later cores if the cache policy is different from the default one (it may lead to strongly ordered or shared device mappings). This patch disallows cache policies other than writeback and the CPU_[ID]CACHE_DISABLE options only affect the CP15 system control register rather than the page tables. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
This patch adds the necessary ifdef's to the proc-v7.S code and defines the v7wbi_tlb_fns macro in pgtable-nommu.h Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
The auxiliary control and the L2 auxiliary control registers are Cortex-A8 specific. They need to be removed from the generic ARMv7 support code. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
With this patch, Kconfig only selects CPU_HAS_ASID for the MMU case. It also corrects the typo in the v6wbi_tlb_fns definition in pgtable-nommu.h. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
If not MMU and not v6K, access to the TLS register has to be emulated. MMU-less systems do not provide a high page for kuser helpers. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 30 5月, 2007 1 次提交
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由 Catalin Marinas 提交于
We are currently using the ARMv6 operations but need to duplicate some of the code because of the introduction of the new CPU barrier instructions in ARMv7. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 17 5月, 2007 1 次提交
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由 Russell King 提交于
Presently, we check for the minimum ARM architecture that we're building for to determine whether we need ASID support. This is wrong - if we're going to support a range of CPUs which include ARMv6 or higher, we need the ASID. Convert the checks to use a new configuration symbol, and arrange for ARMv6 and higher CPU entries to select it. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 12 5月, 2007 3 次提交
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由 Andrew Victor 提交于
Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: NAndrew Victor <andrew@sanpeople.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Andrew Victor 提交于
Add support for Atmel's new AT91SAM9RL range of processors. Includes similar peripherals as other AT91SAM9 processors, but with a High-speed USB controller and various sizes of internal SRAM. Signed-off-by: NNicolas Ferre <nicolas.ferre@rfo.atmel.com> Signed-off-by: NAndrew Victor <andrew@sanpeople.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Kevin Hilman 提交于
Add base kernel support for the TI DaVinci platform. This patch only includes interrupts, timers, CPU identification, serial support and basic power and sleep controller init. More drivers to come. Signed-off-by: NKevin Hilman <khilman@mvista.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 09 5月, 2007 1 次提交
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由 Catalin Marinas 提交于
This patch adds the necessary lines to the Makefile and Kconfig files for enabling the compilation of the ARMv7 CPU support. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 18 2月, 2007 2 次提交
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由 Uwe Kleine-König 提交于
Signed-off-by: NUwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Robert P. J. Day 提交于
Replace the very few remaining "depends" Kconfig directives with "depends on". Signed-off-by: NRobert P. J. Day <rpjday@mindspring.com> Signed-off-by: NAdrian Bunk <bunk@stusta.de>
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- 12 2月, 2007 1 次提交
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由 Catalin Marinas 提交于
This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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