- 03 4月, 2014 1 次提交
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由 Ben Dooks 提交于
If the driver needs to change a clock rate, then it must be propogated through the MSTP clock to the parent clock (such as shdi0 -> sd0). Without this we cannot up-rate default clocks which are really slow (such as the mmcif1 which defaults to 12MHz where it could be running at 97MHz) Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 01 4月, 2014 1 次提交
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由 Ben Dooks 提交于
The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks parented to pll1_div2 where the hardware diagram shows these to be directly fed from pll1. This fixes the initial rate for sdh0 clock to be 97.5MHz instead of the reported 48MHz where the manual says the default register values are for 97.5MHz. Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 28 3月, 2014 2 次提交
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由 Sylwester Nawrocki 提交于
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sylwester Nawrocki 提交于
This restores the default clocks registration order as parsed from devicetree, i.e. as before commit 1771b10d "clk: respect the clock dependencies in of_clk_init", for when there is no explicit parent clock dependencies between clock providers specified in the device tree. It prevents regressions (boot failure, division by 0 errors) on imx and exynos platforms. Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 27 3月, 2014 4 次提交
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由 Barry Song 提交于
Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Chao Xie 提交于
The orignal code will use the bigger rate between "previous rate" and "current rate" when caculate the rate. In fact, hardware cares about the closest one. So choose the closer rate between "previous rate" and "current rate". Signed-off-by: NChao Xie <chao.xie@marvell.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Chao Xie 提交于
The formula is numerator/denominator = Fin / (Fout * factor) So Fout = Fin * denominator / (numerator * factor). Current clk_factor_round_rate and clk_factor_recalc_rate use wrong formula. This patch will fix them. Signed-off-by: NChao Xie <chao.xie@marvell.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Chao Xie 提交于
The code has typo when calculate denominator. It should use den_mask instead of num_mask. Signed-off-by: NChao Xie <chao.xie@marvell.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 26 3月, 2014 6 次提交
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由 Gabriel FERNANDEZ 提交于
The patch supports the A9-mux clocks used by ClockGenA9 A9-mux clock : Multiplexer inside ClockGenA9. A9 clock can be driven by either PLL or External clock (with an optional divide-by-2). This is implemented as 3-parent clock : PLL, Ext-clk OR Ext-clk/2 Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
The patch added support for DT registration of ClockGenA9/DDR/GPU ClockgenA9/DDR : It includes c32 type PLL (also in ClockgenA1x), hence only CLK_OF_DECLARE implementation is required. ClockgenGPU : It includes c65 type PLL (also in ClockgenAx), hence only CLK_OF_DECLARE implementation is required. Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
The patch supports the 216/432/660 type Quad Frequency Synthesizers used by ClockGenB/C/D/E/F QUADFS clock : It includes support for all 216/432/660 type Quad Frequency Synthesizers : implemented as Fixed Parent / Rate / Gate clock, with clock rate calculated reading H/w settings done at BOOT. QuadFS have 4 outputs : chan0 chan1 chan2 chan3 Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
The patch supports the VCC-mux and MUX clocks used by ClockGenC/F VCC-mux clock : Divider-Multiplexer-Gate inside ClockGenC/F It includes support for each channel : 4-parent Multiplexer, Post Divide by 1, 2, 4 or 8, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider, clk_mux, clk_gate and clk_composite (to combine all) MUX clock : 2-parent clock used inside ClockGenC/F. The clock is implemented using generic clocks implemented in the kernel clk_mux. Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
The patch supports the c65/c32 type PLLs used by ClockGenA(s) PLL clock : It includes support for all c65/c32 type PLLs inside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock, with clock rate calculated reading H/w settings done at BOOT. c65 PLLs have 2 outputs : HS and LS c32 PLLs have 1-4 outputs : ODFx Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
The patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s) DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s) It includes support for each channel : 3-parent Multiplexer, Divider for each Parent, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider and clk_mux. PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide the oscillator clock by factor-of-16. The clock is implemented using generic clocks implemented in the kernel clk_divider. Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 25 3月, 2014 3 次提交
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由 Alex Elder 提交于
Add a new clk_ops->debug_init method to allow a clock hardware driver to populate the clock's debugfs directory with entries beyond those common for every clock. Signed-off-by: NAlex Elder <elder@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Krzysztof Kozlowski 提交于
of_find_node_by_name() walks over all nodes and can thus walk outside of the parent node. Use of_get_child_by_name() instead. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Krzysztof Kozlowski 提交于
If parent device does not have of_node set the s2mps11_clk_parse_dt() returned NULL. This NULL was later passed to of_clk_add_provider() which dereferenced it in pr_debug() call. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Cc: <stable@vger.kernel.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 21 3月, 2014 4 次提交
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由 Zhangfei Gao 提交于
drivers/clk/hisilicon/clk-hi3620.c:338 mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)' Reported-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Wolfram Sang 提交于
Signed-off-by: NWolfram Sang <wsa@sang-engineering.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sascha Hauer 提交于
If a rate change failed it's the opportunity of the caller to handle this. Do not spam the log with a message. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
Most of the clock related dt-binding header files are located in dt-bindings/clock folder. It would be good to keep all the similar header files at a single location. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 20 3月, 2014 9 次提交
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由 Gregory CLEMENT 提交于
Until now the clock providers were initialized in the order found in the device tree. This led to have the dependencies between the clocks not respected: children clocks could be initialized before their parent clocks. Instead of forcing each platform to manage its own initialization order, this patch adds this work inside the framework itself. Using the data of the device tree the of_clk_init function now delayed the initialization of a clock provider if its parent provider was not ready yet. The strict dependency check (all parents of a given clk must be initialized) was added by Boris BREZILLON Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tang Yuantian 提交于
The clock bindings for Freescale CoreNet platform are updated. So, the driver needs to be updated accordingly. The main changes include: - Added a new node to present the input system clock - Changed PLL and MUX's compatible string Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Acked-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Jean-Jacques Hiblot 提交于
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Jean-Jacques Hiblot 提交于
The PCKRDY bit is not set until the system clock is enabled. This patch moves the management of the ready status in the system clock driver. Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Boris BREZILLON 提交于
System clks are just gates, and thus do not provide any rate operations. Authorize clk rate change to be propagated to system clk parents. Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Boris BREZILLON 提交于
Implement the determine_rate callback to choose the best parent clk that fulfills the requested rate. Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Emilio López 提交于
This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Emilio López 提交于
Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: NBoris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Emilio López 提交于
Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 19 3月, 2014 7 次提交
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由 Haojian Zhuang 提交于
Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
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由 Haojian Zhuang 提交于
Now only fixed rate clocks are appended into the clock driver. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
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由 Haojian Zhuang 提交于
The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
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由 Dinh Nguyen 提交于
WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NDinh Nguyen <dinguyen@altera.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
Since clock operation within S2MPS11 and S5M8767 are similar, we can support both the devices within a single driver. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Reviewed-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
The clocks in S2MPS11 and S5M8767 are managed in the same way, baring a difference in the register offset. It would be better to update existing S2MPS11 driver to support the clocks in S5M8767, rather than creating an almost duplicate driver altogether. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Reviewed-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Jonas Jensen 提交于
MOXA ART SoCs allow to determine PLL output and APB frequencies by reading registers holding multiplier and divisor information. Add a clock driver for this SoC. Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 17 3月, 2014 1 次提交
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由 Michal Simek 提交于
Move of_clk_init() from clock driver to enable options not to use zynq clock driver. Use for example fixed clock setting. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 14 3月, 2014 2 次提交
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由 Ezequiel Garcia 提交于
This commit adds support for the Core Divider clocks of the Armada 380 SoCs. Similarly to Armada 370 and XP, the Core Divider clocks of the 380 have gate capabilities. The only difference is the register layout. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-2-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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