提交 0b5c69ef 编写于 作者: T thread-liu

[update] stm32mp1 heap address.

上级 f549c792
......@@ -26,15 +26,19 @@ extern "C" {
#define STM32_FLASH_SIZE (192 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#if defined(BSP_USING_OPENAMP)
#define STM32_SRAM_BEGIN (uint32_t)0x10030000
#else
#define STM32_SRAM_BEGIN (uint32_t)0x2FFF0000
#define STM32_SRAM_SIZE (64)
#define STM32_SRAM_END (0x10030000 + 64 * 1024)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#endif
#define STM32_SRAM_SIZE (64)
#define STM32_SRAM_END (STM32_SRAM_BEGIN + (STM32_SRAM_SIZE * 1024))
#define HEAP_BEGIN STM32_SRAM_BEGIN
#define HEAP_END STM32_SRAM_END
void SystemClock_Config(void);
......@@ -46,4 +50,3 @@ extern void _Error_Handler(char *s, int num);
#endif
#endif
......@@ -84,7 +84,6 @@ void HAL_MspInit(void)
if (IS_ENGINEERING_BOOT_MODE())
{
__HAL_RCC_SYSRAM_CLK_ENABLE();
__HAL_RCC_RETRAM_CLK_ENABLE();
}
HAL_NVIC_SetPriority(RCC_WAKEUP_IRQn, 0, 0);
......
......@@ -12,6 +12,7 @@
#include "board.h"
void PeriphCommonClock_Config(void);
/**
* @brief System Clock Configuration
* @retval None
......@@ -124,6 +125,12 @@ void SystemClock_Config(void)
/**Set the HSE division factor for RTC clock
*/
__HAL_RCC_RTC_HSEDIV(24);
/* Configure the peripherals common clocks */
if(IS_ENGINEERING_BOOT_MODE())
{
PeriphCommonClock_Config();
}
}
......
......@@ -23,18 +23,23 @@ extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000)
#define STM32_FLASH_SIZE (191 * 1024)
#define STM32_FLASH_SIZE (192 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#if defined(BSP_USING_OPENAMP)
#define STM32_SRAM_BEGIN (uint32_t)0x10030000
#define STM32_SRAM_SIZE (64)
#define STM32_SRAM_END (0x10030000 + 64 * 1024)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
#define STM32_SRAM_BEGIN (uint32_t)0x2FFF0000
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#endif
#define STM32_SRAM_SIZE (64)
#define STM32_SRAM_END (STM32_SRAM_BEGIN + (STM32_SRAM_SIZE * 1024))
#define HEAP_BEGIN STM32_SRAM_BEGIN
#define HEAP_END STM32_SRAM_END
void SystemClock_Config(void);
......@@ -46,4 +51,3 @@ extern void _Error_Handler(char *s, int num);
#endif
#endif
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