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未验证 提交 0d1c709f 编写于 作者: W Wayne 提交者： GitHub
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Sync upstream (#6793) 

Co-authored-by: NWayne Lin <wclin@nuvoton.com>
上级 882a0af9
展开全部 隐藏空白更改
内联 并排
Showing with 11987 addition and 34479 deletion
bsp/nuvoton/README.md
浏览文件 @ 0d1c709f
......@@ -14,3 +14,4 @@ Current supported BSP shown in below table:
| NuMaker-M467HJ | CORTEX-M4 | [numaker-m467hj](numaker-m467hj) |
| NuMaker-IoT-M467 | CORTEX-M4 | [numaker-iot-m467](numaker-iot-m467) |
| NuMaker-HMI-MA35D1 | CORTEX-A35, CORTEX-M4 | [numaker-hmi-ma35d1](numaker-hmi-ma35d1), [ma35-rtp](ma35-rtp) |
| NuMaker-IOT-MA35D1 | CORTEX-A35, CORTEX-M4 | [numaker-iot-ma35d1](numaker-iot-ma35d1), [ma35-rtp](ma35-rtp) |
bsp/nuvoton/libraries/m460/rtt_port/drv_pdma.c
浏览文件 @ 0d1c709f
......@@ -154,12 +154,6 @@ static const nu_pdma_periph_ctl_t g_nu_pdma_peripheral_ctl_pool[ ] =
{ PDMA_SPI9_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_SPI10_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C0_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C1_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C2_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C3_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C4_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2S0_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2S1_TX, eMemCtl_SrcInc_DstFix },
......@@ -215,12 +209,6 @@ static const nu_pdma_periph_ctl_t g_nu_pdma_peripheral_ctl_pool[ ] =
{ PDMA_EPWM1_P2_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_EPWM1_P3_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C0_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C1_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C2_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C3_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C4_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2S0_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2S1_RX, eMemCtl_SrcFix_DstInc },
......
bsp/nuvoton/libraries/m480/StdDriver/src/nu_rtc.c
浏览文件 @ 0d1c709f
......@@ -67,15 +67,15 @@ void RTC_Open(S_RTC_TIME_DATA_T *sPt)
{
RTC->INIT = RTC_INIT_KEY;
if(RTC->INIT != RTC_INIT_ACTIVE_Msk)
if (RTC->INIT != RTC_INIT_ACTIVE_Msk)
{
RTC->INIT = RTC_INIT_KEY;
while(RTC->INIT != RTC_INIT_ACTIVE_Msk)
while (RTC->INIT != RTC_INIT_ACTIVE_Msk)
{
}
}
if(sPt == 0)
if (sPt == 0)
{
}
else
......@@ -110,14 +110,14 @@ void RTC_Close(void)
void RTC_32KCalibration(int32_t i32FrequencyX10000)
{
uint64_t u64Compensate;
int32_t i32RegInt,i32RegFra ;
int32_t i32RegInt, i32RegFra ;
if(!(SYS->CSERVER & 0x1))
if (!(SYS->CSERVER & 0x1))
{
u64Compensate = (uint64_t)(0x2710000000000);
u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000);
if(u64Compensate >= (uint64_t)0x400000)
if (u64Compensate >= (uint64_t)0x400000)
{
u64Compensate = (uint64_t)0x3FFFFF;
}
......@@ -128,23 +128,23 @@ void RTC_32KCalibration(int32_t i32FrequencyX10000)
else
{
/* Compute Integer and Fraction for RTC register*/
i32RegInt = (i32FrequencyX10000/10000) - 32752;
i32RegFra = ((((i32FrequencyX10000%10000)) * 64) + 5000) / 10000;
i32RegInt = (i32FrequencyX10000 / 10000) - 32752;
i32RegFra = ((((i32FrequencyX10000 % 10000)) * 64) + 5000) / 10000;
if(i32RegFra >= 0x40)
if (i32RegFra >= 0x40)
{
i32RegFra = 0x0;
i32RegInt++;
}
/* Judge Integer part is reasonable */
if ( (i32RegInt < 0) | (i32RegInt > 31) )
if ((i32RegInt < 0) | (i32RegInt > 31))
{
return;
}
RTC_WaitAccessEnable();
RTC->FREQADJ = (uint32_t)((i32RegInt<<8) | i32RegFra);
RTC->FREQADJ = (uint32_t)((i32RegInt << 8) | i32RegFra);
}
}
......@@ -204,13 +204,13 @@ void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
sPt->u32Day = u32Tmp + g_u32loDay;
/* Compute 12/24 hour */
if(sPt->u32TimeScale == RTC_CLOCK_12)
if (sPt->u32TimeScale == RTC_CLOCK_12)
{
u32Tmp = (g_u32hiHour * 10ul);
u32Tmp += g_u32loHour;
sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
if(sPt->u32Hour >= 21ul)
if (sPt->u32Hour >= 21ul)
{
sPt->u32AmPm = RTC_PM;
sPt->u32Hour -= 20ul;
......@@ -301,13 +301,13 @@ void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
sPt->u32Day = u32Tmp + g_u32loDay;
/* Compute 12/24 hour */
if(sPt->u32TimeScale == RTC_CLOCK_12)
if (sPt->u32TimeScale == RTC_CLOCK_12)
{
u32Tmp = (g_u32hiHour * 10ul);
u32Tmp += g_u32loHour;
sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
if(sPt->u32Hour >= 21ul)
if (sPt->u32Hour >= 21ul)
{
sPt->u32AmPm = RTC_PM;
sPt->u32Hour -= 20ul;
......@@ -366,7 +366,7 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
{
uint32_t u32RegCAL, u32RegTIME;
if(sPt == 0ul)
if (sPt == NULL)
{
}
else
......@@ -375,14 +375,14 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
RTC_WaitAccessEnable();
if(sPt->u32TimeScale == RTC_CLOCK_12)
if (sPt->u32TimeScale == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
/*-------------------------------------------------------------------------------------------------*/
/* Important, range of 12-hour PM mode is 21 up to 32 */
/*-------------------------------------------------------------------------------------------------*/
if(sPt->u32AmPm == RTC_PM)
if (sPt->u32AmPm == RTC_PM)
{
sPt->u32Hour += 20ul;
}
......@@ -447,7 +447,7 @@ void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
{
uint32_t u32RegCALM, u32RegTALM;
if(sPt == 0)
if (sPt == NULL)
{
}
else
......@@ -456,14 +456,14 @@ void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
RTC_WaitAccessEnable();
if(sPt->u32TimeScale == RTC_CLOCK_12)
if (sPt->u32TimeScale == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
/*-------------------------------------------------------------------------------------------------*/
/* Important, range of 12-hour PM mode is 21 up to 32 */
/*-------------------------------------------------------------------------------------------------*/
if(sPt->u32AmPm == RTC_PM)
if (sPt->u32AmPm == RTC_PM)
{
sPt->u32Hour += 20ul;
}
......@@ -549,7 +549,7 @@ void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint3
uint32_t u32RegTIME;
/* Important, range of 12-hour PM mode is 21 up to 32 */
if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
{
u32Hour += 20ul;
}
......@@ -565,7 +565,7 @@ void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint3
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
RTC_WaitAccessEnable();
if(u32TimeMode == RTC_CLOCK_12)
if (u32TimeMode == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
}
......@@ -624,7 +624,7 @@ void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second,
uint32_t u32RegTALM;
/* Important, range of 12-hour PM mode is 21 up to 32 */
if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
{
u32Hour += 20ul;
}
......@@ -640,7 +640,7 @@ void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second,
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
RTC_WaitAccessEnable();
if(u32TimeMode == RTC_CLOCK_12)
if (u32TimeMode == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
}
......@@ -861,15 +861,15 @@ void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, ui
RTC_WaitAccessEnable();
u32Reg = RTC->TAMPCTL;
u32TmpReg = ( RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |
(u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos) );
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |
(u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos));
for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
for (i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
{
if(u32TamperSelect & (0x1ul << i))
if (u32TamperSelect & (0x1ul << i))
{
u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk|RTC_TAMPCTL_TAMP0LV_Msk|RTC_TAMPCTL_TAMP0DBEN_Msk) << (i*4ul));
u32Reg |= (u32TmpReg << (i*4ul));
u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (i * 4ul));
u32Reg |= (u32TmpReg << (i * 4ul));
}
}
......@@ -904,11 +904,11 @@ void RTC_StaticTamperDisable(uint32_t u32TamperSelect)
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk);
for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
for (i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
{
if(u32TamperSelect & (0x1ul << i))
if (u32TamperSelect & (0x1ul << i))
{
u32Reg &= ~(u32TmpReg << (i*4ul));
u32Reg &= ~(u32TmpReg << (i * 4ul));
}
}
......@@ -958,7 +958,7 @@ void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32
u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk);
u32Reg |= ((u32Pair1Source & 0x1ul) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1ul) << RTC_TAMPCTL_DYN2ISS_Pos);
if(u32DebounceEn)
if (u32DebounceEn)
{
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk |
RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
......@@ -968,22 +968,22 @@ void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
}
for(i = 0ul; i < MAX_PAIR_NUM; i++)
for (i = 0ul; i < MAX_PAIR_NUM; i++)
{
if(u32PairSel & (0x1ul << i))
if (u32PairSel & (0x1ul << i))
{
u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i*8ul));
u32Reg |= (u32TmpReg << (i*8ul));
u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i * 8ul));
u32Reg |= (u32TmpReg << (i * 8ul));
}
}
if((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT))
if ((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT))
{
u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk;
u32Reg |= u32Tamper2Debounce;
}
if((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT))
if ((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT))
{
u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk;
u32Reg |= u32Tamper4Debounce;
......@@ -1015,23 +1015,23 @@ void RTC_DynamicTamperDisable(uint32_t u32PairSel)
RTC_WaitAccessEnable();
u32Reg = RTC->TAMPCTL;
if((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT))
if ((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT))
{
u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk;
}
if((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT))
if ((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT))
{
u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk;
}
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
for(i = 0ul; i < MAX_PAIR_NUM; i++)
for (i = 0ul; i < MAX_PAIR_NUM; i++)
{
if(u32PairSel & (0x1ul << i))
if (u32PairSel & (0x1ul << i))
{
u32Reg &= ~(u32TmpReg << ((i*8ul)));
u32Reg &= ~(u32TmpReg << ((i * 8ul)));
}
}
......
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ma35d1.h
浏览文件 @ 0d1c709f
......@@ -239,9 +239,9 @@ typedef enum IRQn
/****** Platform Exceptions Numbers ***************************************************/
LVD_IRQn = 32, /*!< Low Voltage detection Interrupt */
A35PMU_IRQn = 33, /*!< A35 PMU Interrupt */
HSEM_IRQn = 34, /*!< Hardware Semaphore Interrupt */
HWSEM0_IRQn = 34, /*!< Hardware Semaphore Interrupt */
CKFAIL_IRQn = 35, /*!< Clock failed Interrupt */
WRHO_IRQn = 36, /*!< Wormhole Interrupt */
WHC0_IRQn = 36, /*!< Wormhole Interrupt */
RTC_IRQn = 37, /*!< Real Time Clock Interrupt */
TAMPER_IRQn = 38, /*!< Tamper detection Interrupt */
WDT0_IRQn = 39, /*!< Watchdog timer 0 Interrupt */
......@@ -266,7 +266,7 @@ typedef enum IRQn
SSPCC_IRQn = 58, /*!< SSPCC Interrupt */
GFX_IRQn = 59, /*!< GFX GC520L Interrupt (Graphic Engine) */
VDE_IRQn = 60, /*!< Video Decoder (VC8000) Interrupt */
WRHO1_IRQn = 61, /*!< WRHO 1 Interrupt */
WHC1_IRQn = 61, /*!< WRHO 1 Interrupt */
SDH0_IRQn = 62, /*!< SDH 0 Interrupt */
SDH1_IRQn = 63, /*!< SDH 1 Interrupt */
HSUSBD_IRQn = 64, /*!< USB 2.0 High-Speed Device Interrupt */
......@@ -468,6 +468,7 @@ typedef enum IRQn
#include "sdh_reg.h"
#include "ccap_reg.h"
#include "nfi_reg.h"
/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base
Memory Mapped Structure for Peripherals
......@@ -781,6 +782,7 @@ typedef enum IRQn
#define CCAP0 ((CCAP_T*) CCAP0_BASE)
#define CCAP1 ((CCAP_T*) CCAP1_BASE)
#define NFI ((NFI_T*) NAND_BASE)
/*@}*/ /* end of group ERIPHERAL_DECLARATION */
/** @addtogroup IO_ROUTINE I/O Routines
......
bsp/nuvoton/libraries/ma35/StdDriver/SConscript
浏览文件 @ 0d1c709f
......@@ -8,6 +8,20 @@ src = Glob('*src/*.c') + Glob('src/*.cpp')
cpppath = [cwd + '/inc']
libpath = [cwd + '/lib']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
if not GetDepend('BSP_USE_STDDRIVER_SOURCE'):
if rtconfig.CROSS_TOOL == 'keil':
if GetOption('target') == 'mdk5' and os.path.isfile('./lib/libstddriver_keil.lib'):
libs += ['libstddriver_keil']
elif rtconfig.CROSS_TOOL == 'gcc' and os.path.isfile('./lib/libstddriver_gcc_CM4.a') and GetDepend('USE_MA35D1_SUBM'):
libs += ['libstddriver_gcc_CM4']
elif rtconfig.CROSS_TOOL == 'gcc' and os.path.isfile('./lib/libstddriver_gcc_CA35.a') and GetDepend('USE_MA35D1_AARCH32'):
libs += ['libstddriver_gcc_CA35']
if not libs:
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
else:
src = []
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath)
Return('group')
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_clk.h
浏览文件 @ 0d1c709f
......@@ -363,9 +363,9 @@ extern "C"
#define PDMA1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA1 Module \hideinitializer */
#define PDMA2_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< PDMA2 Module \hideinitializer */
#define PDMA3_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< PDMA3 Module \hideinitializer */
#define WH0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< WH0 Module \hideinitializer */
#define WH1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< WH1 Module \hideinitializer */
#define HWS_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< HWS Module \hideinitializer */
#define WHC0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< WH0 Module \hideinitializer */
#define WHC1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< WH1 Module \hideinitializer */
#define HWSEM0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< HWS Module \hideinitializer */
#define EBI_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< EBI Module \hideinitializer */
#define SRAM0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< SRAM0 Module \hideinitializer */
#define SRAM1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< SRAM1 Module \hideinitializer */
......
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_disp.h
浏览文件 @ 0d1c709f
......@@ -190,6 +190,7 @@ void DISP_SetBlendValue(uint32_t u32GloAV_Src, uint32_t u32GloAV_Dst);
void DISP_SetColorKeyValue(uint32_t u32ColorKeyLow, uint32_t u32ColorKeyHigh);
int DISP_SetFBAddr(E_DISP_LAYER eLayer, uint32_t u32DMAFBStartAddr);
int DISP_SetFBFmt(E_DISP_LAYER eLayer, E_FB_FMT eFbFmt, uint32_t u32Pitch);
uint32_t DISP_LCDTIMING_GetFPS(const DISP_LCD_TIMING* psDispLCDTiming);
/*@}*/ /* end of group DISP_EXPORTED_FUNCTIONS */
......
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_hwsem.h
浏览文件 @ 0d1c709f
......@@ -13,6 +13,11 @@ extern "C"
{
#endif
#ifdef __has_include
#if __has_include("rtconfig.h")
#include "rtconfig.h"
#endif
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
......@@ -26,9 +31,23 @@ extern "C"
@{
*/
#define HWSEM_CNT 8ul /*!<HWSEM count \hideinitializer */
#define HWSEM_NOLOCK 0ul /*!<Semaphore is non-lock \hideinitializer */
#define HWSEM_LOCK_BY_A35 1ul /*!<Semaphore lock by A35 \hideinitializer */
#define HWSEM_LOCK_BY_M4 2ul /*!<Semaphore lock by M4 \hideinitializer */
#if defined(USE_MA35D1_SUBM)
#define HWSEM_LOCK_BY_OWNER HWSEM_LOCK_BY_M4
#define INTSTS_CORE INTSTSM4
#define INTEN_CORE INTENM4
#else
#define HWSEM_LOCK_BY_OWNER HWSEM_LOCK_BY_A35
#define INTSTS_CORE INTSTSA35
#define INTEN_CORE INTENA35
#endif
#define HWSEM_INTSTS_SEM0IF_Pos 0
#define HWSEM_INTSTS_SEM0IF_Msk (1<<HWSEM_INTSTS_SEM0IF_Pos)
#define HWSEM_INTEN_SEM0IEN_Pos 0
#define HWSEM_INTEN_SEM0IEN_Msk (1<<HWSEM_INTEN_SEM0IEN_Pos)
/*@}*/ /* end of group HWSEM_EXPORTED_CONSTANTS */
......@@ -58,6 +77,17 @@ extern "C"
*/
#define HWSEM_IS_LOCKED(hwsem, u32Num) ((hwsem)->SEM[(u32Num)] & (HWSEM_SEM_ID_Msk))
/**
* @brief
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
*
* @retval 0 The key of specified semaphore.
* \hideinitializer
*/
#define HWSEM_GET_KEY(hwsem, u32Num) (((hwsem)->SEM[(u32Num)]&HWSEM_SEM_KEY_Msk) >> HWSEM_SEM_KEY_Pos)
/**
* @brief Enable specified HWSEM interrupt
*
......@@ -67,7 +97,7 @@ extern "C"
*
* \hideinitializer
*/
#define HWSEM_ENABLE_INT(hwsem, u32Num) ((hwsem)->INTENM4 |= (HWSEM_INTENM4_SEM0IEN_Msk << (u32Num)))
#define HWSEM_ENABLE_INT(hwsem, u32Num) ((hwsem)->INTEN_CORE |= (HWSEM_INTEN_SEM0IEN_Msk << (u32Num)))
/**
......@@ -79,7 +109,7 @@ extern "C"
*
* \hideinitializer
*/
#define HWSEM_DISABLE_INT(hwsem, u32Num) ((hwsem)->INTENM4 &= ~(HWSEM_INTENM4_SEM0IEN_Msk << (u32Num)))
#define HWSEM_DISABLE_INT(hwsem, u32Num) ((hwsem)->INTEN_CORE &= ~(HWSEM_INTEN_SEM0IEN_Msk << (u32Num)))
/**
* @brief Get specified interrupt flag
......@@ -91,7 +121,7 @@ extern "C"
* Otherwise The specified interrupt is happened.
* \hideinitializer
*/
#define HWSEM_GET_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTSM4 & (HWSEM_INTSTSM4_SEM0IF_Msk << (u32Num)))
#define HWSEM_GET_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTS_CORE & (HWSEM_INTSTS_SEM0IF_Msk << (u32Num)))
/**
......@@ -102,7 +132,7 @@ extern "C"
*
* \hideinitializer
*/
#define HWSEM_CLR_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTSM4 = (HWSEM_INTSTSM4_SEM0IF_Msk << (u32Num)))
#define HWSEM_CLR_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTS_CORE = (HWSEM_INTSTS_SEM0IF_Msk << (u32Num)))
/**
......@@ -115,6 +145,7 @@ extern "C"
* \hideinitializer
*/
#define HWSEM_UNLOCK(hwsem, u32Num, u8Key) ((hwsem)->SEM[(u32Num)] = ((u8Key) << HWSEM_SEM_KEY_Pos) & HWSEM_SEM_KEY_Msk)
#define HWSEM_LOCK HWSEM_UNLOCK
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE int32_t HWSEM_Try_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key);
......@@ -133,7 +164,7 @@ __STATIC_INLINE void HWSEM_Spin_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8
__STATIC_INLINE int32_t HWSEM_Try_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key)
{
hwsem->SEM[u32Num] = (u8Key << HWSEM_SEM_KEY_Pos);
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_M4 &&
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_OWNER &&
(hwsem->SEM[u32Num] & HWSEM_SEM_KEY_Msk) == (u8Key << HWSEM_SEM_KEY_Pos))
return 0;
else
......@@ -154,7 +185,7 @@ __STATIC_INLINE void HWSEM_Spin_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8
while (1)
{
hwsem->SEM[u32Num] = (u8Key << HWSEM_SEM_KEY_Pos);
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_M4 &&
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_OWNER &&
(hwsem->SEM[u32Num] & HWSEM_SEM_KEY_Msk) == (u8Key << HWSEM_SEM_KEY_Pos))
break;
}
......
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sdh.h
浏览文件 @ 0d1c709f
......@@ -8,6 +8,10 @@
#ifndef __NU_SDH_H__
#define __NU_SDH_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
#ifdef __cplusplus
extern "C"
{
......@@ -116,6 +120,10 @@ void SDH_SetPower(SDH_T *sdh, uint32_t u32OnOff);
}
#endif
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_clk.c
浏览文件 @ 0d1c709f
......@@ -558,7 +558,7 @@ void CLK_DisableXtalRC(uint32_t u32ClkMask)
* - \ref PDMA3_MODULE
* - \ref WH0_MODULE
* - \ref WH1_MODULE
* - \ref HWS_MODULE
* - \ref HWSEM0_MODULE
* - \ref EBI_MODULE
* - \ref SRAM0_MODULE
* - \ref SRAM1_MODULE
......@@ -692,7 +692,7 @@ void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
* - \ref PDMA3_MODULE
* - \ref WH0_MODULE
* - \ref WH1_MODULE
* - \ref HWS_MODULE
* - \ref HWSEM0_MODULE
* - \ref EBI_MODULE
* - \ref SRAM0_MODULE
* - \ref SRAM1_MODULE
......@@ -1471,7 +1471,7 @@ uint64_t CLK_SetPLLFreq(uint32_t u32PllIdx, uint32_t u32OpMode, uint64_t PllSrcC
* - \ref PDMA3_MODULE
* - \ref WH0_MODULE
* - \ref WH1_MODULE
* - \ref HWS_MODULE
* - \ref HWSEM0_MODULE
* - \ref EBI_MODULE
* - \ref SRAM0_MODULE
* - \ref SRAM1_MODULE
......@@ -1611,7 +1611,7 @@ uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
* - \ref PDMA3_MODULE
* - \ref WH0_MODULE
* - \ref WH1_MODULE
* - \ref HWS_MODULE
* - \ref HWSEM0_MODULE
* - \ref EBI_MODULE
* - \ref SRAM0_MODULE
* - \ref SRAM1_MODULE
......
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_disp.c
浏览文件 @ 0d1c709f
......@@ -258,6 +258,23 @@ int DISP_SetTransparencyMode(E_DISP_LAYER eLayer, E_TRANSPARENCY_MODE eTM)
return 0;
}
uint32_t DISP_LCDTIMING_GetFPS(const DISP_LCD_TIMING* psDispLCDTiming)
{
static uint32_t u32FPS = 0;
if ( psDispLCDTiming != NULL )
{
uint32_t u32HTotal, u32VTotal;
u32HTotal = psDispLCDTiming->u32HA + psDispLCDTiming->u32HBP + psDispLCDTiming->u32HFP + psDispLCDTiming->u32HSL;
u32VTotal = psDispLCDTiming->u32VA + psDispLCDTiming->u32VBP + psDispLCDTiming->u32VFP + psDispLCDTiming->u32VSL;
u32FPS = psDispLCDTiming->u32PCF / u32HTotal / u32VTotal;
}
return u32FPS;
}
int DISP_Trigger(E_DISP_LAYER eLayer, uint32_t u32Action)
{
switch (eLayer)
......
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_i2s.c
浏览文件 @ 0d1c709f
......@@ -28,10 +28,8 @@ static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s);
* @param[in] i2s The pointer of the specified I2S module.
* @return Source clock frequency of I2S peripheral.
* @details
* 0: _HXT
* 1: APLL
* 2: PCLK0
* 3: HIRC
* 0: APLL
* 1: SYSCLK1_DIV2
*/
static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
......
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_pdma.c
浏览文件 @ 0d1c709f
......@@ -240,8 +240,8 @@ void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral,
if (u32ScatterEn)
{
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
pdma->DSCT[u32Ch].NEXT = u32DescAddr;
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
}
else
{
......
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_rtc.c
浏览文件 @ 0d1c709f
......@@ -65,12 +65,12 @@ static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32
int32_t RTC_Open(S_RTC_TIME_DATA_T *sPt)
{
RTC->INIT = RTC_INIT_KEY;
if (RTC->INIT != RTC_INIT_ACTIVE_Msk)
if ((RTC->INIT & RTC_INIT_ACTIVE_Msk) != RTC_INIT_ACTIVE_Msk)
{
uint32_t u32Timeout = 10000000ul;
uint32_t volatile u32Timeout = 10000000ul;
RTC->INIT = RTC_INIT_KEY;
while ((u32Timeout > 0) && (RTC->INIT != RTC_INIT_ACTIVE_Msk))
while ((u32Timeout > 0) && ((RTC->INIT & RTC_INIT_ACTIVE_Msk) != RTC_INIT_ACTIVE_Msk))
{
u32Timeout--;
}
......@@ -317,7 +317,7 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
{
uint32_t u32RegCAL, u32RegTIME;
if (sPt == 0ul)
if (sPt == NULL)
{
}
else
......@@ -396,7 +396,7 @@ void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
{
uint32_t u32RegCALM, u32RegTALM;
if (sPt == 0)
if (sPt == NULL)
{
}
else
......
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sys.c
浏览文件 @ 0d1c709f
......@@ -42,7 +42,7 @@ extern "C"
* - \ref WRHO1_RST
* - \ref GMAC0_RST
* - \ref GMAC1_RST
* - \ref HWSEM_RST
* - \ref HWSEM0_RST
* - \ref EBI_RST
* - \ref HSUSBH0_RST
* - \ref HSUSBH1_RST
......
bsp/nuvoton/libraries/ma35/UsbHostLib/inc/config.h
浏览文件 @ 0d1c709f
......@@ -25,8 +25,6 @@
#define HCLK_MHZ 700 /* used for loop-delay. must be larger than
true HCLK clock MHz */
#define NON_CACHE_MASK (0xC0000000)
static __inline void ENABLE_OHCI_IRQ(void)
{
rt_hw_interrupt_umask(USBH0_IRQn);
......@@ -87,7 +85,7 @@ static __inline void DISABLE_EHCI_IRQ(void)
limited. */
#define MAX_UDEV_DRIVER 8 /*!< Maximum number of registered drivers */
#define MAX_ALT_PER_IFACE 8 /*!< maximum number of alternative interfaces per interface */
#define MAX_ALT_PER_IFACE 32 /*!< maximum number of alternative interfaces per interface */
#define MAX_EP_PER_IFACE 6 /*!< maximum number of endpoints per interface */
#define MAX_HUB_DEVICE 8 /*!< Maximum number of hub devices */
......@@ -95,8 +93,8 @@ static __inline void DISABLE_EHCI_IRQ(void)
are all allocated from this pool. Allocated unit size is determined by MEM_POOL_UNIT_SIZE.
May allocate one or more units depend on hardware descriptor type. */
#define MEM_POOL_UNIT_SIZE 64 /*!< A fixed hard coding setting. Do not change it! */
#define MEM_POOL_UNIT_NUM 256 /*!< Increase this or heap size if memory allocate failed. */
#define MEM_POOL_UNIT_SIZE 256 /*!< A fixed hard coding setting. Do not change it! */
#define MEM_POOL_UNIT_NUM 64 /*!< Increase this or heap size if memory allocate failed. */
/*----------------------------------------------------------------------------------------*/
/* Re-defined staff for various compiler */
......
bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ehci.c_
浏览文件 @ 0d1c709f
......@@ -11,15 +11,15 @@
/// @cond HIDDEN_SYMBOLS
static QH_T *_H_qh; /* head of reclamation list */
static qTD_T *_ghost_qtd; /* used as a terminator qTD */
static QH_T *qh_remove_list;
static QH_T *_H_qh __attribute__((section(".usbhostlib._H_qh"))); /* head of reclamation list */
static qTD_T *_ghost_qtd __attribute__((section(".usbhostlib._ghost_qtd"))); /* used as a terminator qTD */
static QH_T *qh_remove_list __attribute__((section(".usbhostlib.qh_remove_list")));
static uint32_t _PFList_mem[FL_SIZE] __attribute__((aligned(4096))); /* Periodic frame list */
static uint32_t _PFList_mem[FL_SIZE] __attribute__((section(".usbhostlib._PFList_mem"))) __attribute__((aligned(4096))); /* Periodic frame list */
static uint32_t *_PFList;
static uint32_t *_PFList __attribute__((section(".usbhostlib._PFList")));
static QH_T *_Iqh[NUM_IQH];
static QH_T *_Iqh[NUM_IQH] __attribute__((section(".usbhostlib.QH_T"))) __attribute__((aligned(32)));;
static int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep);
static void scan_isochronous_list(void);
......@@ -29,24 +29,25 @@ static void scan_isochronous_list(void);
static void dump_ehci_regs(void)
{
USB_debug("Dump HSUSBH(0x%x) registers:\n", ptr_to_u32(&_ehci->EHCVNR));
USB_debug(" EHCVNR = 0x%x\n", _ehci->EHCVNR);
USB_debug(" EHCSPR = 0x%x\n", _ehci->EHCSPR);
USB_debug(" EHCCPR = 0x%x\n", _ehci->EHCCPR);
USB_debug(" UCMDR = 0x%x\n", _ehci->UCMDR);
USB_debug(" USTSR = 0x%x\n", _ehci->USTSR);
USB_debug(" UIENR = 0x%x\n", _ehci->UIENR);
USB_debug(" UFINDR = 0x%x\n", _ehci->UFINDR);
USB_debug(" UPFLBAR = 0x%x\n", _ehci->UPFLBAR);
USB_debug(" UCALAR = 0x%x\n", _ehci->UCALAR);
USB_debug(" UCFGR = 0x%x\n", _ehci->UCFGR);
USB_debug(" UPSCR0 = 0x%x\n", _ehci->UPSCR);
USB_debug(" EHCVNR = 0x%08x\n", _ehci->EHCVNR);
USB_debug(" EHCSPR = 0x%08x\n", _ehci->EHCSPR);
USB_debug(" EHCCPR = 0x%08x\n", _ehci->EHCCPR);
USB_debug(" UCMDR = 0x%08x\n", _ehci->UCMDR);
USB_debug(" USTSR = 0x%08x\n", _ehci->USTSR);
USB_debug(" UIENR = 0x%08x\n", _ehci->UIENR);
USB_debug(" UFINDR = 0x%08x\n", _ehci->UFINDR);
USB_debug(" UPFLBAR = 0x%08x\n", _ehci->UPFLBAR);
USB_debug(" UCALAR = 0x%08x\n", _ehci->UCALAR);
USB_debug(" UCFGR = 0x%08x\n", _ehci->UCFGR);
USB_debug(" UPSCR0 = 0x%08x\n", _ehci->UPSCR[0]);
// USB_debug(" UPSCR1 = 0x%08x\n", _ehci->UPSCR[1]);
// USB_debug(" PHYCTL0 = 0x%x\n", _ehci->USBPCR0);
// USB_debug(" PHYCTL1 = 0x%x\n", _ehci->USBPCR1);
}
static void dump_ehci_ports()
{
USB_debug("_ehci port0=0x%x\n", _ehci->UPSCR);
USB_debug("_ehci port0=0x%x, port1=0x%x\n", _ehci->UPSCR[0], _ehci->UPSCR[1]);
}
static void dump_ehci_qtd(qTD_T *qtd)
......@@ -150,7 +151,7 @@ static void init_periodic_frame_list()
QH_T *qh_p;
int i, idx, interval;
_PFList = (uint32_t *)((uint32_t)_PFList_mem | NON_CACHE_MASK);
_PFList = (uint32_t *)((uint32_t)&_PFList_mem[0]);
memset(_PFList, 0, sizeof(_PFList_mem));
iso_ep_list = NULL;
......@@ -281,6 +282,8 @@ static int ehci_init(void)
else
return USBH_ERR_EHCI_INIT; /* Invalid FL_SIZE setting! */
_ehci->UPFLBAR = (uint32_t)_PFList;
/*------------------------------------------------------------------------------------*/
/* start run */
/*------------------------------------------------------------------------------------*/
......@@ -295,8 +298,8 @@ static int ehci_init(void)
init_periodic_frame_list();
_ehci->UPFLBAR = (uint32_t)_PFList;
usbh_delay_ms(10); /* delay 10 ms */
//usbh_delay_ms(10); /* delay 10 ms */
//dump_ehci_regs();
return 0;
}
......@@ -611,6 +614,7 @@ static int ehci_ctrl_xfer(UTR_T *utr)
_H_qh->HLink = QH_HLNK_QH(qh);
}
//dump_ehci_regs();
/* Start transfer */
_ehci->UCMDR |= HSUSBH_UCMDR_ASEN_Msk; /* start asynchronous transfer */
return 0;
......@@ -1098,8 +1102,13 @@ void EHCI_IRQHandler(int vector, void *param)
USB_error("Transfer error!\n");
}
if (intsts & HSUSBH_USTSR_USBINT_Msk)
if (intsts & (HSUSBH_USTSR_USBINT_Msk | HSUSBH_USTSR_UERRINT_Msk))
{
if (intsts & HSUSBH_USTSR_UERRINT_Msk)
{
USB_error("Transfer error!\n");
}
/* some transfers completed, travel asynchronous */
/* and periodic lists to find and reclaim them. */
scan_asynchronous_list();
......@@ -1140,12 +1149,12 @@ static int ehci_rh_port_reset(int port)
_ehci->UPSCR[port] = (_ehci->UPSCR[port] | HSUSBH_UPSCR_PRST_Msk) & ~HSUSBH_UPSCR_PE_Msk;
t0 = usbh_get_ticks();
while (usbh_get_ticks() - t0 < (reset_time) + 1) ; /* wait at least 50 ms */
while (usbh_get_ticks() - t0 < (reset_time/10) + 1) ; /* wait at least 50 ms */
_ehci->UPSCR[port] &= ~HSUSBH_UPSCR_PRST_Msk;
t0 = usbh_get_ticks();
while (usbh_get_ticks() - t0 < (reset_time) + 1)
while (usbh_get_ticks() - t0 < (reset_time/10) + 1)
{
if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) ||
((_ehci->UPSCR[port] & (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)) == (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)))
......@@ -1174,7 +1183,7 @@ static int ehci_rh_polling(void)
int port;
int connect_status, t0, debounce_tick;
for (port = 0; port < EHCI_PORT_CNT; port++)
for (port = 0; port < 1; port++)
{
if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CSC_Msk))
continue;
......@@ -1197,7 +1206,7 @@ static int ehci_rh_polling(void)
/* Port de-bounce */
/*--------------------------------------------------------------------------------*/
t0 = usbh_get_ticks();
debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME);
debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME/10);
connect_status = _ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk;
while (usbh_get_ticks() - t0 < debounce_tick)
{
......
bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ohci.c_
浏览文件 @ 0d1c709f
......@@ -17,11 +17,9 @@
#define PORT_CNT (_ohci->HcRhDescriptorA & 0xf)
static uint8_t _hcca_mem[256] __attribute__((aligned(256)));
static HCCA_T _hcca __attribute__((section(".usbhostlib._hcca"))) __attribute__((aligned(256)));
static HCCA_T *_hcca;
static ED_T *_Ied[6];
static ED_T * _Ied[6] __attribute__((section(".usbhostlib._Ied")));
static ED_T *ed_remove_list;
......@@ -97,7 +95,7 @@ static void init_hcca_int_table()
ED_T *ed_p;
int i, idx, interval;
memset(_hcca->int_table, 0, sizeof(_hcca->int_table));
memset(_hcca.int_table, 0, sizeof(_hcca.int_table));
for (i = 5; i >= 0; i--) /* interval = i^2 */
{
......@@ -108,13 +106,13 @@ static void init_hcca_int_table()
for (idx = interval - 1; idx < 32; idx += interval)
{
if (_hcca->int_table[idx] == 0) /* is empty list, insert directly */
if (_hcca.int_table[idx] == 0) /* is empty list, insert directly */
{
_hcca->int_table[idx] = (uint32_t)_Ied[i];
_hcca.int_table[idx] = (uint32_t)_Ied[i];
}
else
{
ed_p = (ED_T *)_hcca->int_table[idx];
ed_p = (ED_T *)_hcca.int_table[idx];
while (1)
{
......@@ -133,7 +131,7 @@ static void init_hcca_int_table()
}
}
static ED_T *get_int_tree_head_node(int interval)
static ED_T * get_int_tree_head_node(int interval)
{
int i;
......@@ -166,8 +164,6 @@ static int ohci_init(void)
uint32_t fminterval;
volatile int i;
_hcca = (HCCA_T *)((uint32_t)_hcca_mem | NON_CACHE_MASK);
if (ohci_reset() < 0)
return -1;
......@@ -180,11 +176,11 @@ static int ohci_init(void)
_ohci->HcControlHeadED = 0; /* control ED list head */
_ohci->HcBulkHeadED = 0; /* bulk ED list head */
_ohci->HcHCCA = (uint32_t)_hcca; /* HCCA area */
_ohci->HcHCCA = (uint32_t)&_hcca; /* HCCA area */
/* periodic start 90% of frame interval */
fminterval = 0x2edf; /* 11,999 */
_ohci->HcPeriodicStart = (fminterval * 9) / 10;
_ohci->HcPeriodicStart = (fminterval*9)/10;
/* set FSLargestDataPacket, 10,104 for 0x2edf frame interval */
fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
......@@ -342,7 +338,7 @@ static uint32_t ed_make_info(UDEV_T *udev, EP_INFO_T *ep)
static void write_td(TD_T *td, uint32_t info, uint8_t *buff, uint32_t data_len)
{
uint32_t baddr = ptr_to_u32(buff);
td->Info = info;
td->CBP = (((baddr == 0) || !data_len) ? 0 : baddr);
td->BE = (((baddr == 0) || !data_len) ? 0 : baddr + data_len - 1);
......@@ -661,7 +657,7 @@ static int ohci_int_xfer(UTR_T *utr)
info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_INT);
/* Keep data toggle */
info = (info & ~(1 << 25)) | (td->Info & (1 << 25));
info = (info & ~(1<<25)) | (td->Info & (1<<25));
/* fill this TD */
write_td(td, info, utr->buff, utr->data_len);
......@@ -735,7 +731,7 @@ static int ohci_iso_xfer(UTR_T *utr)
/* Prepare TDs */
/*------------------------------------------------------------------------------------*/
if (utr->bIsoNewSched) /* Is the starting of isochronous streaming? */
ed->next_sf = _hcca->frame_no + OHCI_ISO_DELAY;
ed->next_sf = _hcca.frame_no + OHCI_ISO_DELAY;
utr->td_cnt = 0;
utr->iso_sf = ed->next_sf;
......@@ -759,7 +755,7 @@ static int ohci_iso_xfer(UTR_T *utr)
td->PSW[0] = 0xE000 | (buff_addr & 0xFFF);
td->ed = ed;
utr->td_cnt++; /* increase TD count, for recalim counter */
utr->td_cnt++; /* increase TD count, for reclaim counter */
/* chain to end of TD list */
if (td_list == NULL)
......@@ -841,7 +837,7 @@ static int ohci_rh_port_reset(int port)
_ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_PRS_Msk;
t0 = usbh_get_ticks();
while (usbh_get_ticks() - t0 < (reset_time) + 1)
while (usbh_get_ticks() - t0 < (reset_time/10) + 1)
{
/*
* If device is disconnected or port enabled, we can stop port reset.
......@@ -853,7 +849,7 @@ static int ohci_rh_port_reset(int port)
reset_time += PORT_RESET_RETRY_INC_MS;
}
USB_debug("OHCI port %d - port reset failed!\n", port + 1);
USB_debug("OHCI port %d - port reset failed!\n", port+1);
return USBH_ERR_PORT_RESET;
port_reset_done:
......@@ -871,7 +867,7 @@ static int ohci_rh_polling(void)
UDEV_T *udev;
int ret;
for (i = 0; i < OHCI_PORT_CNT; i++)
for (i = 0; i < 1; i++)
{
/* clear unwanted port change status */
_ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_OCIC_Msk | USBH_HcRhPortStatus_PRSC_Msk |
......@@ -1183,8 +1179,8 @@ void OHCI_IRQHandler(int vector, void *param)
/*
* reverse done list
*/
td = (TD_T *)(_hcca->done_head & TD_ADDR_MASK);
_hcca->done_head = 0;
td = (TD_T *)(_hcca.done_head & TD_ADDR_MASK);
_hcca.done_head = 0;
td_prev = NULL;
_ohci->HcInterruptStatus = USBH_HcInterruptStatus_WDH_Msk;
......@@ -1232,7 +1228,7 @@ static void dump_ohci_int_table()
{
USB_debug("%02d: ", i);
ed = (ED_T *)_hcca->int_table[i];
ed = (ED_T *)_hcca.int_table[i];
while (ed != NULL)
{
......@@ -1268,12 +1264,14 @@ static void dump_ohci_regs()
USB_debug(" HcRhDescriptorB = 0x%x\n", _ohci->HcRhDescriptorB);
USB_debug(" HcRhStatus = 0x%x\n", _ohci->HcRhStatus);
USB_debug(" HcRhPortStatus0 = 0x%x\n", _ohci->HcRhPortStatus[0]);
USB_debug(" HcRhPortStatus1 = 0x%x\n", _ohci->HcRhPortStatus[1]);
USB_debug(" HcPhyControl = 0x%x\n", _ohci->HcPhyControl);
USB_debug(" HcMiscControl = 0x%x\n", _ohci->HcMiscControl);
}
static void dump_ohci_ports()
{
USB_debug("_ohci port0=0x%x\n", _ohci->HcRhPortStatus[0]);
USB_debug("_ohci port0=0x%x, port1=0x%x\n", _ohci->HcRhPortStatus[0], _ohci->HcRhPortStatus[1]);
}
#endif // ENABLE_DEBUG_MSG
......
bsp/nuvoton/libraries/ma35/UsbHostLib/src/mem_alloc.c
浏览文件 @ 0d1c709f
......@@ -25,14 +25,7 @@
#define mem_debug(...)
#endif
#ifdef __ICCARM__
#pragma data_alignment=1024
uint8_t _mem_pool_buff[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE];
#else
uint8_t _mem_pool_buff[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE] __attribute__((aligned(1024)));
#endif
static uint8_t *_mem_pool[MEM_POOL_UNIT_NUM];
static uint8_t _mem_pool[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE] __attribute__((section(".usbhostlib._mem_pool"))) __attribute__((aligned(32)));
static uint8_t _unit_used[MEM_POOL_UNIT_NUM];
static volatile int _usbh_mem_used;
......@@ -42,7 +35,7 @@ static volatile int _mem_pool_used;
UDEV_T *g_udev_list;
uint8_t _dev_addr_pool[128];
uint8_t _dev_addr_pool[128] __attribute__((section(".usbhostlib._dev_addr_pool")));
static volatile int _device_addr;
static int _sidx = 0;;
......@@ -53,8 +46,6 @@ static int _sidx = 0;;
void usbh_memory_init(void)
{
int i;
if (sizeof(TD_T) > MEM_POOL_UNIT_SIZE)
{
USB_error("TD_T - MEM_POOL_UNIT_SIZE too small!\n");
......@@ -67,15 +58,10 @@ void usbh_memory_init(void)
while (1);
}
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
_unit_used[i] = 0;
_mem_pool[i] = (uint8_t *)((uint32_t)&_mem_pool_buff[i] | NON_CACHE_MASK);
}
_usbh_mem_used = 0L;
_usbh_max_mem_used = 0L;
memset(_unit_used, 0, sizeof(_unit_used));
_mem_pool_used = 0;
_sidx = 0;
......@@ -93,9 +79,13 @@ uint32_t usbh_memory_used(void)
return _usbh_mem_used;
}
static void memory_counter(int size)
static void memory_counter(int inc, int size)
{
_usbh_mem_used += size;
if (inc)
_usbh_mem_used += size;
else
_usbh_mem_used -= size;
if (_usbh_mem_used > _usbh_max_mem_used)
_usbh_max_mem_used = _usbh_mem_used;
}
......@@ -104,7 +94,7 @@ void *usbh_alloc_mem(int size)
{
void *p;
p = USB_malloc(size, 16);
p = USB_malloc(size, 4);
if (p == NULL)
{
USB_error("usbh_alloc_mem failed! %d\n", size);
......@@ -112,14 +102,14 @@ void *usbh_alloc_mem(int size)
}
memset(p, 0, size);
memory_counter(size);
memory_counter(1, size);
return p;
}
void usbh_free_mem(void *p, int size)
{
USB_free(p);
memory_counter(0 - size);
memory_counter(0, size);
}
......@@ -131,15 +121,14 @@ UDEV_T *alloc_device(void)
{
UDEV_T *udev;
udev = (UDEV_T *)USB_malloc(sizeof(*udev), 16);
udev = (UDEV_T *)USB_malloc(sizeof(*udev), 4);
if (udev == NULL)
{
USB_error("alloc_device failed!\n");
return NULL;
}
memset(udev, 0, sizeof(*udev));
memory_counter(sizeof(*udev));
memory_counter(1, sizeof(*udev));
udev->cur_conf = -1; /* must! used to identify the first SET CONFIGURATION */
udev->next = g_udev_list; /* chain to global device list */
g_udev_list = udev;
......@@ -177,7 +166,7 @@ void free_device(UDEV_T *udev)
}
}
USB_free(udev);
memory_counter(-sizeof(*udev));
memory_counter(0, sizeof(*udev));
}
int alloc_dev_address(void)
......@@ -212,39 +201,19 @@ void free_dev_address(int dev_addr)
UTR_T *alloc_utr(UDEV_T *udev)
{
#if 0
UTR_T *utr, *utr_noncache;
utr = (UTR_T *)USB_malloc(sizeof(*utr), 16);
if (utr == NULL)
{
USB_error("alloc_utr failed!\n");
return NULL;
}
utr_noncache = (UTR_T *)((uint32_t)utr | NONCACHEABLE);
memory_counter(sizeof(*utr));
memset(utr_noncache, 0, sizeof(*utr));
utr_noncache->udev = udev;
mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr_noncache);
return utr_noncache;
#else
UTR_T *utr;
utr = (UTR_T *)USB_malloc(sizeof(*utr), 16);
utr = (UTR_T *)USB_malloc(sizeof(*utr), 4);
if (utr == NULL)
{
USB_error("alloc_utr failed!\n");
return NULL;
}
memory_counter(sizeof(*utr));
memory_counter(1, sizeof(*utr));
memset(utr, 0, sizeof(*utr));
utr->udev = udev;
mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr_noncache);
mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr);
return utr;
#endif
}
void free_utr(UTR_T *utr)
......@@ -253,14 +222,8 @@ void free_utr(UTR_T *utr)
return;
mem_debug("[FREE] [UTR] - 0x%x\n", (int)utr);
#if 0
if ((uint32_t)utr & NONCACHEABLE)
utr = (UTR_T *)((uint32_t)utr & ~NONCACHEABLE);
#endif
USB_free(utr);
memory_counter(0 - (int)sizeof(*utr));
memory_counter(0, (int)sizeof(*utr));
}
/*--------------------------------------------------------------------------*/
......@@ -278,7 +241,7 @@ ED_T *alloc_ohci_ED(void)
{
_unit_used[i] = 1;
_mem_pool_used++;
ed = (ED_T *)_mem_pool[i];
ed = (ED_T *)&_mem_pool[i];
memset(ed, 0, sizeof(*ed));
mem_debug("[ALLOC] [ED] - 0x%x\n", (int)ed);
return ed;
......@@ -294,7 +257,7 @@ void free_ohci_ED(ED_T *ed)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)ed)
if ((uint32_t)&_mem_pool[i] == (uint32_t)ed)
{
mem_debug("[FREE] [ED] - 0x%x\n", (int)ed);
_unit_used[i] = 0;
......@@ -319,7 +282,7 @@ TD_T *alloc_ohci_TD(UTR_T *utr)
{
_unit_used[i] = 1;
_mem_pool_used++;
td = (TD_T *)_mem_pool[i];
td = (TD_T *)&_mem_pool[i];
memset(td, 0, sizeof(*td));
td->utr = utr;
......@@ -337,7 +300,7 @@ void free_ohci_TD(TD_T *td)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)td)
if ((uint32_t)&_mem_pool[i] == (uint32_t)td)
{
mem_debug("[FREE] [TD] - 0x%x\n", (int)td);
_unit_used[i] = 0;
......@@ -363,7 +326,7 @@ QH_T *alloc_ehci_QH(void)
_unit_used[i] = 1;
_sidx = i;
_mem_pool_used++;
qh = (QH_T *)_mem_pool[i];
qh = (QH_T *)&_mem_pool[i];
memset(qh, 0, sizeof(*qh));
mem_debug("[ALLOC] [QH] - 0x%x\n", (int)qh);
break;
......@@ -387,7 +350,7 @@ void free_ehci_QH(QH_T *qh)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)qh)
if ((uint32_t)&_mem_pool[i] == (uint32_t)qh)
{
mem_debug("[FREE] [QH] - 0x%x\n", (int)qh);
_unit_used[i] = 0;
......@@ -413,7 +376,7 @@ qTD_T *alloc_ehci_qTD(UTR_T *utr)
_unit_used[i] = 1;
_sidx = i;
_mem_pool_used++;
qtd = (qTD_T *)_mem_pool[i];
qtd = (qTD_T *)&_mem_pool[i];
memset(qtd, 0, sizeof(*qtd));
qtd->Next_qTD = QTD_LIST_END;
......@@ -434,7 +397,7 @@ void free_ehci_qTD(qTD_T *qtd)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)qtd)
if ((uint32_t)&_mem_pool[i] == (uint32_t)qtd)
{
mem_debug("[FREE] [qTD] - 0x%x\n", (int)qtd);
_unit_used[i] = 0;
......@@ -463,7 +426,7 @@ iTD_T *alloc_ehci_iTD(void)
_unit_used[i] = _unit_used[i + 1] = 1;
_sidx = i + 1;
_mem_pool_used += 2;
itd = (iTD_T *)_mem_pool[i];
itd = (iTD_T *)&_mem_pool[i];
memset(itd, 0, sizeof(*itd));
mem_debug("[ALLOC] [iTD] - 0x%x\n", (int)itd);
return itd;
......@@ -479,7 +442,7 @@ void free_ehci_iTD(iTD_T *itd)
for (i = 0; i + 1 < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)itd)
if ((uint32_t)&_mem_pool[i] == (uint32_t)itd)
{
mem_debug("[FREE] [iTD] - 0x%x\n", (int)itd);
_unit_used[i] = _unit_used[i + 1] = 0;
......@@ -505,7 +468,7 @@ siTD_T *alloc_ehci_siTD(void)
_unit_used[i] = 1;
_sidx = i;
_mem_pool_used ++;
sitd = (siTD_T *)_mem_pool[i];
sitd = (siTD_T *)&_mem_pool[i];
memset(sitd, 0, sizeof(*sitd));
mem_debug("[ALLOC] [siTD] - 0x%x\n", (int)sitd);
return sitd;
......@@ -521,7 +484,7 @@ void free_ehci_siTD(siTD_T *sitd)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)sitd)
if ((uint32_t)&_mem_pool[i] == (uint32_t)sitd)
{
mem_debug("[FREE] [siTD] - 0x%x\n", (int)sitd);
_unit_used[i] = 0;
......
bsp/nuvoton/libraries/ma35/UsbHostLib/src/support.c
浏览文件 @ 0d1c709f
......@@ -39,8 +39,7 @@ typedef struct USB_mhdr
uint32_t reserved;
} USB_MHDR_T;
uint8_t _USBMemoryPool[USB_MEMORY_POOL_SIZE] __attribute__((aligned(USB_MEM_BLOCK_SIZE)));
uint8_t _USBMemoryPool[USB_MEMORY_POOL_SIZE] __attribute__((section(".usbhostlib.USBMemoryPool"))) __attribute__((aligned(USB_MEM_BLOCK_SIZE)));
static USB_MHDR_T *_pCurrent;
uint32_t *_USB_pCurrent = (uint32_t *) &_pCurrent;
......@@ -50,7 +49,7 @@ static uint32_t _MemoryPoolBase, _MemoryPoolEnd;
void USB_InitializeMemoryPool()
{
_MemoryPoolBase = (uint32_t)&_USBMemoryPool[0] | NON_CACHE_MASK;
_MemoryPoolBase = (uint32_t)&_USBMemoryPool[0];
_MemoryPoolEnd = _MemoryPoolBase + USB_MEMORY_POOL_SIZE;
_FreeMemorySize = _MemoryPoolEnd - _MemoryPoolBase;
_AllocatedMemorySize = 0;
......
bsp/nuvoton/libraries/ma35/UsbHostLib/src/usb_core.c
浏览文件 @ 0d1c709f
......@@ -103,6 +103,7 @@ int usbh_polling_root_hubs(void)
int ret, change = 0;
#ifdef ENABLE_EHCI0
//_ehci0->UPSCR[1] = HSUSBH_UPSCR_PP_Msk | HSUSBH_UPSCR_PO_Msk; /* set port 2 owner to OHCI */
do
{
ret = ehci0_driver.rthub_polling();
......@@ -114,6 +115,7 @@ int usbh_polling_root_hubs(void)
#endif
#ifdef ENABLE_EHCI1
//_ehci1->UPSCR[1] = HSUSBH_UPSCR_PP_Msk | HSUSBH_UPSCR_PO_Msk; /* set port 2 owner to OHCI */
do
{
ret = ehci1_driver.rthub_polling();
......
bsp/nuvoton/libraries/ma35/rtt_port/Kconfig
浏览文件 @ 0d1c709f
......@@ -5,6 +5,32 @@
select RT_USING_USER_MAIN
default y
config BSP_USING_SSPCC
bool
depends on SOC_SERIES_MA35D1 && !USE_MA35D1_SUBM
default y
config BSP_USING_SSMCC
bool
depends on SOC_SERIES_MA35D1 && !USE_MA35D1_SUBM
default y
config BSP_USING_UMCTL2
bool
depends on SOC_SERIES_MA35D1 && !USE_MA35D1_SUBM
default y
config BSP_USING_RTP
bool
depends on SOC_SERIES_MA35D1 && !USE_MA35D1_SUBM
default y
if BSP_USING_RTP
config RTP_USING_AT_STARTUP
bool "Enable RTP Executation at startup"
default y
endif
config USE_MA35D1_AARCH32
bool
select ARCH_ARM_CORTEX_A
......@@ -17,6 +43,15 @@
bool
select ARCH_ARMV8
if USE_MA35D1_AARCH64
config BSP_USING_GIC
bool
default y
config BSP_USING_GICV2
bool
default y
endif
config USE_MA35D1_SUBM
bool
select ARCH_ARM_CORTEX_M4
......@@ -1098,6 +1133,36 @@
default n
endif
config BSP_USING_HWSEM
bool "Enable Hardware semaphore(HWSEM)"
default y
if BSP_USING_HWSEM
config BSP_USING_HWSEM0
bool "Enable HWSEM0"
default y
endif
config BSP_USING_WHC
bool "Enable Wormhole(WHC)"
default y
if BSP_USING_WHC
config BSP_USING_WHC0
bool "Enable WHC0"
default y
config BSP_USING_WHC1
bool "Enable WHC1"
depends on !USE_MA35D1_SUBM
default n
endif
config BSP_USING_NFI
bool "Enable Raw NAND flash Interface(NFI)"
depends on !USE_MA35D1_SUBM
default y
config BSP_USING_EBI
bool "Enable External Bus Interface(EBI)"
default n
......
bsp/nuvoton/libraries/ma35/rtt_port/drv_common.h
浏览文件 @ 0d1c709f
......@@ -21,7 +21,9 @@
#include "gic.h"
#include "mmu.h"
#include "cp15.h"
#if defined(USE_MA35D1_AARCH32)
#include "cp15.h"
#endif
#include "gtimer.h"
#define __REG32(x) (*((volatile unsigned int*)((rt_ubase_t)x)))
......@@ -35,21 +37,6 @@
#define DDR_LIMIT_SIZE 0xC0000000u
#define UNCACHEABLE 0x40000000u
#define SSPCC_SET_REALM(IP, REALM) \
do { \
rt_kprintf("Set %s realm to %s(%d)\n", #IP, #REALM, REALM); \
SSPCC_SetRealm(IP, REALM); \
rt_kprintf("Get %s realm is %d ....%s\n", #IP, SSPCC_GetRealm(IP), (SSPCC_GetRealm(IP)==REALM)?"Success":"Failure"); \
} while(0)
#define SSPCC_SET_GPIO_REALM(PORT, PIN, REALM) \
do { \
rt_kprintf("Set %s%s realm to %s(%d)\n", #PORT, #PIN, #REALM, REALM); \
SSPCC_SetRealm_GPIO((uint32_t)PORT, PIN, REALM); \
rt_kprintf("Get %s%s realm is %d ....%s\n", #PORT, #PIN, SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN), (SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN)==REALM)?"Success":"Failure"); \
} while(0)
/* the basic constants needed by gic */
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
{
......@@ -72,12 +59,16 @@ rt_inline rt_uint32_t nu_cpu_dcache_line_size(void)
return 4 << ((ctr >> 16) & 0xF);
}
extern void rt_hw_cpu_dcache_clean(void *addr, int size);
extern void rt_hw_cpu_dcache_clean_inv(void *addr, int size);
extern void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size);
extern void rt_hw_cpu_dcache_invalidate(void *addr, int size);
#else
#define UNCACHEABLE 0
#endif
void nu_clock_init(void);
#define REGION_ADDR_SRAM0 0x24000000
#define REGION_ADDR_DDR (0x80020000|UNCACHEABLE)
#define REGION_MAXSIZE_SRAM0 (128*1024)
#define REGION_MAXSIZE_DDR (4*1024*1024-REGION_MAXSIZE_SRAM0)
#define REGION_MAXSIZE_LIMIT (REGION_MAXSIZE_SRAM0+REGION_MAXSIZE_DDR)
#endif /* __DRV_COMMON_H__ */
bsp/nuvoton/libraries/ma35/rtt_port/drv_common.c → bsp/nuvoton/libraries/ma35/rtt_port/drv_common_aarch32.c
浏览文件 @ 0d1c709f
......@@ -11,21 +11,25 @@
******************************************************************************/
#include <rtthread.h>
#if defined(USE_MA35D1_AARCH32)
#include <rthw.h>
#include <stdio.h>
#include "drv_common.h"
#include "board.h"
#include "drv_uart.h"
#include "drv_sspcc.h"
#include "drv_ssmcc.h"
#include "drv_umctl2.h"
#define LOG_TAG "drv.common"
#undef DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_LEVEL LOG_LVL_INFO
#define DBG_COLOR
#include <rtdbg.h>
#if defined(USE_MA35D1_AARCH32)
#define NORMAL_MEM_UNCACHED (SHARED|AP_RW|DOMAIN0|STRONGORDER|DESC_SEC)
/*
......@@ -46,26 +50,23 @@ struct mem_desc platform_mem_desc[] =
{0xC0000000, 0xFFFFFFFF, 0x80000000, NORMAL_MEM_UNCACHED} // 1GB DDR, non-cacheable
};
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
#endif
/**
* This function will initialize board
*/
static void nu_mmu_initialize(void)
{
#if defined(USE_MA35D1_AARCH64)
mmu_init();
/* device memory 0x0000_0000 - 0x3FFF_FFFF */
armv8_map(0x00000000, 0x00000000, 0x40000000, MEM_ATTR_IO);
/* device memory 0x4000_0000 - 0x7FFF_FFFF */
armv8_map(0x40000000, 0x40000000, 0x40000000, MEM_ATTR_IO);
/* system memory 0x8000_0000 - 0xFFFF_FFFF */
armv8_map(0x80000000, 0x80000000, 0x80000000, MEM_ATTR_MEMORY);
mmu_enable();
#endif
}
rt_mmu_info mmu_info;
extern size_t MMUTable[];
#if !defined(USE_MA35D1_SUBM)
extern void nu_clock_dump(void);
extern void nu_clock_raise(void);
extern void nu_clock_init(void);
extern void nu_chipcfg_dump(void);
extern uint32_t nu_chipcfg_ddrsize(void);
volatile uint32_t secondary_cpu_entry __attribute__((aligned(32))) = 0;
static rt_uint32_t timerStep;
void rt_hw_systick_isr(int vector, void *parameter)
{
gtimer_set_load_value(timerStep);
......@@ -83,42 +84,6 @@ int rt_hw_systick_init(void)
return 0;
}
void nu_sspcc_init(void)
{
int i, j;
CLK->APBCLK2 |= CLK_APBCLK2_SSPCCEN_Msk;
/* Set all GPIO security set to TZNS. */
for (i = 0; i < 16; i++)
{
for (j = 0; j < 14; j++)
{
SSPCC_SetRealm_GPIO(GPIO_BASE + (j * 0x40), i, SSPCC_SSET_TZNS);
}
}
}
void nu_ssmcc_init(void)
{
CLK->APBCLK2 |= CLK_APBCLK2_SSMCCEN_Msk;
/* set region 0 to secure region, non-secure and m4 all can access */
SSMCC_SetRegion0(SSMCC_SECURE_READ | SSMCC_SECURE_WRITE | SSMCC_NONSECURE_READ | SSMCC_NONSECURE_WRITE | SSMCC_M4NS_READ | SSMCC_M4NS_WRITE);
}
void nu_ddr_init(void)
{
UMCTL2->PCTRL_0 = UMCTL2_PCTRL_0_port_en_Msk; //[0x0490]
UMCTL2->PCTRL_1 = UMCTL2_PCTRL_1_port_en_Msk; //[0x0540]
UMCTL2->PCTRL_2 = UMCTL2_PCTRL_2_port_en_Msk; //[0x05f0]
UMCTL2->PCTRL_3 = UMCTL2_PCTRL_3_port_en_Msk; //[0x06a0]
UMCTL2->PCTRL_4 = UMCTL2_PCTRL_4_port_en_Msk; //[0x0750]
UMCTL2->PCTRL_5 = UMCTL2_PCTRL_5_port_en_Msk; //[0x0800]
UMCTL2->PCTRL_6 = UMCTL2_PCTRL_6_port_en_Msk; //[0x08b0]
UMCTL2->PCTRL_7 = UMCTL2_PCTRL_7_port_en_Msk; //[0x0960]
}
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
......@@ -156,154 +121,13 @@ void rt_hw_us_delay(rt_uint32_t us)
}
} /* rt_hw_us_delay */
#else
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
int rt_hw_systick_init(void)
{
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/* Configure SysTick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
return 0;
}
/**
* The time delay function.
*
* @param microseconds.
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
#endif
void devmem(int argc, char *argv[])
{
volatile unsigned int u32Addr;
unsigned int value = 0, mode = 0;
if (argc < 2 || argc > 3)
{
goto exit_devmem;
}
if (argc == 3)
{
if (sscanf(argv[2], "0x%x", &value) != 1)
goto exit_devmem;
mode = 1; //Write
}
if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
goto exit_devmem;
else if (u32Addr & (4 - 1))
goto exit_devmem;
if (mode)
{
*((volatile uint32_t *)u32Addr) = value;
}
rt_kprintf("0x%08x\n", *((volatile uint32_t *)u32Addr));
return;
exit_devmem:
rt_kprintf("Read: devmem <physical address in hex>\n");
rt_kprintf("Write: devmem <physical address in hex> <value in hex format>\n");
return;
}
MSH_CMD_EXPORT(devmem, dump device registers);
void devmem2(int argc, char *argv[])
{
volatile unsigned int u32Addr;
unsigned int value = 0, word_count = 1;
if (argc < 2 || argc > 3)
{
goto exit_devmem;
}
if (argc == 3)
{
if (sscanf(argv[2], "%d", &value) != 1)
goto exit_devmem;
word_count = value;
}
if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
goto exit_devmem;
else if (u32Addr & (4 - 1))
goto exit_devmem;
if (word_count > 0)
{
LOG_HEX("devmem", 16, (void *)u32Addr, word_count * sizeof(rt_base_t));
}
return;
exit_devmem:
rt_kprintf("devmem2: <physical address in hex> <count in dec>\n");
return;
}
MSH_CMD_EXPORT(devmem2, dump device registers);
void idle_wfi(void)
{
#if defined(USE_MA35D1_SUBM)
__WFI();
#else
asm volatile("wfi");
#endif
}
extern void nu_clock_dump(void);
extern void nu_clock_raise(void);
rt_weak void nutool_pincfg_init(void)
{
}
/**
......@@ -311,10 +135,11 @@ rt_weak void nutool_pincfg_init(void)
*/
rt_weak void rt_hw_board_init(void)
{
uint32_t u32BoardHeapEnd;
/* Unlock protected registers */
SYS_UnlockReg();
#if !defined(USE_MA35D1_SUBM)
/* initialize SSPCC */
nu_sspcc_init();
......@@ -322,25 +147,32 @@ rt_weak void rt_hw_board_init(void)
nu_ssmcc_init();
/* initialize UMCTL2 */
nu_ddr_init();
#endif
nu_umctl2_init();
/* initialize base clock */
nu_clock_init();
/* initialize peripheral pin function */
nutool_pincfg_init();
rt_hw_mmu_map_init(&mmu_info, (void*)0x80000000, 0x10000000, MMUTable, 0);
rt_hw_mmu_ioremap_init(&mmu_info, (void*)0x80000000, 0x10000000);
/* initialize hardware interrupt */
rt_hw_interrupt_init();
/* initialize MMU */
nu_mmu_initialize();
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)BOARD_HEAP_START, (void *)BOARD_HEAP_END);
if (nu_chipcfg_ddrsize() > 0)
{
/* Get MCP DDR capacity in run-time. */
u32BoardHeapEnd = 0x80000000 + nu_chipcfg_ddrsize();
}
else
{
/* Use board.h definition */
u32BoardHeapEnd = (uint32_t)BOARD_HEAP_END;
}
rt_system_heap_init((void *)BOARD_HEAP_START, (void *)u32BoardHeapEnd);
#endif
/* initialize uart */
......@@ -350,18 +182,7 @@ rt_weak void rt_hw_board_init(void)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#if !defined(USE_MA35D1_SUBM)
#if !defined(USE_MA35D1_AARCH64)
//TOFIX
nu_clock_raise();
#endif
nu_clock_dump();
#endif
#if defined(RT_USING_HEAP)
/* Dump heap information */
rt_kprintf("Heap: Begin@%08x, END@%08x, SIZE: %d KiB\n", BOARD_HEAP_START, BOARD_HEAP_END, ((rt_uint32_t)BOARD_HEAP_END - (rt_uint32_t)BOARD_HEAP_START) / 1024);
#endif
/* initialize systick */
rt_hw_systick_init();
......@@ -371,22 +192,29 @@ rt_weak void rt_hw_board_init(void)
rt_components_board_init();
#endif
#if defined(RT_USING_HEAP)
/* Dump heap information */
LOG_I("Heap: Begin@%08x, END@%08x, SIZE: %d MB", BOARD_HEAP_START, u32BoardHeapEnd, ((rt_uint32_t)u32BoardHeapEnd - (rt_uint32_t)BOARD_HEAP_START) / 1024 / 1024);
#endif
nu_chipcfg_dump();
nu_clock_dump();
#if defined(RT_USING_SMP)
/* install IPI handle */
rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
#endif
}
#if defined(RT_USING_SMP)
extern void secondary_cpu_start(void);
extern void rt_secondary_cpu_entry(void);
void set_secondary_cpu_boot_address(void)
{
secondary_cpu_entry = (uint32_t)&secondary_cpu_start;
rt_kprintf("Wake up cpu-1 goto -> 0x%08x\n", secondary_cpu_entry);
secondary_cpu_entry = (uint32_t)&rt_secondary_cpu_entry;
rt_kprintf("Wake up cpu-1 goto -> 0x%08x@0x%08x\n", secondary_cpu_entry, &secondary_cpu_entry);
}
void rt_hw_secondary_cpu_up(void)
......@@ -414,7 +242,7 @@ void rt_hw_secondary_cpu_up(void)
}
}
void secondary_cpu_c_start(void)
void rt_hw_secondary_cpu_bsp_start(void)
{
rt_kprintf("[%s] cpu-%d\r\n", __func__, rt_hw_cpu_id());
......@@ -435,3 +263,5 @@ void rt_hw_secondary_cpu_idle_exec(void)
}
#endif
#endif /* #if defined(USE_MA35D1_AARCH32) */
bsp/nuvoton/libraries/ma35/rtt_port/drv_common_subm.c 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-14 Wayne First version
*
******************************************************************************/
#include <rtthread.h>
#if defined(USE_MA35D1_SUBM)
#include <rthw.h>
#include <stdio.h>
#include "drv_common.h"
#include "board.h"
#include "drv_uart.h"
#define LOG_TAG "drv.common"
#undef DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_COLOR
#include <rtdbg.h>
extern void nu_clock_init(void);
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
int rt_hw_systick_init(void)
{
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/* Configure SysTick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
return 0;
}
/**
* The time delay function.
*
* @param microseconds.
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
void idle_wfi(void)
{
__WFI();
}
rt_weak void nutool_pincfg_init(void)
{
}
/**
* This function will initial board.
*/
rt_weak void rt_hw_board_init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* initialize base clock */
nu_clock_init();
/* initialize peripheral pin function */
nutool_pincfg_init();
/* initialize hardware interrupt */
rt_hw_interrupt_init();
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)BOARD_HEAP_START, (void *)BOARD_HEAP_END);
#endif
/* initialize uart */
rt_hw_uart_init();
#if defined(RT_USING_CONSOLE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#if defined(RT_USING_HEAP)
/* Dump heap information */
rt_kprintf("Heap: Begin@%08x, END@%08x, SIZE: %d KiB\n", BOARD_HEAP_START, BOARD_HEAP_END, ((rt_uint32_t)BOARD_HEAP_END - (rt_uint32_t)BOARD_HEAP_START) / 1024);
#endif
/* initialize systick */
rt_hw_systick_init();
rt_thread_idle_sethook(idle_wfi);
#if defined(RT_USING_COMPONENTS_INIT)
rt_components_board_init();
#endif
}
#endif
bsp/nuvoton/libraries/ma35/rtt_port/drv_disp.c
浏览文件 @ 0d1c709f
......@@ -53,6 +53,10 @@ typedef struct nu_disp *nu_disp_t;
static volatile uint32_t g_u32VSyncBlank = 0;
static struct rt_completion vsync_wq;
#if defined(DISP_USING_OVERLAY)
static rt_mutex_t disp_lock;
#endif
static struct nu_disp nu_fbdev[eLayer_Cnt] =
{
{
......@@ -69,9 +73,9 @@ static struct nu_disp nu_fbdev[eLayer_Cnt] =
#endif
};
rt_weak void nu_lcd_backlight_on(void) { }
RT_WEAK void nu_lcd_backlight_on(void) { }
rt_weak void nu_lcd_backlight_off(void) { }
RT_WEAK void nu_lcd_backlight_off(void) { }
static void nu_disp_isr(int vector, void *param)
{
......@@ -88,6 +92,10 @@ static rt_err_t disp_layer_open(rt_device_t dev, rt_uint16_t oflag)
nu_disp_t psDisp = (nu_disp_t)dev;
RT_ASSERT(psDisp != RT_NULL);
#if defined(DISP_USING_OVERLAY)
rt_mutex_take(disp_lock, RT_WAITING_FOREVER);
#endif
psDisp->ref_count++;
#if defined(DISP_USING_OVERLAY)
......@@ -112,6 +120,10 @@ static rt_err_t disp_layer_open(rt_device_t dev, rt_uint16_t oflag)
}
#endif
#if defined(DISP_USING_OVERLAY)
rt_mutex_release(disp_lock);
#endif
return RT_EOK;
}
......@@ -120,6 +132,10 @@ static rt_err_t disp_layer_close(rt_device_t dev)
nu_disp_t psDisp = (nu_disp_t)dev;
RT_ASSERT(psDisp != RT_NULL);
#if defined(DISP_USING_OVERLAY)
rt_mutex_take(disp_lock, RT_WAITING_FOREVER);
#endif
psDisp->ref_count--;
#if defined(DISP_USING_OVERLAY)
......@@ -140,6 +156,10 @@ static rt_err_t disp_layer_close(rt_device_t dev)
DISP_Trigger(eLayer_Video, 0);
}
#if defined(DISP_USING_OVERLAY)
rt_mutex_release(disp_lock);
#endif
return RT_EOK;
}
......@@ -208,8 +228,6 @@ static rt_err_t disp_layer_control(rt_device_t dev, int cmd, void *args)
/* Initial LCD */
DISP_SetFBFmt(psDisp->layer, eFBFmt, psDisp->info.pitch);
}
break;
......@@ -243,7 +261,7 @@ static rt_err_t disp_layer_control(rt_device_t dev, int cmd, void *args)
if (psDisp->last_commit >= g_u32VSyncBlank)
{
rt_completion_init(&vsync_wq);
rt_completion_wait(&vsync_wq, RT_TICK_PER_SECOND / 60);
rt_completion_wait(&vsync_wq, RT_TICK_PER_SECOND / DISP_LCDTIMING_GetFPS(RT_NULL));
}
}
break;
......@@ -331,12 +349,20 @@ int rt_hw_disp_init(void)
rt_kprintf("%s's fbdev video memory at 0x%08x.\n", psDisp->name, psDisp->info.framebuffer);
}
#if defined(DISP_USING_OVERLAY)
/* Initial display lock */
disp_lock = rt_mutex_create("displock", RT_IPC_FLAG_FIFO);
RT_ASSERT(disp_lock);
#endif
/* Register ISR */
rt_hw_interrupt_install(DISP_IRQn, nu_disp_isr, RT_NULL, "DISP");
/* Enable interrupt. */
rt_hw_interrupt_umask(DISP_IRQn);
rt_kprintf("LCD panel timing is %d FPS.\n", DISP_LCDTIMING_GetFPS(&psDispLcdInstance->sLcdTiming));
return (int)ret;
}
INIT_DEVICE_EXPORT(rt_hw_disp_init);
......
bsp/nuvoton/libraries/ma35/rtt_port/drv_hwsem.c 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-5 Wayne First version
*
******************************************************************************/
#include <rtconfig.h>
#if defined(BSP_USING_HWSEM)
#include <rthw.h>
#include "drv_hwsem.h"
#include "drv_sys.h"
#include "drv_common.h"
#include "nu_bitutil.h"
/* Private define ---------------------------------------------------------------*/
enum
{
HWSEM_START = -1,
#if defined(BSP_USING_HWSEM0)
HWSEM0_IDX,
#endif
HWSEM_END
};
/* Private typedef --------------------------------------------------------------*/
struct nu_mutex_priv
{
struct nu_mutex parent;
rt_thread_t owner;
uint8_t key;
uint8_t hold;
struct rt_completion completion;
void *user_data;
};
typedef struct nu_mutex_priv *nu_mutex_priv_t;
struct nu_hwsem
{
struct rt_device dev;
char *name;
HWSEM_T *base;
IRQn_Type irqn;
uint32_t rstidx;
struct nu_mutex_priv mutex[evHWSEM_CNT];
};
typedef struct nu_hwsem *nu_hwsem_t;
static struct nu_hwsem nu_hwsem_arr [] =
{
#if defined(BSP_USING_HWSEM0)
{
.name = "hwsem0",
.base = HWSEM0,
.irqn = HWSEM0_IRQn,
.rstidx = HWSEM0_RST,
},
#endif
}; /* nu_hwsem */
/**
* All HWSEM interrupt service routine
*/
static void nu_hwsem_isr(int vector, void *param)
{
nu_hwsem_t psNuHwSem = (nu_hwsem_t)param;
rt_int32_t irqidx;
volatile uint32_t vu32Intsts = psNuHwSem->base->INTSTS_CORE;
while ((irqidx = nu_ctz(vu32Intsts)) < evHWSEM_CNT)
{
nu_mutex_priv_t priv = (nu_mutex_priv_t)&psNuHwSem->mutex[irqidx];
uint32_t u32IsrBitMask = 1 << irqidx ;
HWSEM_CLR_INT_FLAG(psNuHwSem->base, irqidx);
/* Unlocked, Signal waiter. */
rt_completion_done(&priv->completion);
/* Clear sent bit */
vu32Intsts &= ~(u32IsrBitMask);
}
}
nu_mutex_t nu_mutex_init(struct rt_device *device, E_HWSEM_ID id)
{
if (id < evHWSEM_CNT)
{
nu_hwsem_t psNuHwSem = (nu_hwsem_t)device->user_data;
nu_mutex_t mutex = (nu_mutex_t)&psNuHwSem->mutex[id];
nu_mutex_priv_t priv = (nu_mutex_priv_t)mutex;
if (!priv->owner)
{
priv->owner = rt_thread_self();
}
else
{
goto exit_nu_mutex_init;
}
return mutex;
}
exit_nu_mutex_init:
return RT_NULL;
}
void nu_mutex_deinit(struct rt_device *device, E_HWSEM_ID id)
{
if (id < evHWSEM_CNT)
{
nu_hwsem_t psNuHwSem = (nu_hwsem_t)device->user_data;
nu_mutex_t mutex = (nu_mutex_t)&psNuHwSem->mutex[id];
nu_mutex_priv_t priv = (nu_mutex_priv_t)mutex;
if (priv->owner == rt_thread_self())
{
priv->owner = RT_NULL;
}
}
}
rt_err_t nu_mutex_take(nu_mutex_t mutex, rt_int32_t timeout)
{
rt_err_t ret = RT_EOK;
nu_mutex_priv_t priv = (nu_mutex_priv_t)mutex;
nu_hwsem_t dev = (nu_hwsem_t)priv->user_data;
uint8_t u8PrivKey = priv->key;
#ifdef RT_USING_SMP
u8PrivKey |= (rt_hw_cpu_id() << 6);
#endif /* RT_USING_SMP */
if (priv->owner != rt_thread_self())
{
return -RT_ERROR;
}
rt_completion_init(&priv->completion);
while (1)
{
if (HWSEM_IS_LOCKED(dev->base, mutex->id) != HWSEM_NOLOCK)
{
/* LOCKED */
if (HWSEM_GET_KEY(dev->base, mutex->id) != u8PrivKey)
{
/* Enable interrupt */
HWSEM_ENABLE_INT(dev->base, mutex->id);
/* owner is NOT me. */
if (rt_completion_wait(&priv->completion, timeout) != RT_EOK)
{
ret = -RT_EBUSY;
break;
}
else
{
/* Got notification, do lock. */
}
}
else
{
/* owner is me. */
priv->hold++;
break;
}
}
else
{
/* NOLOCK, To lock */
HWSEM_LOCK(dev->base, mutex->id, u8PrivKey);
if (HWSEM_GET_KEY(dev->base, mutex->id) == u8PrivKey)
{
/* owner is me. */
priv->hold = 1;
/* Disable interrupt */
HWSEM_DISABLE_INT(dev->base, mutex->id);
break;
}
else
{
/* Failed to lock, owner is not me. wait notification. */
}
}
} //while(1)
return ret;
}
RTM_EXPORT(nu_mutex_take);
rt_err_t nu_mutex_release(nu_mutex_t mutex)
{
rt_err_t ret = RT_EOK;
nu_mutex_priv_t priv = (nu_mutex_priv_t)mutex;
nu_hwsem_t dev = (nu_hwsem_t)priv->user_data;
uint8_t u8PrivKey = priv->key;
if (priv->owner != rt_thread_self())
{
return -RT_ERROR;
}
#ifdef RT_USING_SMP
u8PrivKey |= (rt_hw_cpu_id() << 6);
#endif /* RT_USING_SMP */
if (HWSEM_IS_LOCKED(dev->base, mutex->id) != 0 &&
HWSEM_GET_KEY(dev->base, mutex->id) == u8PrivKey)
{
priv->hold--;
if (priv->hold == 0)
{
/* Unlocked */
HWSEM_UNLOCK(dev->base, mutex->id, u8PrivKey);
}
}
else
{
ret = -RT_ERROR;
}
return ret;
}
RTM_EXPORT(nu_mutex_release);
static rt_err_t hwsem_register(struct rt_device *device, const char *name, void *user_data)
{
RT_ASSERT(device);
device->type = RT_Device_Class_Miscellaneous;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
device->ops = RT_NULL;
#else
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = RT_NULL;
#endif
device->user_data = user_data;
return rt_device_register(device, name, RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_STANDALONE);
}
/**
* Hardware Sem Initialization
*/
int rt_hw_hwsem_init(void)
{
int i, j;
rt_err_t ret = RT_EOK;
for (i = (HWSEM_START + 1); i < HWSEM_END; i++)
{
#if !defined(USE_MA35D1_SUBM)
/* Reset this module */
nu_sys_ip_reset(nu_hwsem_arr[i].rstidx);
#endif
for (j = 0; j < evHWSEM_CNT; j++)
{
nu_hwsem_arr[i].mutex[j].parent.id = (E_HWSEM_ID)j;
nu_hwsem_arr[i].mutex[j].user_data = (void *)&nu_hwsem_arr[i];
nu_hwsem_arr[i].mutex[j].key = (HWSEM_LOCK_BY_OWNER << 4) | j; // CoreID + SemID
nu_hwsem_arr[i].mutex[j].hold = 0;
nu_hwsem_arr[i].mutex[j].owner = RT_NULL;
if (HWSEM_IS_LOCKED(nu_hwsem_arr[i].base, j) == HWSEM_LOCK_BY_OWNER)
HWSEM_UNLOCK(nu_hwsem_arr[i].base, j, nu_hwsem_arr[i].mutex[j].key);
/* Disable interrupt */
HWSEM_DISABLE_INT(nu_hwsem_arr[i].base, j);
}
rt_hw_interrupt_install(nu_hwsem_arr[i].irqn, nu_hwsem_isr, &nu_hwsem_arr[i], nu_hwsem_arr[i].name);
rt_hw_interrupt_umask(nu_hwsem_arr[i].irqn);
ret = hwsem_register(&nu_hwsem_arr[i].dev, (const char *)nu_hwsem_arr[i].name, (void *)&nu_hwsem_arr[i]);
RT_ASSERT(ret == RT_EOK);
}
return 0;
}
INIT_BOARD_EXPORT(rt_hw_hwsem_init);
#endif //#if defined(BSP_USING_UART)
bsp/nuvoton/libraries/ma35/rtt_port/drv_hwsem.h 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-5 Wayne First version
*
******************************************************************************/
#ifndef __DRV_HWSEM_H__
#define __DRV_HWSEM_H__
#include <rtdevice.h>
typedef enum
{
evHWSEM0 = 0,
evHWSEM1,
evHWSEM2,
evHWSEM3,
evHWSEM4,
evHWSEM5,
evHWSEM6,
evHWSEM7,
evHWSEM_CNT,
} E_HWSEM_ID;
struct nu_mutex
{
E_HWSEM_ID id;
};
typedef struct nu_mutex *nu_mutex_t;
nu_mutex_t nu_mutex_init(struct rt_device *device, E_HWSEM_ID id);
rt_err_t nu_mutex_take(nu_mutex_t mutex, rt_int32_t timeout);
rt_err_t nu_mutex_release(nu_mutex_t mutex);
void nu_mutex_deinit(struct rt_device *device, E_HWSEM_ID id);
#endif /* __DRV_HWSEM_H__ */
bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.c
浏览文件 @ 0d1c709f
......@@ -328,22 +328,6 @@ static inline void nu_pdma_channel_reset(int i32ChannID)
while ((PDMA->CHCTL & (1 << u32ModChannId)));
}
void nu_pdma_channel_terminate(int i32ChannID)
{
if (nu_pdma_check_is_nonallocated(i32ChannID))
goto exit_pdma_channel_terminate;
/* Reset specified channel. */
nu_pdma_channel_reset(i32ChannID);
/* Enable specified channel after reset. */
nu_pdma_channel_enable(i32ChannID);
exit_pdma_channel_terminate:
return;
}
static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us)
{
rt_err_t ret = RT_EINVAL;
......@@ -396,6 +380,25 @@ exit_nu_pdma_timeout_set:
return -(ret);
}
void nu_pdma_channel_terminate(int i32ChannID)
{
if (nu_pdma_check_is_nonallocated(i32ChannID))
goto exit_pdma_channel_terminate;
/* Disable timeout function of specified channel. */
nu_pdma_timeout_set(i32ChannID, 0);
/* Reset specified channel. */
nu_pdma_channel_reset(i32ChannID);
/* Enable specified channel after reset. */
nu_pdma_channel_enable(i32ChannID);
exit_pdma_channel_terminate:
return;
}
int nu_pdma_channel_allocate(int32_t i32PeripType)
{
int ChnId, i32PeripCtlIdx, j;
......@@ -595,6 +598,22 @@ exit_nu_pdma_transferred_byte_get:
return -1;
}
nu_pdma_desc_t nu_pdma_get_channel_desc(int32_t i32ChannID)
{
PDMA_T *PDMA;
if (nu_pdma_check_is_nonallocated(i32ChannID))
goto exit_nu_pdma_get_srcaddr;
PDMA = NU_PDMA_GET_BASE(i32ChannID);
return &PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)];
exit_nu_pdma_get_srcaddr:
return RT_NULL;
}
nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID)
{
nu_pdma_memctrl_t eMemCtrl = eMemCtl_Undefined;
......@@ -727,31 +746,31 @@ exit_nu_pdma_desc_setup:
rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num)
{
int i;
nu_pdma_desc_t psSgTblHead;
RT_ASSERT(ppsSgtbls != NULL);
RT_ASSERT(num > 0);
psSgTblHead = (nu_pdma_desc_t) rt_malloc_align(RT_ALIGN(sizeof(DSCT_T) * num, 64), 64);
RT_ASSERT(psSgTblHead != RT_NULL);
rt_memset((void *)psSgTblHead, 0, sizeof(DSCT_T) * num);
for (i = 0; i < num; i++)
ppsSgtbls[i] = &psSgTblHead[i];
{
ppsSgtbls[i] = (nu_pdma_desc_t) rt_malloc_align(RT_ALIGN(sizeof(DSCT_T), 64), 64);
RT_ASSERT(ppsSgtbls[i] != RT_NULL);
rt_memset((void *)ppsSgtbls[i], 0, RT_ALIGN(sizeof(DSCT_T), 64));
}
return RT_EOK;
}
void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num)
{
nu_pdma_desc_t psSgTblHead;
int i;
RT_ASSERT(ppsSgtbls != NULL);
psSgTblHead = *ppsSgtbls;
RT_ASSERT(psSgTblHead != NULL);
RT_ASSERT(num > 0);
rt_free_align(psSgTblHead);
for (i = 0; i < num; i++)
{
rt_free_align(ppsSgtbls[i]);
}
}
static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us)
......@@ -781,18 +800,20 @@ static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_de
rt_kprintf("[%s] u32SrcCtl=0x%08x\n", __func__, u32SrcCtl);
rt_kprintf("[%s] u32DstCtl=0x%08x\n", __func__, u32DstCtl);
rt_kprintf("[%s] u32FlushLen=%d\n", __func__, u32FlushLen);
rt_kprintf("[%s] DA=%08x\n", __func__, next->DA);
rt_kprintf("[%s] SA=%08x\n", __func__, next->SA);
#endif
/* Flush Src buffer into memory. */
if ((u32SrcCtl == PDMA_SAR_INC)) // for M2P, M2M
rt_hw_cpu_dcache_clean_inv((void *)next->SA, u32FlushLen);
rt_hw_cpu_dcache_clean_and_invalidate((void *)next->SA, u32FlushLen);
/* Flush Dst buffer into memory. */
if ((u32DstCtl == PDMA_DAR_INC)) // for P2M, M2M
rt_hw_cpu_dcache_clean_inv((void *)next->DA, u32FlushLen);
rt_hw_cpu_dcache_clean_and_invalidate((void *)next->DA, u32FlushLen);
/* Flush descriptor into memory */
rt_hw_cpu_dcache_clean_inv((void *)next, sizeof(DSCT_T));
rt_hw_cpu_dcache_clean_and_invalidate((void *)next, sizeof(DSCT_T));
if (bNonCacheAlignedWarning)
{
......@@ -806,7 +827,7 @@ static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_de
Source, destination, DMA descriptor address and length should be aligned at len(CACHE_LINE_SIZE)
*/
bNonCacheAlignedWarning = 0;
rt_kprintf("[PDMA-W]\n");
//rt_kprintf("[PDMA-W]\n");
}
}
......@@ -817,19 +838,29 @@ static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_de
}
#endif
PDMA_DisableTimeout(PDMA, 1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
PDMA_EnableInt(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID), PDMA_INT_TRANS_DONE);
nu_pdma_desc_t psDesc = nu_pdma_get_channel_desc(i32ChannID);
nu_pdma_timeout_set(i32ChannID, u32IdleTimeout_us);
PDMA_DisableTimeout(PDMA, 1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
/* Set scatter-gather mode and head */
/* Take care the head structure, you should make sure cache-coherence. */
PDMA_SetTransferMode(PDMA,
NU_PDMA_GET_MOD_CHIDX(i32ChannID),
u32Peripheral,
(head->NEXT != 0) ? 1 : 0,
(uint32_t)head);
NU_PDMA_GET_MOD_CHIDX(i32ChannID),
u32Peripheral,
(head->NEXT != 0) ? 1 : 0,
(uint32_t)head);
/* PDMA fetchs description on-demand if SG enabled. We check it valid in here. */
if ( (u32Peripheral != PDMA_MEM) &&
(head->NEXT != 0) &&
(head->DA != psDesc->DA) )
{
RT_ASSERT(0);
}
PDMA_EnableInt(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID), PDMA_INT_TRANS_DONE);
nu_pdma_timeout_set(i32ChannID, u32IdleTimeout_us);
/* If peripheral is M2M, trigger it. */
if (u32Peripheral == PDMA_MEM)
......
bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.h
浏览文件 @ 0d1c709f
......@@ -73,6 +73,7 @@ rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl)
nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cbtype_t eCBType, nu_pdma_chn_cb_t psChnCb_Hijack);
rt_err_t nu_pdma_filtering_set(int i32ChannID, uint32_t u32EventFilter);
uint32_t nu_pdma_filtering_get(int i32ChannID);
nu_pdma_desc_t nu_pdma_get_channel_desc(int32_t i32ChannID);
// For scatter-gather DMA
rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t TransferCnt, nu_pdma_desc_t next, uint32_t u32BeSilent);
......
bsp/nuvoton/libraries/ma35/rtt_port/drv_qspi.c
浏览文件 @ 0d1c709f
......@@ -402,7 +402,7 @@ static int rt_hw_qspi_init(void)
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_qspi_init);
INIT_PREV_EXPORT(rt_hw_qspi_init);
rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
{
......
bsp/nuvoton/libraries/ma35/rtt_port/drv_rtp.c
浏览文件 @ 0d1c709f
......@@ -11,12 +11,11 @@
#include <rtconfig.h>
#if !defined(USE_MA35D1_SUBM)
#if defined(BSP_USING_RTP) && defined(RT_USING_DFS)
#define LOG_TAG "drv.rtp"
#undef DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_LEVEL LOG_LVL_INFO
#define DBG_COLOR
#include <rtdbg.h>
......@@ -28,17 +27,12 @@
#include <sys/stat.h>
#include <sys/statfs.h>
#define RTP_USING_AT_STARTUP
#include "drv_sspcc.h"
/* Link to rtthread.bin in ma35-rtp folder. */
#define PATH_RTP_INCBIN "..//ma35-rtp//rtthread.bin"
#define READ_BLOCK_SIZE 128
#define REGION_ADDR_SRAM0 0x24000000
#define REGION_ADDR_DDR (0x80020000|UNCACHEABLE)
#define REGION_MAXSIZE_SRAM0 (128*1024)
#define REGION_MAXSIZE_DDR (4*1024*1024-REGION_MAXSIZE_SRAM0)
#define REGION_MAXSIZE_LIMIT (REGION_MAXSIZE_SRAM0+REGION_MAXSIZE_DDR)
#if !defined(PATH_RTP_FW_FILE)
#define PATH_RTP_FW_FILE "/mnt/sd1p0/rtp.bin"
......@@ -106,7 +100,7 @@ exit_nu_rtp_load_from_memory:
}
#endif
rt_weak void nu_rtp_sspcc_setup(void)
RT_WEAK void nu_rtp_sspcc_setup(void)
{
SSPCC_SET_REALM(SSPCC_UART16, SSPCC_SSET_SUBM);
......@@ -216,7 +210,7 @@ int nu_rtp_load_run(int argc, char *argv[])
if (!szFilePath || nu_rtp_load_from_file(szFilePath) < 0)
return -1;
rt_kprintf("Loaded %s, then run...\n", szFilePath);
LOG_I("Loaded %s, then run...", szFilePath);
nu_rtp_start();
......@@ -227,11 +221,11 @@ MSH_CMD_EXPORT(nu_rtp_load_run, load rtp code then run);
int rt_hw_rtp_init(void)
{
int fw_size;
fw_size = (int)((char *)&incbin_rtp_end - (char *)&incbin_rtp_start);
rt_kprintf("INCBIN RTP Start = %p\n", &incbin_rtp_start);
rt_kprintf("INCBIN RTP Size = %p\n", fw_size);
#if defined(RTP_USING_AT_STARTUP)
int fw_size = (int)((char *)&incbin_rtp_end - (char *)&incbin_rtp_start);
LOG_I("INCBIN RTP Start = %p", &incbin_rtp_start);
LOG_I("INCBIN RTP Size = %p", fw_size);
#endif
/* Enable RTP and reset M4 reset */
nu_rtp_init();
......@@ -247,4 +241,4 @@ int rt_hw_rtp_init(void)
}
INIT_BOARD_EXPORT(rt_hw_rtp_init);
#endif //#if defined(USE_MA35D1_SUBM)
#endif //#if defined(BSP_USING_RTP)
bsp/nuvoton/libraries/ma35/rtt_port/drv_sdio.c
浏览文件 @ 0d1c709f
......@@ -59,12 +59,12 @@ typedef struct nu_sdh *nu_sdh_t;
/* Private variables ------------------------------------------------------------*/
#if defined(BSP_USING_SDH0)
rt_align(SDH_ALIGN_LEN)
ALIGN(SDH_ALIGN_LEN)
static uint8_t g_au8CacheBuf_SDH0[SDH_BUFF_SIZE];
#endif
#if defined(BSP_USING_SDH1)
rt_align(SDH_ALIGN_LEN)
ALIGN(SDH_ALIGN_LEN)
static uint8_t g_au8CacheBuf_SDH1[SDH_BUFF_SIZE];
#endif
......@@ -481,7 +481,7 @@ static void nu_sdh_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
}
}
rt_hw_cpu_dcache_clean_inv((void *)data.dest, size);
rt_hw_cpu_dcache_clean_and_invalidate((void *)data.dest, size);
req->cmd->err = nu_sdh_send_command(sdh->base, &cmd, &data);
rt_hw_cpu_dcache_invalidate((void *)data.dest, size);
......@@ -766,7 +766,7 @@ void nu_sdh_host_initial(nu_sdh_t sdh)
nu_sdh_irq_update(host, 1);
/* ready to change */
mmcsd_change(host);
//mmcsd_change(host);
}
void nu_sd_attach(void)
......
bsp/nuvoton/libraries/ma35/rtt_port/drv_ssmcc.c 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#include "rtthread.h"
#if defined(BSP_USING_SSMCC)
#include "drv_common.h"
rt_err_t nu_ssmcc_init(void)
{
CLK->APBCLK2 |= CLK_APBCLK2_SSMCCEN_Msk;
/* set region 0 to secure region, non-secure and m4 all can access */
SSMCC_SetRegion0(SSMCC_SECURE_READ | SSMCC_SECURE_WRITE | SSMCC_NONSECURE_READ | SSMCC_NONSECURE_WRITE | SSMCC_M4NS_READ | SSMCC_M4NS_WRITE);
return RT_EOK;
}
#endif //#if defined(BSP_USING_SSMCC)
bsp/nuvoton/libraries/ma35/rtt_port/drv_ssmcc.h 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#ifndef __DRV_SSMCC_H__
#define __DRV_SSMCC_H__
rt_err_t nu_ssmcc_init(void);
#endif /* __DRV_SSMCC_H__ */
bsp/nuvoton/libraries/ma35/rtt_port/drv_sspcc.c 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#include "rtthread.h"
#if defined(BSP_USING_SSPCC)
#include "drv_common.h"
rt_err_t nu_sspcc_init(void)
{
int i, j;
/* Enable SSPCC clock. */
CLK->APBCLK2 |= CLK_APBCLK2_SSPCCEN_Msk;
/* Assign all SRAM1 capacity to TZNS. */
SSPCC->SRAMSB = 0;
/* Set all GPIO security set to TZNS. */
for (i = 0; i < 16; i++)
{
for (j = 0; j < 14; j++)
{
SSPCC_SetRealm_GPIO(GPIO_BASE + (j * 0x40), i, SSPCC_SSET_TZNS);
}
}
return RT_EOK;
}
#endif //#if defined(BSP_USING_SSPCC)
bsp/nuvoton/libraries/ma35/rtt_port/drv_sspcc.h 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#ifndef __DRV_SSPCC_H__
#define __DRV_SSPCC_H__
#include "rtthread.h"
#define SSPCC_SET_REALM(IP, REALM) \
do { \
rt_kprintf("Set %s realm to %s(%d)\n", #IP, #REALM, REALM); \
SSPCC_SetRealm(IP, REALM); \
rt_kprintf("Get %s realm is %d ....%s\n", #IP, SSPCC_GetRealm(IP), (SSPCC_GetRealm(IP)==REALM)?"Success":"Failure"); \
} while(0)
#define SSPCC_SET_GPIO_REALM(PORT, PIN, REALM) \
do { \
rt_kprintf("Set %s%s realm to %s(%d)\n", #PORT, #PIN, #REALM, REALM); \
SSPCC_SetRealm_GPIO((uint32_t)PORT, PIN, REALM); \
rt_kprintf("Get %s%s realm is %d ....%s\n", #PORT, #PIN, SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN), (SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN)==REALM)?"Success":"Failure"); \
} while(0)
rt_err_t nu_sspcc_init(void);
#endif /* __DRV_SSPCC_H__ */
bsp/nuvoton/libraries/ma35/rtt_port/drv_sys.c
浏览文件 @ 0d1c709f
......@@ -15,6 +15,13 @@
#include "drv_sys.h"
#include <stdio.h>
#define LOG_TAG "drv.sys"
#undef DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_COLOR
#include <rtdbg.h>
#define DEF_RAISING_CPU_FREQUENCY
//Dont enable #define DEF_RAISING_CPU_VOLTAGE
......@@ -80,14 +87,14 @@ void nu_sys_check_register(S_NU_REG *psNuReg)
{
vu32 vc32RegValue = *((vu32 *)psNuReg->vu32RegAddr);
vu32 vc32BMValue = vc32RegValue & psNuReg->vu32BitMask;
rt_kprintf("[%3s] %32s(0x%08x) %24s(0x%08x): 0x%08x(AndBitMask:0x%08x)\n",
(psNuReg->vu32Value == vc32BMValue) ? "Ok" : "!OK",
psNuReg->szVName,
psNuReg->vu32Value,
psNuReg->szRegName,
psNuReg->vu32RegAddr,
vc32RegValue,
vc32BMValue);
LOG_I("[%3s] %32s(0x%08x) %24s(0x%08x): 0x%08x(AndBitMask:0x%08x)\n",
(psNuReg->vu32Value == vc32BMValue) ? "Ok" : "!OK",
psNuReg->szVName,
psNuReg->vu32Value,
psNuReg->szRegName,
psNuReg->vu32RegAddr,
vc32RegValue,
vc32BMValue);
psNuReg++;
}
}
......@@ -122,7 +129,7 @@ static int nu_tempsen_get_value()
count = 0;
temp = (double)((SYS->TSENSRFCR & 0x0FFF0000) >> 16) * 274.3531 / 4096.0 - 93.3332;
snprintf(sztmp, sizeof(sztmp), "Temperature: %.1f\n", temp);
rt_kprintf("%s", sztmp);
LOG_I("%s", sztmp);
}
// Clear Valid bit
......@@ -142,7 +149,7 @@ static int nu_tempsen_go(void)
if (err != RT_EOK)
{
rt_kprintf("set %s idle hook failed!\n", __func__);
LOG_E("set %s idle hook failed!\n", __func__);
return -1;
}
......@@ -153,32 +160,51 @@ static int nu_tempsen_go(void)
//INIT_APP_EXPORT(nu_tempsen_go);
MSH_CMD_EXPORT(nu_tempsen_go, go tempsen);
#define REG_SYS_CHIPCFG (SYS_BASE + 0x1F4)
uint32_t nu_chipcfg_ddrsize(void)
{
uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG);
return ((u32ChipCfg & 0xF0000) != 0) ? (1 << ((u32ChipCfg & 0xF0000) >> 16)) << 20 : 0;
}
void nu_chipcfg_dump(void)
{
uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG);
uint32_t u32ChipCfg_DDRSize = ((u32ChipCfg & 0xF0000) != 0) ? 1 << ((u32ChipCfg & 0xF0000) >> 16) : 0;
uint32_t u32ChipCfg_DDRType = ((u32ChipCfg & 0x8000) >> 15);
LOG_I("CHIPCFG: 0x%08x ", u32ChipCfg);
LOG_I("DDR SDRAM Size: %d MB", u32ChipCfg_DDRSize);
LOG_I("MCP DDR TYPE: %s", u32ChipCfg_DDRSize ? (u32ChipCfg_DDRType ? "DDR2" : "DDR3/3L") : "Unknown");
}
void nu_clock_dump(void)
{
rt_kprintf("HXT: %d Hz\n", CLK_GetHXTFreq());
rt_kprintf("LXT: %d Hz\n", CLK_GetLXTFreq());
rt_kprintf("CAPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(CAPLL), CLK_GetPLLOpMode(CAPLL));
rt_kprintf("DDRPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(DDRPLL), CLK_GetPLLOpMode(DDRPLL));
rt_kprintf("APLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(APLL), CLK_GetPLLOpMode(APLL));
rt_kprintf("EPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(EPLL), CLK_GetPLLOpMode(EPLL));
rt_kprintf("VPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(VPLL), CLK_GetPLLOpMode(VPLL));
rt_kprintf("M4-CPU: %d Hz\n", CLK_GetCPUFreq());
rt_kprintf("SYSCLK0: %d Hz\n", CLK_GetSYSCLK0Freq());
rt_kprintf("SYSCLK1: %d Hz\n", CLK_GetSYSCLK1Freq());
rt_kprintf("HCLK0: %d Hz\n", CLK_GetHCLK0Freq());
rt_kprintf("HCLK1: %d Hz\n", CLK_GetHCLK1Freq());
rt_kprintf("HCLK2: %d Hz\n", CLK_GetHCLK2Freq());
rt_kprintf("HCLK3: %d Hz\n", CLK_GetHCLK3Freq());
rt_kprintf("PCLK0: %d Hz\n", CLK_GetPCLK0Freq());
rt_kprintf("PCLK1: %d Hz\n", CLK_GetPCLK1Freq());
rt_kprintf("PCLK2: %d Hz\n", CLK_GetPCLK2Freq());
rt_kprintf("PCLK3: %d Hz\n", CLK_GetPCLK3Freq());
rt_kprintf("PCLK4: %d Hz\n", CLK_GetPCLK4Freq());
LOG_I("HXT: %d Hz", CLK_GetHXTFreq());
LOG_I("LXT: %d Hz", CLK_GetLXTFreq());
LOG_I("CAPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(CAPLL), CLK_GetPLLOpMode(CAPLL));
LOG_I("DDRPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(DDRPLL), CLK_GetPLLOpMode(DDRPLL));
LOG_I("APLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(APLL), CLK_GetPLLOpMode(APLL));
LOG_I("EPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(EPLL), CLK_GetPLLOpMode(EPLL));
LOG_I("VPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(VPLL), CLK_GetPLLOpMode(VPLL));
LOG_I("M4-CPU: %d Hz", CLK_GetCPUFreq());
LOG_I("SYSCLK0: %d Hz", CLK_GetSYSCLK0Freq());
LOG_I("SYSCLK1: %d Hz", CLK_GetSYSCLK1Freq());
LOG_I("HCLK0: %d Hz", CLK_GetHCLK0Freq());
LOG_I("HCLK1: %d Hz", CLK_GetHCLK1Freq());
LOG_I("HCLK2: %d Hz", CLK_GetHCLK2Freq());
LOG_I("HCLK3: %d Hz", CLK_GetHCLK3Freq());
LOG_I("PCLK0: %d Hz", CLK_GetPCLK0Freq());
LOG_I("PCLK1: %d Hz", CLK_GetPCLK1Freq());
LOG_I("PCLK2: %d Hz", CLK_GetPCLK2Freq());
LOG_I("PCLK3: %d Hz", CLK_GetPCLK3Freq());
LOG_I("PCLK4: %d Hz", CLK_GetPCLK4Freq());
}
const char *szClockName [] =
static const char *szClockName [] =
{
"HXT",
"LXT",
......@@ -202,7 +228,7 @@ void nu_clock_isready(void)
{
if (i == 5 || i == 7 || i == 2) continue;
u32IsReady = CLK_WaitClockReady(1 << i);
rt_kprintf("%s: %s\n", szClockName[i], (u32IsReady == 1) ? "[Stable]" : "[Unstable]");
LOG_I("%s: %s\n", szClockName[i], (u32IsReady == 1) ? "[Stable]" : "[Unstable]");
}
}
......@@ -230,7 +256,7 @@ void nu_clock_raise(void)
}
CLK_SetPLLFreq(VPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 102000000ul);
CLK_SetPLLFreq(APLL, PLL_OPMODE_INTEGER, u32PllRefClk, 160000000ul);
CLK_SetPLLFreq(APLL, PLL_OPMODE_INTEGER, u32PllRefClk, 144000000ul);
CLK_SetPLLFreq(EPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 500000000ul);
/* Waiting clock ready */
......@@ -247,7 +273,9 @@ void nu_clock_raise(void)
else
#endif
{
#if defined(DEF_RAISING_CPU_VOLTAGE)
ma35d1_set_cpu_voltage(CLK_GetPLLClockFreq(SYSPLL), 0x5F);
#endif
CLK_SetPLLFreq(CAPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 800000000ul);
}
......@@ -267,3 +295,74 @@ void nu_clock_raise(void)
#endif
void devmem(int argc, char *argv[])
{
volatile unsigned int u32Addr;
unsigned int value = 0, mode = 0;
if (argc < 2 || argc > 3)
{
goto exit_devmem;
}
if (argc == 3)
{
if (sscanf(argv[2], "0x%x", &value) != 1)
goto exit_devmem;
mode = 1; //Write
}
if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
goto exit_devmem;
else if (u32Addr & (4 - 1))
goto exit_devmem;
if (mode)
{
*((volatile uint32_t *)u32Addr) = value;
}
LOG_I("0x%08x\n", *((volatile uint32_t *)u32Addr));
return;
exit_devmem:
rt_kprintf("Read: devmem <physical address in hex>\n");
rt_kprintf("Write: devmem <physical address in hex> <value in hex format>\n");
return;
}
MSH_CMD_EXPORT(devmem, dump device registers);
void devmem2(int argc, char *argv[])
{
volatile unsigned int u32Addr;
unsigned int value = 0, word_count = 1;
if (argc < 2 || argc > 3)
{
goto exit_devmem;
}
if (argc == 3)
{
if (sscanf(argv[2], "%d", &value) != 1)
goto exit_devmem;
word_count = value;
}
if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
goto exit_devmem;
else if (u32Addr & (4 - 1))
goto exit_devmem;
if (word_count > 0)
{
LOG_HEX("devmem", 16, (void *)u32Addr, word_count * sizeof(rt_base_t));
}
return;
exit_devmem:
rt_kprintf("devmem2: <physical address in hex> <count in dec>\n");
return;
}
MSH_CMD_EXPORT(devmem2, dump device registers);
bsp/nuvoton/libraries/ma35/rtt_port/drv_umctl2.c 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#include "rtthread.h"
#if defined(BSP_USING_UMCTL2)
#include "drv_common.h"
rt_err_t nu_umctl2_init(void)
{
UMCTL2->PCTRL_0 = UMCTL2_PCTRL_0_port_en_Msk; //[0x0490]
UMCTL2->PCTRL_1 = UMCTL2_PCTRL_1_port_en_Msk; //[0x0540]
UMCTL2->PCTRL_2 = UMCTL2_PCTRL_2_port_en_Msk; //[0x05f0]
UMCTL2->PCTRL_3 = UMCTL2_PCTRL_3_port_en_Msk; //[0x06a0]
UMCTL2->PCTRL_4 = UMCTL2_PCTRL_4_port_en_Msk; //[0x0750]
UMCTL2->PCTRL_5 = UMCTL2_PCTRL_5_port_en_Msk; //[0x0800]
UMCTL2->PCTRL_6 = UMCTL2_PCTRL_6_port_en_Msk; //[0x08b0]
UMCTL2->PCTRL_7 = UMCTL2_PCTRL_7_port_en_Msk; //[0x0960]
return RT_EOK;
}
#endif //#if defined(BSP_USING_UMCTL2)
bsp/nuvoton/libraries/ma35/rtt_port/drv_umctl2.h 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#ifndef __DRV_UMCTL2_H__
#define __DRV_UMCTL2_H__
rt_err_t nu_umctl2_init(void);
#endif /* __DRV_UMCTL2_H__*/
bsp/nuvoton/libraries/ma35/rtt_port/drv_usbhost.c
浏览文件 @ 0d1c709f
......@@ -517,7 +517,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_OUT)
{
rt_memcpy(buffer_nonch, buffer, nbytes);
rt_hw_cpu_dcache_clean_inv((void *)buffer_nonch, nbytes);
rt_hw_cpu_dcache_clean_and_invalidate((void *)buffer_nonch, nbytes);
}
}
......
bsp/nuvoton/libraries/ma35/rtt_port/drv_whc.c 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-5 Wayne First version
*
******************************************************************************/
#include <rtconfig.h>
#if defined(BSP_USING_WHC)
#include <rthw.h>
#include "drv_whc.h"
#include "drv_sys.h"
#include "nu_bitutil.h"
/* Private define ---------------------------------------------------------------*/
enum
{
WHC_START = -1,
#if defined(BSP_USING_WHC0)
WHC0_IDX,
#endif
#if defined(BSP_USING_WHC1)
WHC1_IDX,
#endif
WHC_CNT
};
/* Private typedef --------------------------------------------------------------*/
struct nu_whc_priv
{
char *name;
WHC_T *base;
IRQn_Type irqn;
uint32_t rstidx;
rt_device_t psChDev[WHC_CH];
};
typedef struct nu_whc_priv *nu_whc_priv_t;
struct nu_whc
{
struct rt_device dev;
nu_whc_priv_t psPriv;
uint32_t u32WhcChNum;
void *pvTxBuf;
};
typedef struct nu_whc *nu_whc_t;
static struct nu_whc_priv nu_whc_priv_arr [] =
{
#if defined(BSP_USING_WHC0)
{
.name = "whc0",
.base = WHC0,
.irqn = WHC0_IRQn,
.rstidx = WHC0_RST,
},
#endif
#if defined(BSP_USING_WHC1)
{
.name = "whc1",
.base = WHC1,
.irqn = WHC1_IRQn,
.rstidx = WHC1_RST,
},
#endif
}; /* nu_whc_priv */
/**
* All WHC interrupt service routine
*/
static void nu_whc_isr(int vector, void *param)
{
nu_whc_priv_t psNuWhcPriv = (nu_whc_priv_t)param;
volatile uint32_t vu32Intsts = psNuWhcPriv->base->INTSTS;
uint32_t irqidx;
while ((irqidx = nu_ctz(vu32Intsts)) != 32)
{
uint32_t u32IsrBitMask = 1 << irqidx ;
switch (irqidx)
{
/* Process TX-complete interrupt event */
case WHC_INTSTS_TX0IF_Pos:
case WHC_INTSTS_TX1IF_Pos:
case WHC_INTSTS_TX2IF_Pos:
case WHC_INTSTS_TX3IF_Pos:
{
uint32_t u32ChNum = irqidx - WHC_INTSTS_TX0IF_Pos;
rt_device_t device = psNuWhcPriv->psChDev[u32ChNum];
nu_whc_t psWhc = (nu_whc_t)device;
if (device->tx_complete && psWhc->pvTxBuf)
{
device->tx_complete(device, psWhc->pvTxBuf);
psWhc->pvTxBuf = RT_NULL;
}
}
break;
/* Process RX-indicate interrupt event */
case WHC_INTSTS_RX0IF_Pos:
case WHC_INTSTS_RX1IF_Pos:
case WHC_INTSTS_RX2IF_Pos:
case WHC_INTSTS_RX3IF_Pos:
{
uint32_t u32ChNum = irqidx - WHC_INTSTS_RX0IF_Pos;
rt_device_t device = psNuWhcPriv->psChDev[u32ChNum];
if (device->rx_indicate)
{
device->rx_indicate(device, 1);
}
}
break;
default:
break;
}
/* Clear interrupt bit. */
WHC_CLR_INT_FLAG(psNuWhcPriv->base, u32IsrBitMask);
/* Clear served bit */
vu32Intsts &= ~(u32IsrBitMask);
}
}
rt_err_t nu_whc_init(rt_device_t dev)
{
return RT_EOK;
}
rt_err_t nu_whc_open(rt_device_t dev, rt_uint16_t oflag)
{
nu_whc_t psWhc = (nu_whc_t)dev;
nu_whc_priv_t psWhcPriv = psWhc->psPriv;
WHC_ENABLE_INT(psWhcPriv->base, WHC_INTEN_TX0IEN_Msk << psWhc->u32WhcChNum |
WHC_INTEN_RX0IEN_Msk << psWhc->u32WhcChNum);
return RT_EOK;
}
rt_err_t nu_whc_close(rt_device_t dev)
{
nu_whc_t psWhc = (nu_whc_t)dev;
nu_whc_priv_t psWhcPriv = psWhc->psPriv;
WHC_DISABLE_INT(psWhcPriv->base, WHC_INTEN_TX0IEN_Msk << psWhc->u32WhcChNum |
WHC_INTEN_RX0IEN_Msk << psWhc->u32WhcChNum);
return RT_EOK;
}
rt_size_t nu_whc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
nu_whc_t psWhc = (nu_whc_t)dev;
nu_whc_priv_t psWhcPriv = psWhc->psPriv;
if ((sizeof(nu_whc_msg) != size) || ((uint32_t)buffer & 0x3))
goto exit_nu_whc_read;
if (WHC_Recv(psWhcPriv->base, psWhc->u32WhcChNum, (uint32_t *)buffer) < 0)
goto exit_nu_whc_read;
return size;
exit_nu_whc_read:
return 0;
}
rt_size_t nu_whc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
nu_whc_t psWhc = (nu_whc_t)dev;
nu_whc_priv_t psWhcPriv = psWhc->psPriv;
if ((sizeof(nu_whc_msg) != size) || ((uint32_t)buffer & 0x3))
goto exit_nu_whc_write;
psWhc->pvTxBuf = (void *)buffer;
if (WHC_Send(psWhcPriv->base, psWhc->u32WhcChNum, (uint32_t *)buffer) < 0)
goto exit_nu_whc_write;
return size;
exit_nu_whc_write:
return 0;
}
rt_err_t nu_whc_control(rt_device_t dev, int cmd, void *args)
{
return RT_EOK;
}
static rt_err_t whc_register(nu_whc_priv_t psWhcPriv)
{
int i;
char szDevName[16];
for (i = 0; i < WHC_CH; i++)
{
nu_whc_t psWhc;
rt_device_t device = rt_device_create(RT_Device_Class_Miscellaneous, sizeof(struct nu_whc) - sizeof(struct rt_device));
RT_ASSERT(device);
psWhcPriv->psChDev[i] = device;
psWhc = (nu_whc_t)device;
psWhc->psPriv = psWhcPriv;
psWhc->u32WhcChNum = i;
device->type = RT_Device_Class_Miscellaneous;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
device->ops = RT_NULL;
#else
device->init = nu_whc_init;
device->open = nu_whc_open;
device->close = nu_whc_close;
device->read = nu_whc_read;
device->write = nu_whc_write;
device->control = nu_whc_control;
#endif
device->user_data = (void *)psWhcPriv;
rt_snprintf(szDevName, sizeof(szDevName), "%s-%d", psWhcPriv->name, psWhc->u32WhcChNum);
RT_ASSERT(rt_device_register(device, szDevName, RT_DEVICE_FLAG_STANDALONE) == RT_EOK);
}
return RT_EOK;
}
/**
* Hardware Sem Initialization
*/
int rt_hw_whc_init(void)
{
int i;
for (i = (WHC_START + 1); i < WHC_CNT; i++)
{
nu_whc_priv_t psNuWhcPriv = &nu_whc_priv_arr[i];
whc_register(psNuWhcPriv);
rt_hw_interrupt_install(psNuWhcPriv->irqn, nu_whc_isr, psNuWhcPriv, psNuWhcPriv->name);
rt_hw_interrupt_umask(nu_whc_priv_arr[i].irqn);
}
return 0;
}
INIT_BOARD_EXPORT(rt_hw_whc_init);
#endif //#if defined(BSP_USING_WHC)
bsp/nuvoton/libraries/ma35/rtt_port/drv_whc.h 0 → 100644
浏览文件 @ 0d1c709f
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-5 Wayne First version
*
******************************************************************************/
#ifndef __DRV_WHC_H__
#define __DRV_WHC_H__
#include "drv_common.h"
typedef struct
{
uint32_t content[WHC_BUFFER_LEN];
} nu_whc_msg;
typedef nu_whc_msg *nu_whc_msg_t;
#endif /* __DRV_WHC_H__ */
bsp/nuvoton/libraries/ma35/rtt_port/nu_clock_init.c
浏览文件 @ 0d1c709f
......@@ -191,11 +191,11 @@ static void nu_clock_i2s_init(void)
{
#if defined(BSP_USING_I2S0)
CLK_EnableModuleClock(I2S0_MODULE);
CLK_SetModuleClock(I2S0_MODULE, CLK_CLKSEL4_I2S0SEL_SYSCLK1_DIV2, MODULE_NoMsk);
CLK_SetModuleClock(I2S0_MODULE, CLK_CLKSEL4_I2S0SEL_APLL, MODULE_NoMsk);
#endif
#if defined(BSP_USING_I2S1)
CLK_EnableModuleClock(I2S1_MODULE);
CLK_SetModuleClock(I2S1_MODULE, CLK_CLKSEL4_I2S1SEL_SYSCLK1_DIV2, MODULE_NoMsk);
CLK_SetModuleClock(I2S1_MODULE, CLK_CLKSEL4_I2S1SEL_APLL, MODULE_NoMsk);
#endif
}
......@@ -365,6 +365,23 @@ void nu_clock_base_init(void)
}
#endif
static void nu_clock_hwsem_init(void)
{
#if defined(BSP_USING_HWSEM0)
CLK_EnableModuleClock(HWSEM0_MODULE);
#endif
}
static void nu_clock_whc_init(void)
{
#if defined(BSP_USING_WHC0)
CLK_EnableModuleClock(WHC0_MODULE);
#endif
#if defined(BSP_USING_WHC1)
CLK_EnableModuleClock(WHC1_MODULE);
#endif
}
void nu_clock_init(void)
{
#if !defined(USE_MA35D1_SUBM)
......@@ -377,6 +394,8 @@ void nu_clock_init(void)
nu_clock_disp_init();
#endif
nu_clock_whc_init();
nu_clock_hwsem_init();
nu_clock_pdma_init();
nu_clock_gpio_init();
nu_clock_uart_init();
......
bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig
浏览文件 @ 0d1c709f
......@@ -12,6 +12,7 @@ config SOC_SERIES_N9H30
config BSP_USING_MMU
bool "Enable MMU"
select ARCH_ARM_MMU
default y
config BSP_USING_GPIO
......
bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau8822.c
浏览文件 @ 0d1c709f
......@@ -370,9 +370,13 @@ static rt_err_t nau8822_mixer_control(rt_uint32_t ui32Units, rt_uint32_t ui32Val
break;
case AUDIO_MIXER_VOLUME:
{
uint8_t u8DACGAIN = 256 * ui32Value / 100;
I2C_WriteNAU8822(11, u8DACGAIN);
I2C_WriteNAU8822(12, u8DACGAIN);
uint8_t u8GAIN = 256 * ui32Value / 100;
I2C_WriteNAU8822(11, 0x100 | u8GAIN);
I2C_WriteNAU8822(12, 0x100 | u8GAIN);
u8GAIN = 0x3F * ui32Value / 100;
I2C_WriteNAU8822(54, 0x100 | u8GAIN);
I2C_WriteNAU8822(55, 0x100 | u8GAIN);
}
break;
case AUDIO_MIXER_QUERY:
......
bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160.h
浏览文件 @ 0d1c709f
......@@ -1570,7 +1570,7 @@ FOR THE AUTO OFFSET INTERRUPT */
/***********************************************/
/**\name NUMERIC DEFINITIONS*/
/**********************************************/
#define BMG160_INIT_VALUE ((u8)0)
#define BMG160_INIT_VALUE (0)
#define BMG160_GEN_READ_WRITE_DATA_LENGTH ((u8)1)
#define BMG160_X_DATA_LENGTH ((u8)2)
#define BMG160_Y_DATA_LENGTH ((u8)2)
......
bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050.h
浏览文件 @ 0d1c709f
......@@ -709,7 +709,7 @@ delay_func(delay_in_msec)
#define E_BMM050_NULL_PTR ((s8)-127)
#define ERROR ((s8)-1)
#define E_BMM050_OUT_OF_RANGE ((s8)-2)
#define BMM050_NULL ((u8)0)
#define BMM050_NULL (0)
#define E_BMM050_UNDEFINED_MODE (0)
/********************************************/
......
bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.c
浏览文件 @ 0d1c709f
......@@ -248,14 +248,15 @@ static double get_mdps_value(int32_t i32AccelVal)
return 0.0f;
}
static rt_size_t bmx055_fetch_data(rt_sensor_t sensor, void *buf, rt_size_t len)
static rt_ssize_t bmx055_fetch_data(rt_sensor_t sensor, rt_sensor_data_t data, rt_size_t len)
{
struct rt_sensor_data *data = (struct rt_sensor_data *)buf;
RT_ASSERT(data);
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
bma2x2_read_accel_xyzt(&g_sbmx055.accel_xyzt);
data->type = RT_SENSOR_CLASS_ACCE;
data->type = RT_SENSOR_TYPE_ACCE;
/* Report mg */
data->data.acce.x = (int32_t)get_mg_value(g_sbmx055.accel_xyzt.x);
......@@ -263,9 +264,9 @@ static rt_size_t bmx055_fetch_data(rt_sensor_t sensor, void *buf, rt_size_t len)
data->data.acce.z = (int32_t)get_mg_value(g_sbmx055.accel_xyzt.z);
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
bmg160_get_data_XYZI(&g_sbmx055.gyro_xyzi);
data->type = RT_SENSOR_CLASS_GYRO;
data->type = RT_SENSOR_TYPE_GYRO;
/* Report mdps */
data->data.gyro.x = (int32_t)get_mdps_value(g_sbmx055.gyro_xyzi.datax);
......@@ -273,9 +274,9 @@ static rt_size_t bmx055_fetch_data(rt_sensor_t sensor, void *buf, rt_size_t len)
data->data.gyro.z = (int32_t)get_mdps_value(g_sbmx055.gyro_xyzi.dataz);
break;
case RT_SENSOR_CLASS_MAG:
case RT_SENSOR_TYPE_MAG:
bmm050_read_mag_data_XYZ(&g_sbmx055.mag_data);
data->type = RT_SENSOR_CLASS_MAG;
data->type = RT_SENSOR_TYPE_MAG;
/* Report mquass */
data->data.mag.x = g_sbmx055.mag_data.datax;
......@@ -307,15 +308,15 @@ static rt_err_t bmx055_getid(rt_sensor_t sensor, rt_uint8_t *pu8)
{
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
*pu8 = g_sbmx055.accel.chip_id;
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
*pu8 = g_sbmx055.gyro.chip_id;
break;
case RT_SENSOR_CLASS_MAG:
case RT_SENSOR_TYPE_MAG:
*pu8 = g_sbmx055.mag.company_id;
break;
}
......@@ -329,19 +330,19 @@ static rt_err_t bmx055_set_power(rt_sensor_t sensor, rt_uint8_t power_mode)
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
{
switch (power_mode)
{
case RT_SENSOR_POWER_DOWN:
case RT_SENSOR_MODE_POWER_DOWN:
power_ctr = BMA2x2_MODE_STANDBY;
break;
case RT_SENSOR_POWER_NORMAL:
case RT_SENSOR_MODE_POWER_MEDIUM:
power_ctr = BMA2x2_MODE_NORMAL;
break;
case RT_SENSOR_POWER_LOW:
case RT_SENSOR_MODE_POWER_LOW:
power_ctr = BMA2x2_MODE_LOWPOWER1;
break;
......@@ -355,15 +356,15 @@ static rt_err_t bmx055_set_power(rt_sensor_t sensor, rt_uint8_t power_mode)
}
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
{
switch (power_mode)
{
case RT_SENSOR_POWER_DOWN:
case RT_SENSOR_MODE_POWER_DOWN:
power_ctr = BMG160_MODE_DEEPSUSPEND;
break;
case RT_SENSOR_POWER_NORMAL:
case RT_SENSOR_MODE_POWER_MEDIUM:
power_ctr = BMG160_MODE_NORMAL;
break;
......@@ -377,15 +378,15 @@ static rt_err_t bmx055_set_power(rt_sensor_t sensor, rt_uint8_t power_mode)
}
break;
case RT_SENSOR_CLASS_MAG:
case RT_SENSOR_TYPE_MAG:
{
switch (power_mode)
{
case RT_SENSOR_POWER_DOWN:
case RT_SENSOR_MODE_POWER_DOWN:
power_ctr = 0;
break;
case RT_SENSOR_POWER_NORMAL:
case RT_SENSOR_MODE_POWER_MEDIUM:
power_ctr = 1;
break;
......@@ -412,7 +413,7 @@ static rt_err_t bmx055_set_range(rt_sensor_t sensor, rt_uint16_t range)
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
{
idx = find_param_index(range, accel_ranges, sizeof(accel_ranges));
if (bma2x2_set_range(accel_ranges[idx].reg) != 0)
......@@ -422,7 +423,7 @@ static rt_err_t bmx055_set_range(rt_sensor_t sensor, rt_uint16_t range)
}
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
{
idx = find_param_index(range, gyro_ranges, sizeof(gyro_ranges));
if (bmg160_set_range_reg(gyro_ranges[idx].reg) != 0)
......@@ -446,7 +447,7 @@ static rt_err_t bmx055_set_odr(rt_sensor_t sensor, rt_uint16_t odr_hz)
int idx;
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
{
idx = find_param_index(odr_hz, accel_odr, sizeof(accel_odr));
if (bma2x2_set_bw(accel_odr[idx].reg) != 0)
......@@ -454,7 +455,7 @@ static rt_err_t bmx055_set_odr(rt_sensor_t sensor, rt_uint16_t odr_hz)
}
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
{
idx = find_param_index(odr_hz, gyro_odr, sizeof(gyro_odr));
if (bmg160_set_bw(gyro_odr[idx].reg) != 0)
......@@ -462,7 +463,7 @@ static rt_err_t bmx055_set_odr(rt_sensor_t sensor, rt_uint16_t odr_hz)
}
break;
case RT_SENSOR_CLASS_MAG:
case RT_SENSOR_TYPE_MAG:
{
idx = find_param_index(odr_hz, mag_odr, sizeof(mag_odr));
if (bmm050_set_data_rate(mag_odr[idx].reg) != 0)
......@@ -483,8 +484,8 @@ exit_bmx055_set_power:
static rt_err_t bmx055_control(rt_sensor_t sensor, int cmd, void *args)
{
RT_ASSERT(sensor != RT_NULL);
RT_ASSERT(args != RT_NULL);
RT_ASSERT(sensor);
RT_ASSERT(args);
switch (cmd)
{
......@@ -496,7 +497,7 @@ static rt_err_t bmx055_control(rt_sensor_t sensor, int cmd, void *args)
case RT_SENSOR_CTRL_SET_RANGE:
return bmx055_set_range(sensor, (rt_uint32_t)args);
case RT_SENSOR_CTRL_SET_POWER:
case RT_SENSOR_CTRL_SET_POWER_MODE:
return bmx055_set_power(sensor, ((rt_uint32_t)args & 0xff));
case RT_SENSOR_CTRL_SET_ODR:
......@@ -521,14 +522,14 @@ static int rt_hw_bmx055_accel_init(const char *name, struct rt_sensor_config *cf
if (sensor == RT_NULL)
return -(RT_ENOMEM);
sensor->info.type = RT_SENSOR_CLASS_ACCE;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.model = "bmx055_acce";
sensor->info.unit = RT_SENSOR_UNIT_MG;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.range_max = 16000;
sensor->info.range_min = 2000;
sensor->info.period_min = 100;
sensor->info.type = RT_SENSOR_TYPE_ACCE;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.name = "bmx055_acce";
sensor->info.unit = RT_SENSOR_UNIT_MG;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.scale.range_max = 16000;
sensor->info.scale.range_min = 2000;
sensor->info.acquire_min = 100;
rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config));
sensor->ops = &sensor_ops;
......@@ -552,14 +553,14 @@ static int rt_hw_bmx055_gyro_init(const char *name, struct rt_sensor_config *cfg
if (sensor == RT_NULL)
return -(RT_ENOMEM);
sensor->info.type = RT_SENSOR_CLASS_GYRO;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.model = "bmx055_gyro";
sensor->info.unit = RT_SENSOR_UNIT_MDPS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.range_max = 2000;
sensor->info.range_min = 125;
sensor->info.period_min = 100;
sensor->info.type = RT_SENSOR_TYPE_GYRO;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.name = "bmx055_gyro";
sensor->info.unit = RT_SENSOR_UNIT_MDPS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.scale.range_max = 2000;
sensor->info.scale.range_min = 125;
sensor->info.acquire_min = 100;
rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config));
sensor->ops = &sensor_ops;
......@@ -583,14 +584,14 @@ static int rt_hw_bmx055_mag_init(const char *name, struct rt_sensor_config *cfg)
if (sensor == RT_NULL)
return -(RT_ENOMEM);
sensor->info.type = RT_SENSOR_CLASS_MAG;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.model = "bmx055_mag";
sensor->info.unit = RT_SENSOR_UNIT_MGAUSS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.range_max = 25000; // 1uT = 10*mGauss, X/Y: 1300uT=13000mGauss, Z: 2500uT=25000mG
sensor->info.range_min = 0;
sensor->info.period_min = 100;
sensor->info.type = RT_SENSOR_TYPE_MAG;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.name = "bmx055_mag";
sensor->info.unit = RT_SENSOR_UNIT_MGAUSS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.scale.range_max = 25000; // 1uT = 10*mGauss, X/Y: 1300uT=13000mGauss, Z: 2500uT=25000mG
sensor->info.scale.range_min = 0;
sensor->info.acquire_min = 100;
rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config));
sensor->ops = &sensor_ops;
......
bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.h
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......@@ -13,7 +13,8 @@
#ifndef __SENSOR_BMX055_H__
#define __SENSOR_BMX055_H__
#include "sensor.h"
#include "rtdevice.h"
#include "bma2x2.h"
#include "bmm050.h"
#include "bmg160.h"
......
bsp/nuvoton/libraries/nu_packages/Demo/SConscript
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Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
src = Split("""
usbd_hid_dance_mouse.c
slcd_show_tick.c
usbd_cdc_vcom_echo.c
atdev_utils.c
""")
group = DefineGroup('nu_pkgs_demo', src, depend = ['NU_PKG_USING_DEMO'], CPPPATH = CPPPATH)
Return('group')
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......@@ -7,10 +7,6 @@ menu "Nuvoton Packages Config"
bool "Enable demos"
default y
config NU_PKG_USING_LVGL
bool "Enable LVGL demos"
default n
config NU_PKG_USING_BMX055
bool "BMX055 9-axis sensor."
select RT_USING_I2C
......
bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.h
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......@@ -13,7 +13,8 @@
#ifndef __SENSOR_MAX31875_H__
#define __SENSOR_MAX31875_H__
#include "sensor.h"
#include "rtdevice.h"
#include "max31875_c.h"
int rt_hw_max31875_init(const char *name, struct rt_sensor_config *cfg);
......
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