[libcpu][riscv] 添加宏用于区别是否开启FPU，更新ch32v208v-r0 ->ch32v208w-r0，更新注释

bsp/wch/risc-v/Libraries/Kconfig

@@ -14,6 +14,7 @@ config SOC_RISCV_SERIES_CH32V2
 config SOC_RISCV_SERIES_CH32V3
     bool
     select ARCH_RISCV
+    select ARCH_RISCV_FPU
     select SOC_RISCV_FAMILY_CH32
 
 config SOC_FAMILY_CH56X

libcpu/risc-v/ch32/context_gcc.S

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2021-09-09     WCH        the first version
+ * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
 
 #include "cpuport.h"

libcpu/risc-v/ch32/cpuport.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2021-09-09     WCH        the first version
+ * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
 
 #include <rthw.h>

libcpu/risc-v/ch32/interrupt_gcc.S

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2021-09-09     WCH        the first version
+ * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
  
 #include "cpuport.h"

libcpu/risc-v/common/context_gcc.S

@@ -8,6 +8,7 @@
  * 2018/10/28     Bernard      The unify RISC-V porting implementation
  * 2018/12/27     Jesven       Add SMP support
  * 2020/11/20     BalanceTWK   Add FPU support
+ * 2022/12/28     WangShun     Add macro to distinguish whether FPU is supported
  */
 
 #define __ASSEMBLY__
@@ -212,8 +213,11 @@ rt_hw_context_switch_exit:
     csrw mepc, a0
 
     LOAD x1,   1 * REGBYTES(sp)
-
+    #ifdef ARCH_RISCV_FPU
     li    t0, 0x00007800
+    #else
+    li    t0, 0x00001800
+    #endif
     csrw  mstatus, t0
     LOAD a0,   2 * REGBYTES(sp)
     csrs mstatus, a0