- 27 2月, 2023 12 次提交
-
-
由 gaoziyuan 提交于
-
由 csy0225 提交于
-
由 Charles-hit 提交于
-
由 jameszhang 提交于
* [kunlun] support reduce_scatter * uncomment unittest * update xccl to 1.0.10
-
由 Yiqun Liu 提交于
-
由 zhouweiwei2014 提交于
-
由 zhangbo9674 提交于
* add TypeUniquer and IrContext * refine include code * add Type, TypeBase * add built-in type * add bulit-in Float32Type * refine ut * refine code * refine code * delete type_base * rename ImplType to StorageType * rename ImplType to StorageType * add macros util for register type * add macros util for register type * refine name * refine name * change storage manager * add multi_thread for ir_ctx * rwlock_2_spinlock, add REGISTER_TYPE_2_IRCONTEXT * DECLARE_TYPE_UTILITY_FUNCTOR * refine ircontext singleton * del destructor for ParametricStorageManager * refine code * Add necessary logs for debugging * refine ir_context instance * refine type get interface * refine code by comment
-
由 wangshengxiang 提交于
* [XPU] bind op scatter_nd_add * [XPU] add more data type for op: clip, transpose2 & assign_value
-
由 zhaoyingli 提交于
* fix dist_attr in data_parallel in optimization * fix grad_clip pass when pp2 * fix dist_attr
-
由 shaojie_wang 提交于
* register bfloat16 datatype for squared l2 norm * register bfloat16 datatype for softmax with upper triangular mask * register bfloat16 for tril triu cuda kernel
-
由 wangzhen38 提交于
* [mv fleet] mv fleet to distributed * [mv fleet] for ci * [mv fleet] for ci * [mv fleet] solve ci of version
-
由 zhaoyingli 提交于
* fix set_grad_var_shape * recover modify
-
- 26 2月, 2023 2 次提交
-
-
由 limingshu 提交于
* implement of matmul using cublasLt instead of cublas * Update matmul_kernel_impl_via_blasLt.h --------- Co-authored-by: Nzhangbopd <1299246947@qq.com> Co-authored-by: NBo Zhang <105368690+zhangbopd@users.noreply.github.com> Co-authored-by: NLiu Yiqun <liuyiqun01@baidu.com>
-
由 Yiqun Liu 提交于
* Enable matmul + bias fusion in fused_gat_attention. * Add a variable to control whether using fused matmul + bias.
-
- 25 2月, 2023 3 次提交
-
-
由 zhouweiwei2014 提交于
-
由 Vvsmile 提交于
* change outputs and grads from fp16-fp16-comparision and fp16-fp32 comparision * support grad comparision fp16-fp32 * the change of reference dtype only occured from np.float16 to np.float32 * fix the list type can not infer the dtype by attribute dtype by transfer the list to array * adjust the default atol and rtol of float16 to 1e-3 * Polish code * fix error * fix * Polish code * fix the _is_cal_ref and np.float16 * fix the combination of is_calc_ref and np.float16 * remove unuseful codes in op_test.py * fix ci * fix the rtol set in the dygraph checker and eager checker --------- Co-authored-by: NZzSean <18818272991@163.com>
-
由 zyfncg 提交于
* rename elementwise_heaviside to heaviside * delete __init__.py * fix bug
-
- 24 2月, 2023 23 次提交
-
-
由 yunyaoXYY 提交于
-
由 chenxujun 提交于
-
由 Weilong Wu 提交于
* Revert "fixoptminizer _set_auxiliary_var bug (#50335)" This reverts commit c44005f0. * Revert "refine optimizer create accumulators (#50188)" This reverts commit 244e7546. * Revert "fix found_inf bug for custom optimizer (#50158)" This reverts commit 64573f9f. * Revert "refine amp scaler found_inf (#49864)" This reverts commit 382e9a06. * fix code format * fix conflict
-
由 姜永久 提交于
* fix * and others * more ops * reset distribute_fpn and precision_recall * reset fc * modify arange test * modify reshape&reduce * add fill_any and sigmoid_cross_entropy * reset linear_interp_v2 * reset reduce * modify * modify arange * modify cast
-
由 zhoutianzi666 提交于
* allow fall back to fp16 when int8 * refine code * refine code * refine code
-
由 Sławomir Siwek 提交于
* ConvertToFusedOp * change static to inline Co-authored-by: NTomasz Socha <tomasz.socha@intel.com> --------- Co-authored-by: NTomasz Socha <tomasz.socha@intel.com>
-
由 niuliling123 提交于
-
由 Jiabin Yang 提交于
* change amp with to_prim * fix prim amp * fix rules * fix liear * add amp test * add test * disable this test on cpu * disable this test on cpu --------- Co-authored-by: Ncyber-pioneer <chenzhuo@tju.edu.cn>
-
由 Charles-hit 提交于
-
由 Yuanle Liu 提交于
-
由 YUNSHEN XIE 提交于
-
由 HappyHeavyRain 提交于
* support 'backend' in static ops * change bitwise_xx comment in python * change bitwise_xxx comment in python * change 'backend' and 'data_type' in GetExpectedKernelType
-
由 YuanRisheng 提交于
-
由 WangZhen 提交于
* Add bert prim and cinn test
-
由 xiaoguoguo626807 提交于
* support prim test in OpTest * fix cmake * fix op test * fix test_input_spec * disable cinn in reduce_sum unit test * add bfloat16 dtype for sum * add approve rules * polish code * add clear jit program function * convert grad out from tensor to numpy * remove unnecessary code * add only_prim flag * fix flag * fix op test * add attr * fix optest comp inplace error * fix op test * fix op test with guard * add initialization of check_comp flag * fix comp inplace error in op test * rename check_comp with check_prim and add bfloat16 dtype convert * rename comp_op_type to prim_op_type * rename comp to prim * remove useless code * skip ci check for only prim * add no_grad_vars and grad_outputs in prim test * fix var_dict * fix op test for only_prim * fix dy2static bugs * polish some code * temp * modify op test * except cinn test * modify bfp16 * modify pad grad * add pad_grad dtype * start cinn part --------- Co-authored-by: NCharles-hit <wanghao107@baidu.com>
-
由 HongyuJia 提交于
-
由 xiongkun 提交于
-
由 cyber-pioneer 提交于
* fix attrs loss in creating op * add comment * add case * add case * remove unused case setting
-
由 YuanRisheng 提交于
* perfect translated layer * perfect code according comment
-
由 pangengzheng 提交于
* change protobuf version in pslib mode and link libjvm.so fot libps.so * keep protobuf version same with pslib and enable compile with pslib
-
由 ronnywang 提交于
* [XPU] add expand_grad, isnan, meshgrid kernels * update
-
由 zhoutianzi666 提交于
* fix multihead * fix multihead
-
由 Aurelius84 提交于
* [CINN]Enhance CacheKey hash logic by considering input dtypes * add unittest * fix typo * fix typo * fix map.at * fix find * fix test * fix cinn cache key structure realize * using ordered map for attributes * add test by review advice --------- Co-authored-by: Njiangcheng <thisjiang@qq.com>
-