test=develop

* fix: update fpga backend and kernel
test=develop

* style: style fix
test=develop

test=develop

test=develop

* Optimize the transform from Paddle' Tensor to EigenVector, avoiding defining multiple DDim.

* Optimize the compute implementation of several operators.
test=develop

* Optimize the InferShape of several operators.
test=develop

* Remove the new function, resize and CheckPositive in DDim.
test=develop

* Fix a bug in fc_op's InferShape.
test=develop

* update doc:add_operation, model_quantization and support_operation_list, test=document_fix

[LITE][OPENCL] Add 3 kernels of ElementwiseAdd/FusionElemenwiseAddAct op with opencl image format (#2844)

* [LITE][OPENCL] Add 3 kernels of ElementwiseAdd/FuseElementwiseAdd op. test=develop

test=develop

* [LITE][OPENCL][Image]develop 1x1/5x5/7x7 routing in conv_compute ,test=develop

* [LITE][OPENCL][Image]develop 1x1/5x5/7x7 routing in conv_compute ,convert bias filter in prepare for run ,test=develop

* [LITE][OPENCL] remove useless code. test=develop

* [LITE][OPENCL] finish 4 kernel and unit tests of image2d opencl elementwise_mul kernel. test=develop

* [LITE][OPENCL] Fix little bug of ASSERT. test=develop

* [LITE][OPENCL] Fix bug of channel_mul_d2 and d4. test=develop

* add docs

* FIX CXX DEMO MAKEFILE TO SUPPORT MAC COMPILE test=develop

* test=develop

* optimize quant_dequant_fuse_pass, test=develop

* update, test=develop

* update, test=develop

* fix bug for accessing the removed node, test=develop

* set the bias of int8 conv as float, test=develop

* support weight quantization, test=develop

* up, test=develop

* up, test=develop

* up, test=develop

[arm] fix conv_dw leakyRelu compute error

* refactor 5x5s1 dw conv armv8, test=develop

* [ARM] refactor depthwise conv 5x5s1, and support relu6, leakey relu, test=develop

* [ARM] sgemv support fuse relu6 and leakey relu,test=develop

* [ARM] reduce some conv ut case, test=develop

* [ARM] fix 5x5dw conv pick kernel bug, test=develop

* fix code style, test=develop

* [ARM] fix sgemv fuse relu6 bug, test=develop

* [ARM] fix fp32 5x5s1 dw bug, test=develop

* [ARM] fix fp32 5x5 dw conv pick kernel bug, test=develop

* [LITE][OPENCL]develop basic image depthwiseconv,passed loop test,test=develop

* [LITE][OPENCL]log to vlog(4),test=develop

* [LITE][OPENCL]fix depthwise buffer conv kernel name ,test=develop

- modify aligned_matmul kernel for dynamically malloc memory
- fix top_k_avg_pooling kernel to support data whose size is more than cuda shared memory.

* [NPU] reshape x,y,out node in elementwise ops

* [LITE][OPENCL] conv2d_1x1_image, choose simple kernel when in some case. for opencl ,test=develop

* [LITE][OPENCL] conv2d_1x1_image, add looptest ,test=develop

1. add conv_5x5s2_dw to support any padding
2. add 1x1s2pooling impl
3. fix conv dw 3x3 s1p01 bug

test_model_bin support print intermediate tensor.