- 13 2月, 2020 11 次提交
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由 Santa An 提交于
* [LITE][BM] support VGG,Inception,Mobilenet,Darknet, test=develop
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由 huzhiqiang 提交于
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由 cc 提交于
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由 huzhiqiang 提交于
* modify opt name test=develop * fix code style test=develop * test=develop
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由 GaoWei8 提交于
* replace gru RowWiseAdd Eigen with c implementation test=develop
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由 huzhiqiang 提交于
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由 Yuan Shuai 提交于
* [LITE][OPENCL] Add opencl image2d conv3x3. test=develop
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由 cc 提交于
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由 zhupengyang 提交于
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由 zhupengyang 提交于
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由 huzhiqiang 提交于
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- 12 2月, 2020 10 次提交
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由 yiicy 提交于
* [DEMO] add mask detection demo, test=develop * [DEMO] fix ssd detection demo bug, test=develop
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由 Jiaying Zhao 提交于
* [LITE][OPENCL]Add scale kernel. * [LITE][OPENCL]Add scale kernel, format code style.
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由 HappyAngel 提交于
add concat ut, test=develop * fix axis compute, test=develop * add other axis, test=develop * fix ut. test=develop
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由 HappyAngel 提交于
* fix con+relu6/leakyRelu fusion in Fp32, test=develop * note m=397 in sgemv_int8 ut, test=develop * fix ios build error. test=develop
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由 xiaogang 提交于
fix conv_winograd multithreads bug
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由 yiicy 提交于
* [ARM] add 5x5s2 depthwise conv armv8 impl, test=develop * [ARM] add int8 5x5s2 dw conv armv7 impl, test=develop * [ARM] add int8 5x5s2 dw conv impl, test=develop * [ARM] close int8 conv ut, test=develop
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由 yiicy 提交于
[OPENCL] add sigmoid image2d kernel and ut
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由 zhupengyang 提交于
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由 zhupengyang 提交于
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由 xiaogang 提交于
* fix: update fpga backend and kernel test=develop * style: style fix test=develop
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- 11 2月, 2020 3 次提交
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由 Yiqun Liu 提交于
* Optimize the transform from Paddle' Tensor to EigenVector, avoiding defining multiple DDim. * Optimize the compute implementation of several operators. test=develop
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由 Yiqun Liu 提交于
* Optimize the InferShape of several operators. test=develop * Remove the new function, resize and CheckPositive in DDim. test=develop * Fix a bug in fc_op's InferShape. test=develop
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由 huzhiqiang 提交于
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- 10 2月, 2020 4 次提交
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由 xiaogang 提交于
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由 Yuan Shuai 提交于
[LITE][OPENCL] Add 3 kernels of ElementwiseAdd/FusionElemenwiseAddAct op with opencl image format (#2844) * [LITE][OPENCL] Add 3 kernels of ElementwiseAdd/FuseElementwiseAdd op. test=develop
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由 huzhiqiang 提交于
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由 hong19860320 提交于
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- 08 2月, 2020 2 次提交
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由 Yiqun Liu 提交于
test=develop
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由 xiebaiyuan 提交于
* [LITE][OPENCL][Image]develop 1x1/5x5/7x7 routing in conv_compute ,test=develop * [LITE][OPENCL][Image]develop 1x1/5x5/7x7 routing in conv_compute ,convert bias filter in prepare for run ,test=develop
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- 07 2月, 2020 2 次提交
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由 Yuan Shuai 提交于
* [LITE][OPENCL] remove useless code. test=develop * [LITE][OPENCL] finish 4 kernel and unit tests of image2d opencl elementwise_mul kernel. test=develop * [LITE][OPENCL] Fix little bug of ASSERT. test=develop * [LITE][OPENCL] Fix bug of channel_mul_d2 and d4. test=develop
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由 liu zhengxi 提交于
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- 06 2月, 2020 2 次提交
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由 huzhiqiang 提交于
* FIX CXX DEMO MAKEFILE TO SUPPORT MAC COMPILE test=develop * test=develop
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由 juncaipeng 提交于
* optimize quant_dequant_fuse_pass, test=develop * update, test=develop * update, test=develop * fix bug for accessing the removed node, test=develop * set the bias of int8 conv as float, test=develop * support weight quantization, test=develop * up, test=develop * up, test=develop * up, test=develop
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- 05 2月, 2020 1 次提交
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由 HappyAngel 提交于
[arm] fix conv_dw leakyRelu compute error
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- 04 2月, 2020 2 次提交
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由 yiicy 提交于
* refactor 5x5s1 dw conv armv8, test=develop * [ARM] refactor depthwise conv 5x5s1, and support relu6, leakey relu, test=develop * [ARM] sgemv support fuse relu6 and leakey relu,test=develop * [ARM] reduce some conv ut case, test=develop * [ARM] fix 5x5dw conv pick kernel bug, test=develop * fix code style, test=develop * [ARM] fix sgemv fuse relu6 bug, test=develop * [ARM] fix fp32 5x5s1 dw bug, test=develop * [ARM] fix fp32 5x5 dw conv pick kernel bug, test=develop
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由 juncaipeng 提交于
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- 03 2月, 2020 3 次提交
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由 Yuan Shuai 提交于
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由 huzhiqiang 提交于
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由 xiebaiyuan 提交于
* [LITE][OPENCL]develop basic image depthwiseconv,passed loop test,test=develop * [LITE][OPENCL]log to vlog(4),test=develop * [LITE][OPENCL]fix depthwise buffer conv kernel name ,test=develop
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