* add x86 gru&&relu&&sequence_expand_as op test=develop

* checkout if passes match targets and kernels, test=develop

* add pass_utils, test=develop

* fix lite/core/mir/pass_registry.h, test=develop

* improve code styles, test=develop

* fix spell error, test=develop

fix bilinear-interp unit test for more cases

test=develop

add math function: lstm  and selected_rows into lite/x86/math
add selected_rows and rw_lock into lite/fluid
add lstm_cpu_kernel and  lstm_kernel into lite/x86/detail

* add unsqueeze and range op. modify concat op test=develop

* modify exception in range_test_x86

add transpose kernel for cuda

* make passes related to the device type, test=develop

* improve tips, test=develop

add slice op, reshape op,  reshape2 op, squeeze op and squeeze2 op and their unittests for x86

test=develop

* add assign_value op, arm kernel and test, add fluid_type, test=develop

* add hard_sigmoid, test=develop

* use image and new imple to test detection model, delete faster_rcnn_test, test=develop

fix model_optimize_tool error when using host kernel, fix reshape op build error on ios, test=develop (#1984)

* add assign_value op, arm kernel and test, add fluid_type, test=develop

* add hard_sigmoid, test=develop

* add nearest_interp_cuda kernel, test=develop

* add concat op and elementwise_add op

* remove eigen dependency from nearest_interp cuda kernel, test=develop

* free cuda pointers, test=develop

* add calib cuda kernel.

* add unit test for calib cuda kernel. test=develop

* add lite x86 ops for ASR test=develop

* add lite x86 ops for ASR test=develop

* fix x86 ci run test problems test=develop

* fix mkl path for CI test=develop

test=develop

modify reshape2 OP to add shape_tensor input

* modify slice op and add slice test

* modify nearest_polate when align_corners=false (bugfix)

* paddle lite cuda init
can run model with leaky_relu

* add the missing file.
test=develop

* add the load from memory interface.
test=develop

* refine this pr. fix comments
fix ci error
test=develop

* conv impl
fp32:
conv, conv+bais, conv+bias+relu, conv+bias+leaky_relu

int8:
conv, conv+bais+relu(int8 or fp32 output), conv+bias+leaky_relu(int8 or fp32 output)

can run conv+ bias+relu using cxx_api
test=develop

* move the lite/cuda/math to backends/cuda/math
test=develop

* modify slice op and add slice test

* modify slice op bug

* fix attr and refine subgraph pass test=develop

* refine the npu pass functions

* fix test

test=develop

test=develop

* add ops for faster rcnn

* disable test for generate_proposals and roi_align, test=develop

* remove .swp file

* remove log in tensor slice

* finish the unit test for roi_align, test=develop

* add box_clip op and fix tensor slice bug

* remove add four op twice

* rewrite the implement for box_coder and sequence_expand, add faster_rcnn_test, test=develop

* fix test bug of box_clip in x86 server, test=develop

* rewrite multiclass_nms according to fluid, test=develop

* fix param load bug in box_coder and multiclass_nms op, test=develop

* fix value transfor error in multiclass_nms, test=develop

test=develop

* enhance benchmark
* update code format. test=develop

* add ops for faster rcnn

* disable test for generate_proposals and roi_align, test=develop

* remove .swp file

* remove log in tensor slice

* finish the unit test for roi_align, test=develop

* add box_clip op and fix tensor slice bug

* remove add four op twice

* rewrite the implement for box_coder and sequence_expand, add faster_rcnn_test, test=develop

* fix test bug of box_clip in x86 server, test=develop